Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23671

1

T1

20

T2

19

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3316

1

T3

28

T4

4

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20726

1

T1

20

T2

19

T3

148

auto[1]

6261

1

T3

30

T4

14

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	749	1			T3	11		T8	4		T11	2
values[0]	47	1			T191	32		T206	15		-	-
values[1]	708	1			T4	4		T151	1		T129	20
values[2]	2807	1			T4	14		T5	11		T7	2
values[3]	666	1			T3	19		T8	3		T155	1
values[4]	700	1			T11	12		T38	9		T123	14
values[5]	642	1			T3	1		T121	1		T120	13
values[6]	515	1			T12	1		T26	13		T37	8
values[7]	630	1			T12	1		T23	28		T37	3
values[8]	850	1			T3	8		T4	13		T8	14
values[9]	1219	1			T6	18		T24	1		T122	1
minimum	17454	1			T1	20		T2	19		T3	139

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	731	1			T4	4		T38	12		T129	20
values[1]	2753	1			T4	14		T5	11		T7	2
values[2]	610	1			T3	19		T8	3		T129	28
values[3]	710	1			T11	12		T38	9		T123	14
values[4]	743	1			T3	1		T121	1		T120	13
values[5]	409	1			T12	2		T23	10		T26	13
values[6]	710	1			T23	18		T37	3		T120	1
values[7]	784	1			T3	8		T4	13		T8	14
values[8]	1246	1			T6	18		T24	2		T136	11
values[9]	83	1			T11	2		T172	7		T201	10
minimum	18208	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T129	16		T144	14		T131	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	4		T38	12		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T4	14		T5	11		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T23	11		T24	1		T48	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T125	15		T187	2		T194	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	11		T8	2		T129	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T38	9		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T129	11		T32	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T140	1		T155	1		T171	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T121	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T26	13		T37	1		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	2		T23	10		T171	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T120	1		T125	9		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T23	18		T37	2		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	13		T26	6		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	4		T8	8		T139	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T24	1		T136	1		T117	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T6	18		T24	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T11	1		T277	1		T278	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T172	2		T201	1		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17843	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T130	1		T193	4		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	4		T131	2		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T199	7		T175	7		T208	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T166	7		T31	1		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	2		T127	13		T175	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T125	15		T187	21		T194	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	8		T8	1		T129	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	2		T123	13		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	8		T129	11		T32	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	2		T35	4		T196	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T120	12		T30	2		T123	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T37	7		T31	9		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T152	2		T164	16		T279	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T125	12		T158	15		T43	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T37	1		T48	10		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T30	2		T130	8		T125	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	4		T8	6		T36	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T136	10		T117	24		T32	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T120	11		T123	12		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T11	1		T277	3		T278	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T172	5		T201	9		T221	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T130	13		T193	2		T94	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	579	1			T3	11		T8	4		T11	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T172	2		T27	1		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T191	16		T206	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	1		T129	16		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	4		T130	1		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T4	14		T5	11		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T23	11		T24	1		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T155	1		T172	17		T125	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	11		T8	2		T48	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T38	9		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T129	26		T32	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	12		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	1		T121	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	13		T37	1		T38	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T123	1		T48	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T120	1		T31	4		T125	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	1		T23	28		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	13		T26	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	4		T8	8		T139	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T117	17		T130	1		T32	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T6	18		T24	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17332	1			T1	20		T2	19		T3	136
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	1		T117	11		T229	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T172	5		T201	9		T221	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T191	16		T206	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	4		T33	1		T226	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T130	13		T193	2		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T166	7		T31	1		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T199	7		T127	13		T175	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T172	13		T125	15		T187	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	8		T8	1		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T123	13		T194	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	8		T129	24		T32	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T31	7		T44	2		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	12		T30	2		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T37	7		T42	2		T35	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T123	7		T48	9		T211	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T31	2		T125	12		T158	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T37	1		T48	10		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T136	10		T30	2		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	4		T8	6		T165	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T117	13		T130	8		T32	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T120	11		T123	12		T36	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	5		T144	1		T131	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T38	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T4	1		T5	1		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T23	1		T24	1		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T125	16		T187	23		T194	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	11		T8	2		T129	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	3		T38	1		T123	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	9		T129	12		T32	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T140	1		T155	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	1		T121	1		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T26	1		T37	8		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T12	2		T23	1		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T120	1		T125	13		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T23	1		T37	2		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	1		T26	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T3	5		T8	11		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T24	1		T136	11		T117	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T6	1		T24	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T11	2		T277	4		T278	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T172	6		T201	10		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17977	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T130	14		T193	4		T154	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	15		T144	13		T131	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	3		T38	11		T199	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T4	13		T5	10		T9	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T23	10		T48	7		T208	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T125	14		T194	17		T197	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	8		T8	1		T129	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	8		T194	10		T210	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T129	10		T32	13		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T171	12		T172	7		T35	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T48	6		T211	10		T158	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	12		T38	12		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T23	9		T171	13		T152	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T125	8		T158	14		T159	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T23	17		T37	1		T48	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	12		T26	5		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	3		T8	3		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T117	29		T32	2		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T6	17		T120	9		T263	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T278	12		T202	1		T280	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T172	1		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T190	2		T281	12		T20	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T193	2		T94	6		T215	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	558	1			T3	11		T8	4		T11	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T172	6		T27	1		T201	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T191	17		T206	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	1		T129	5		T33	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T130	14		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T4	1		T5	1		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T23	1		T24	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T155	1		T172	14		T125	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	11		T8	2		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	3		T38	1		T123	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	9		T129	26		T32	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	10		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T121	1		T120	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	1		T37	8		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T123	8		T48	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T120	1		T31	5		T125	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T12	1		T23	2		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	1		T26	1		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T3	5		T8	11		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T117	14		T130	9		T32	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T6	1		T24	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17454	1			T1	20		T2	19		T3	139
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T117	13		T13	4		T262	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T172	1		T270	4		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T191	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	15		T33	1		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	3		T193	2		T94	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T4	13		T5	10		T9	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T23	10		T38	11		T199	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T172	16		T125	14		T194	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	8		T8	1		T48	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T38	8		T194	10		T210	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	24		T32	13		T210	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	9		T171	12		T172	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T34	1		T216	9		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	12		T38	12		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	6		T171	13		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T31	1		T125	8		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T23	26		T37	1		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	12		T26	5		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	3		T8	3		T139	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T117	16		T32	2		T199	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	17		T120	9		T263	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10