Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23537

1

T1

20

T2

19

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3450

1

T3

28

T4

17

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21397

1

T1

20

T2

19

T3

150

auto[1]

5590

1

T3

28

T4

27

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	333	1			T123	14		T129	20		T199	18
values[0]	4	1			T282	4		-	-		-	-
values[1]	661	1			T24	1		T136	11		T31	19
values[2]	619	1			T3	19		T4	14		T6	18
values[3]	767	1			T4	13		T121	1		T120	1
values[4]	763	1			T24	1		T26	6		T38	12
values[5]	2947	1			T3	1		T7	2		T8	3
values[6]	748	1			T3	8		T4	4		T151	1
values[7]	580	1			T11	3		T26	13		T122	1
values[8]	675	1			T5	11		T12	1		T24	1
values[9]	958	1			T8	14		T12	1		T23	39
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T3	19		T6	18		T24	1
values[1]	744	1			T4	27		T139	10		T155	1
values[2]	712	1			T121	1		T120	1		T30	5
values[3]	2977	1			T3	1		T7	2		T9	27
values[4]	715	1			T8	3		T11	2		T38	9
values[5]	661	1			T4	4		T26	13		T151	1
values[6]	690	1			T3	8		T11	3		T37	3
values[7]	628	1			T5	11		T8	14		T12	1
values[8]	1072	1			T12	1		T23	28		T37	8
values[9]	63	1			T205	1		T189	19		T244	14
minimum	18012	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	1		T120	10		T32	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	11		T6	18		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	14		T183	1		T131	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	13		T139	10		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T121	1		T120	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	3		T31	3		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T7	2		T9	27		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	1		T140	1		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T38	9		T120	1		T211	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	2		T11	1		T139	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	13		T144	11		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	4		T151	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	1		T172	2		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	4		T37	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	8		T12	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	11		T23	11		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T23	18		T117	2		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T12	1		T23	10		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T244	14		T17	1		T243	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T205	1		T189	15		T268	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17835	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T172	8		T230	11		T282	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T120	11		T32	23		T226	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	8		T136	10		T31	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T131	12		T276	15		T164	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T127	13		T226	13		T207	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T123	12		T32	5		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	2		T31	1		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T11	8		T166	7		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T33	1		T158	15		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T120	12		T211	6		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T11	1		T130	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T130	8		T193	2		T197	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T129	11		T217	15		T80	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	2		T172	5		T41	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	4		T37	1		T31	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	6		T44	2		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T117	24		T48	9		T187	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T123	13		T48	10		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T37	7		T48	2		T125	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T17	1		T243	3		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T189	4		T268	8		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T123	1		T129	16		T199	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T217	9		T168	1		T268	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T24	1		T32	17		T159	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T136	1		T31	12		T172	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	14		T120	10		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	11		T6	18		T129	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T121	1		T120	1		T131	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	13		T30	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T24	1		T26	6		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T140	1		T171	14		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T7	2		T9	27		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T8	2		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	1		T144	11		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	4		T4	4		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T26	13		T172	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	1		T123	1		T172	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T187	1		T195	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	11		T24	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T8	8		T23	18		T117	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	1		T23	21		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T123	13		T129	4		T199	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T217	8		T268	8		T242	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	23		T226	12		T275	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T136	10		T31	7		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T120	11		T15	8		T276	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T3	8		T129	13		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T131	12		T194	8		T175	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	2		T31	1		T165	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	2		T123	12		T32	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T125	12		T33	1		T127	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T11	8		T166	7		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T11	1		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T120	12		T130	8		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	4		T129	11		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	2		T172	5		T41	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T123	7		T172	13		T131	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T187	10		T195	9		T92	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T37	1		T31	2		T117	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	6		T48	10		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T37	7		T48	11		T125	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T24	1		T120	12		T32	27
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	11		T6	1		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	1		T183	1		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	1		T139	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T121	1		T120	1		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	3		T31	3		T165	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T7	2		T9	2		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	1		T140	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T38	1		T120	13		T211	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	2		T11	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	1		T144	1		T130	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T151	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	3		T172	6		T41	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	5		T37	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	11		T12	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T23	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T23	1		T117	1		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	1		T23	1		T37	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T244	1		T17	2		T243	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T205	1		T189	5		T268	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17974	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T172	1		T230	1		T282	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T120	9		T32	13		T226	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	8		T6	17		T31	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	13		T131	13		T159	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	12		T139	9		T226	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T171	12		T32	2		T194	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T30	2		T31	1		T125	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T9	25		T26	5		T38	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T171	13		T33	1		T158	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	8		T211	14		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	1		T139	4		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	12		T144	10		T193	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	3		T129	10		T153	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T172	1		T42	2		T230	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	3		T37	1		T31	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	3		T152	3		T195	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	10		T23	10		T117	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T23	17		T117	1		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T23	9		T38	12		T48	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T244	13		T243	1		T85	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T189	14		T242	1		T283	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T220	3		T20	2		T179	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T172	7		T230	10		T282	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T123	14		T129	5		T199	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T217	9		T168	1		T268	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T24	1		T32	27		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	11		T31	10		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	1		T120	12		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	11		T6	1		T129	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T121	1		T120	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	1		T30	3		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T24	1		T26	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	1		T171	1		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T7	2		T9	2		T10	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	1		T8	2		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T120	13		T144	1		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	5		T4	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	3		T26	1		T172	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	1		T123	8		T172	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T187	11		T195	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T24	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	11		T23	1		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T23	2		T37	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T129	15		T199	10		T194	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T217	8		T242	1		T279	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	13		T159	6		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T31	9		T172	7		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	13		T120	9		T263	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	8		T6	17		T129	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T131	13		T194	10		T168	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	12		T30	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	5		T38	11		T171	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T171	13		T125	8		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T9	25		T38	8		T170	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	1		T139	4		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T144	10		T211	9		T162	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	3		T4	3		T129	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	12		T172	1		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T172	16		T131	11		T86	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T195	7		T208	10		T264	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	10		T37	1		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	3		T23	17		T117	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T23	19		T38	12		T48	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10