Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20983

1

T1

20

T2

19

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

6004

1

T3

9

T4

18

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21204

1

T1

20

T2

19

T3

151

auto[1]

5783

1

T3

27

T4

14

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	378	1			T4	4		T151	1		T31	19
values[0]	19	1			T186	3		T284	16		-	-
values[1]	726	1			T37	8		T139	15		T123	14
values[2]	783	1			T3	19		T8	14		T11	9
values[3]	701	1			T3	1		T5	11		T37	3
values[4]	711	1			T3	8		T12	1		T23	18
values[5]	744	1			T12	1		T26	13		T38	12
values[6]	558	1			T8	3		T11	2		T24	1
values[7]	690	1			T123	8		T48	23		T129	48
values[8]	817	1			T6	18		T11	3		T24	1
values[9]	2928	1			T4	27		T7	2		T9	27
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T3	19		T37	8		T139	5
values[1]	2860	1			T3	1		T5	11		T7	2
values[2]	691	1			T37	3		T120	21		T172	7
values[3]	688	1			T3	8		T12	1		T23	18
values[4]	823	1			T12	1		T26	13		T136	11
values[5]	629	1			T8	3		T11	2		T24	1
values[6]	689	1			T6	18		T123	8		T48	39
values[7]	552	1			T11	3		T24	1		T122	1
values[8]	1032	1			T4	31		T23	11		T151	1
values[9]	127	1			T205	1		T210	23		T197	15
minimum	18179	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	11		T37	1		T139	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T211	11		T44	1		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	8		T123	1		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1561	1			T3	1		T5	11		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	2		T120	10		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T172	2		T132	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T12	1		T23	18		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T121	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T117	31		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T26	13		T136	1		T38	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T24	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	2		T38	13		T32	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	18		T48	7		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T123	1		T48	13		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T24	1		T122	1		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	1		T144	14		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T4	13		T23	11		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	18		T120	1		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T285	1		T243	2		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T205	1		T210	12		T197	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17839	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T139	10		T123	1		T186	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	8		T37	7		T48	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T211	11		T44	2		T197	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	6		T123	12		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1033	1			T11	8		T166	7		T30	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	1		T120	11		T158	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T172	5		T41	13		T127	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T125	2		T158	15		T195	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	4		T30	2		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T117	24		T165	8		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T136	10		T125	12		T131	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	1		T129	17		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T32	5		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	9		T211	2		T131	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T123	7		T48	10		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T92	13		T255	7		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	2		T125	15		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T31	1		T43	11		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T120	12		T31	7		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	3		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T210	11		T197	7		T219	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T123	13		T175	7		T134	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T151	1		T183	1		T43	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	4		T31	12		T131	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T186	3		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	1		T139	5		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T139	10		T123	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	11		T8	8		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	1		T23	10		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	2		T155	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T5	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T12	1		T23	18		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	4		T121	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T117	31		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	13		T38	12		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T11	1		T24	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	2		T136	1		T38	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T129	31		T211	10		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T123	1		T48	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T6	18		T24	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T144	14		T125	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	13		T23	11		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1506	1			T4	14		T7	2		T9	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T43	11		T286	12		T287	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T31	7		T131	12		T199	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T284	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	7		T48	2		T187	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T123	13		T44	2		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	8		T8	6		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	8		T172	13		T211	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	1		T158	6		T207	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T30	2		T41	13		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T120	11		T125	2		T158	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	4		T30	2		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T117	24		T165	8		T129	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	12		T131	2		T199	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T11	1		T152	2		T74	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T136	10		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	17		T211	2		T131	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	7		T48	10		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	9		T127	11		T194	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	2		T125	15		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T31	1		T216	7		T92	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1102	1			T166	7		T120	12		T156	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	11		T37	8		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T211	12		T44	3		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	11		T123	13		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1362	1			T3	1		T5	1		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	2		T120	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T172	6		T132	1		T41	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T23	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T121	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T117	26		T165	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T26	1		T136	11		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	2		T24	1		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	2		T38	1		T32	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T48	10		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T123	8		T48	11		T130	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T24	1		T122	1		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	3		T144	1		T125	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	1		T23	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T4	2		T120	13		T31	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T285	1		T243	4		T20	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T205	1		T210	12		T197	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17971	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T139	1		T123	14		T186	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	8		T139	4		T48	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T211	10		T159	15		T197	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T8	3		T80	4		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1232	1			T5	10		T9	25		T23	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	1		T120	9		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T172	1		T13	4		T212	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T23	17		T26	5		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	3		T30	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T117	29		T129	10		T211	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T26	12		T38	11		T172	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T129	29		T152	3		T159	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T38	12		T32	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	17		T48	6		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	12		T200	2		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T117	1		T144	10		T263	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T144	13		T125	14		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	12		T23	10		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	16		T31	9		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T243	1		T288	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T210	11		T197	7		T219	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T94	13		T224	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T139	9		T186	2		T244	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T151	1		T183	1		T43	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	1		T31	10		T131	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T186	1		T284	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	8		T139	1		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T139	1		T123	14		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	11		T8	11		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T11	9		T23	1		T24	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	2		T155	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	1		T5	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T23	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	5		T121	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T117	26		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T26	1		T38	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	2		T24	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	2		T136	11		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	19		T211	3		T131	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T123	8		T48	11		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T6	1		T24	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	3		T144	1		T125	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	1		T23	1		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1449	1			T4	1		T7	2		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T286	9		T287	11		T238	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T4	3		T31	9		T131	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T186	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T139	4		T48	7		T86	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T139	9		T159	15		T197	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	8		T8	3		T264	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T23	9		T38	8		T172	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T37	1		T158	14		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	10		T212	3		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	17		T26	5		T120	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	3		T30	2		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T117	29		T129	10		T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T26	12		T38	11		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T152	3		T159	3		T74	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T38	12		T172	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	29		T211	9		T131	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	12		T240	12		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T6	17		T117	1		T48	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	13		T125	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	12		T23	10		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1159	1			T4	13		T9	25		T170	24

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10