Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23255

1

T1

20

T2

19

T3

158

auto[ADC_CTRL_FILTER_COND_OUT]

3732

1

T3

20

T4

17

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21392

1

T1

20

T2

19

T3

178

auto[1]

5595

1

T4

14

T7

2

T8

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	283	1			T31	19		T117	25		T205	1
values[0]	19	1			T8	3		T244	5		T192	1
values[1]	640	1			T8	14		T121	1		T31	4
values[2]	2839	1			T5	11		T7	2		T9	27
values[3]	756	1			T3	8		T12	1		T24	1
values[4]	563	1			T23	11		T24	1		T151	1
values[5]	756	1			T26	6		T37	11		T117	2
values[6]	683	1			T4	14		T24	1		T38	13
values[7]	619	1			T11	3		T12	1		T120	1
values[8]	514	1			T4	4		T11	9		T23	10
values[9]	1383	1			T3	20		T4	13		T6	18
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	677	1			T5	11		T8	14		T31	4
values[1]	2867	1			T7	2		T9	27		T10	1
values[2]	706	1			T3	8		T12	1		T24	1
values[3]	549	1			T23	11		T24	1		T151	1
values[4]	819	1			T24	1		T26	6		T37	11
values[5]	627	1			T4	14		T140	1		T129	48
values[6]	601	1			T11	3		T12	1		T120	1
values[7]	665	1			T4	4		T11	9		T23	10
values[8]	1184	1			T3	19		T4	13		T11	2
values[9]	198	1			T3	1		T6	18		T117	25
minimum	18094	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	11		T8	8		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T165	1		T171	13		T230	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T7	2		T9	27		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T123	1		T144	14		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	4		T139	5		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T24	1		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T23	11		T48	8		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T24	1		T151	1		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	6		T37	3		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T24	1		T38	13		T32	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	14		T129	16		T186	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T140	1		T129	15		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T130	1		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T120	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T26	13		T117	17		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	4		T11	1		T23	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T11	1		T122	1		T139	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T3	11		T4	13		T23	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T125	3		T283	11		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T3	1		T6	18		T117	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17845	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T152	4		T159	10		T226	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	6		T31	1		T210	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T165	8		T175	7		T200	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T136	10		T166	7		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T123	13		T130	13		T187	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	4		T240	12		T94	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T120	12		T129	11		T196	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	2		T187	11		T36	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	2		T123	12		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	8		T125	12		T131	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T32	5		T35	4		T197	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T129	4		T158	15		T216	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T129	13		T34	1		T94	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T130	8		T33	1		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	2		T30	2		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T117	13		T194	21		T193	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	8		T32	23		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	1		T211	6		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	8		T31	9		T123	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T125	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T117	11		T48	9		T44	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	3		T8	1		T31	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T152	2		T226	12		T217	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T218	9		T261	1		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T31	12		T117	14		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T8	2		T244	5		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	1		T289	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	8		T121	1		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T123	1		T171	13		T152	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1474	1			T5	11		T7	2		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T165	1		T144	14		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	4		T139	5		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T24	1		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T23	11		T48	8		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T24	1		T151	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T26	6		T37	3		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T117	2		T32	4		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	14		T158	15		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T24	1		T38	13		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T129	16		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T120	1		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	17		T165	1		T171	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	4		T11	1		T23	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T11	1		T26	13		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	515	1			T3	12		T4	13		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T261	9		T290	12		T243	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T31	7		T117	11		T196	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T8	1		T202	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	6		T31	1		T127	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T123	13		T152	2		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T136	10		T166	7		T120	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T165	8		T130	13		T127	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	4		T197	16		T94	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T129	11		T187	10		T196	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	2		T240	12		T134	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T120	12		T30	2		T123	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	8		T125	12		T131	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T32	5		T35	4		T197	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T158	15		T216	7		T86	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T129	13		T34	1		T94	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T129	4		T130	8		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	2		T199	12		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T117	13		T194	21		T200	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	8		T30	2		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	1		T125	2		T211	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T3	8		T31	2		T123	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	1		T8	11		T31	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	9		T171	1		T230	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T7	2		T9	2		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	14		T144	1		T130	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	5		T139	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T24	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T23	1		T48	3		T187	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	1		T151	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T26	1		T37	10		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T24	1		T38	1		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T129	5		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	1		T129	14		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T130	9		T33	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	3		T120	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	1		T117	14		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	1		T11	9		T23	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T11	2		T122	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T3	11		T4	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T125	3		T283	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T3	1		T6	1		T117	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17973	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T152	3		T159	1		T226	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	10		T8	3		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T171	12		T230	10		T200	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T9	25		T120	9		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	13		T223	7		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	3		T139	4		T240	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T38	11		T129	10		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T23	10		T48	7		T262	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T117	1		T172	8		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T26	5		T37	1		T125	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	12		T32	2		T35	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	13		T129	15		T186	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T129	14		T94	6		T221	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T33	1		T158	14		T197	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	2		T199	13		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	12		T117	16		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	3		T23	9		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T139	9		T211	14		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T3	8		T4	12		T23	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T125	2		T283	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T6	17		T117	13		T48	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T8	1		T244	4		T202	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T152	3		T159	9		T226	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T218	1		T261	10		T16	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T31	10		T117	12		T205	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T8	2		T244	1		T192	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T19	3		T289	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	11		T121	1		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T123	14		T171	1		T152	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T5	1		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T165	9		T144	1		T130	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	5		T139	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	1		T24	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T23	1		T48	3		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T24	1		T151	1		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T26	1		T37	10		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T117	1		T32	7		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T158	16		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T24	1		T38	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T129	5		T130	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	3		T120	1		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T117	14		T165	1		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	1		T11	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	2		T26	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	431	1			T3	12		T4	1		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T218	8		T215	5		T243	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T31	9		T117	13		T168	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T8	1		T244	4		T202	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	3		T31	1		T210	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T171	12		T152	3		T159	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T5	10		T9	25		T120	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T144	13		T223	7		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T3	3		T139	4		T197	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T38	11		T129	10		T291	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T23	10		T48	7		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T172	8		T42	2		T195	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T26	5		T37	1		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T117	1		T32	2		T35	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	13		T158	14		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	12		T129	14		T94	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	15		T186	10		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T199	13		T209	1		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T117	16		T171	13		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T4	3		T23	9		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T26	12		T139	9		T125	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T3	8		T4	12		T6	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10