Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23633

1

T1

20

T2

19

T3

170

auto[ADC_CTRL_FILTER_COND_OUT]

3354

1

T3

8

T4

4

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21493

1

T1

20

T2

19

T3

169

auto[1]

5494

1

T3

9

T4

31

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	55	1			T140	1		T292	1		T238	11
values[0]	100	1			T4	13		T30	3		T13	5
values[1]	619	1			T31	10		T123	8		T155	1
values[2]	747	1			T6	18		T11	3		T23	11
values[3]	574	1			T11	9		T12	1		T23	18
values[4]	690	1			T37	8		T172	7		T129	42
values[5]	2894	1			T3	8		T4	14		T5	11
values[6]	734	1			T8	3		T23	10		T117	25
values[7]	726	1			T3	1		T4	4		T24	2
values[8]	506	1			T11	2		T120	13		T139	10
values[9]	1410	1			T3	19		T24	1		T26	13
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	808	1			T6	18		T26	6		T30	3
values[1]	761	1			T11	3		T12	1		T23	11
values[2]	587	1			T11	9		T23	18		T123	13
values[3]	2857	1			T4	14		T7	2		T9	27
values[4]	730	1			T3	8		T8	14		T12	1
values[5]	749	1			T5	11		T8	3		T23	10
values[6]	686	1			T3	1		T4	4		T24	2
values[7]	451	1			T11	2		T26	13		T38	13
values[8]	1051	1			T3	19		T24	1		T136	11
values[9]	304	1			T140	1		T172	30		T158	30
minimum	18003	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T123	1		T48	8		T186	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	18		T26	6		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T12	1		T23	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T155	1		T48	13		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T123	1		T48	7		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T23	18		T129	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T4	14		T7	2		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T37	1		T172	2		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T8	8		T38	12		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	4		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	11		T8	2		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T139	5		T123	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T37	2		T38	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	4		T24	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T38	13		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T26	13		T31	12		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	11		T151	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T24	1		T136	1		T117	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T140	1		T172	17		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T158	15		T200	1		T221	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17845	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T286	10		T293	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T123	7		T48	2		T134	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	2		T31	3		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	2		T120	11		T130	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	10		T165	8		T125	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T123	12		T48	9		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	8		T129	4		T200	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T166	7		T156	13		T157	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T37	7		T172	5		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	6		T129	13		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	4		T30	2		T211	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	1		T117	11		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T123	13		T199	7		T127	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	1		T125	2		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T120	12		T187	10		T194	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	1		T33	1		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T31	7		T130	8		T248	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	8		T131	12		T36	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T136	10		T117	13		T41	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T172	13		T240	12		T134	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T158	15		T221	1		T168	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T286	12		T293	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T140	1		T249	16		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T292	1		T238	5		T294	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T4	13		T13	5		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T30	1		T242	2		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T123	1		T48	8		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	7		T155	1		T125	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T23	11		T120	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	18		T26	6		T48	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	1		T123	1		T48	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	1		T23	18		T165	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	11		T211	11		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	1		T172	2		T129	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T4	14		T5	11		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	4		T12	1		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	2		T23	10		T117	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T27	1		T133	1		T199	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	1		T37	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	4		T24	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	1		T125	3		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T120	1		T139	10		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	427	1			T3	11		T38	13		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T24	1		T26	13		T136	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T249	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T238	6		T294	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T268	14		T296	2		T224	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T30	2		T297	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T123	7		T48	2		T189	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T31	3		T125	12		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	2		T120	11		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	10		T125	15		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T123	12		T48	9		T195	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	8		T165	8		T195	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T129	11		T211	11		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	7		T172	5		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T8	6		T166	7		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T3	4		T30	2		T211	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	1		T117	11		T32	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T199	7		T194	8		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	1		T211	2		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T123	13		T187	10		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	1		T125	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T120	12		T130	8		T194	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T3	8		T172	13		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T136	10		T31	7		T117	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T123	8		T48	3		T186	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	1		T26	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	3		T12	1		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T155	1		T48	11		T165	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T123	13		T48	10		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	9		T23	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T4	1		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	8		T172	6		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	11		T38	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	5		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T8	2		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T139	1		T123	14		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T37	2		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T24	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	2		T38	1		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T26	1		T31	10		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	11		T151	1		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T24	1		T136	11		T117	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T140	1		T172	14		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T158	16		T200	1		T221	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17941	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T286	13		T293	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	7		T186	10		T13	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T6	17		T26	5		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T23	10		T120	9		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	12		T172	7		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	6		T244	14		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T23	17		T129	15		T200	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T4	13		T9	25		T170	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T172	1		T144	10		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	3		T38	11		T117	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T3	3		T30	2		T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	10		T8	1		T23	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T139	4		T199	10		T210	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	1		T38	8		T125	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	3		T139	9		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	12		T33	1		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T26	12		T31	9		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	8		T131	13		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T117	16		T171	12		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T172	16		T240	12		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T158	14		T168	11		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T4	12		T189	14		T244	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T286	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T140	1		T249	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T292	1		T238	7		T294	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T4	1		T13	1		T145	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T30	3		T242	2		T295	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	8		T48	3		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T31	8		T155	1		T125	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	3		T23	1		T120	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	1		T26	1		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T123	13		T48	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	9		T23	1		T165	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T129	12		T211	12		T127	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T37	8		T172	6		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T4	1		T5	1		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	5		T12	1		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	2		T23	1		T117	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	1		T133	1		T199	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T37	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	1		T24	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	2		T125	3		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T120	13		T139	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T3	11		T38	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T24	1		T26	1		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T249	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T238	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T4	12		T13	4		T268	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T48	7		T186	10		T181	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T31	2		T125	8		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T23	10		T120	9		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	17		T26	5		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T48	6		T195	7		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T23	17		T144	23		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T129	10		T211	10		T231	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T172	1		T129	15		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T4	13		T5	10		T8	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	3		T30	2		T211	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T23	9		T117	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T199	10		T194	10		T210	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	1		T38	8		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	3		T139	4		T263	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T125	2		T33	1		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T139	9		T171	13		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T3	8		T38	12		T172	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T26	12		T31	9		T117	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10