Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23703

1

T1

20

T2

19

T3

151

auto[ADC_CTRL_FILTER_COND_OUT]

3284

1

T3

27

T4

13

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21206

1

T1

20

T2

19

T3

178

auto[1]

5781

1

T4

27

T6

18

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	298	1			T171	14		T129	22		T125	21
values[0]	73	1			T210	21		T219	26		T224	16
values[1]	786	1			T23	21		T24	1		T120	13
values[2]	600	1			T23	18		T171	13		T130	1
values[3]	562	1			T3	19		T11	3		T12	1
values[4]	649	1			T6	18		T12	1		T24	1
values[5]	727	1			T3	8		T24	1		T26	13
values[6]	678	1			T4	13		T121	1		T38	9
values[7]	729	1			T11	2		T38	12		T117	2
values[8]	814	1			T3	1		T4	18		T8	17
values[9]	3139	1			T5	11		T7	2		T9	27
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	842	1			T23	21		T24	1		T165	9
values[1]	641	1			T3	19		T23	18		T117	30
values[2]	563	1			T6	18		T11	3		T12	1
values[3]	720	1			T12	1		T24	2		T151	1
values[4]	708	1			T3	8		T26	13		T121	1
values[5]	615	1			T4	13		T11	2		T32	9
values[6]	3032	1			T4	4		T7	2		T8	14
values[7]	764	1			T3	1		T4	14		T5	11
values[8]	868	1			T11	9		T37	8		T139	10
values[9]	159	1			T37	3		T171	14		T187	12
minimum	18075	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T23	21		T165	1		T172	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	1		T13	5		T158	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T23	18		T171	13		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	11		T117	17		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T26	6		T38	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	18		T11	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	1		T205	1		T42	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T24	2		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T26	13		T155	1		T48	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	4		T121	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T186	3		T132	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	13		T11	1		T32	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T4	4		T7	2		T9	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	8		T123	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	1		T4	14		T5	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	2		T140	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T37	1		T129	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T139	10		T125	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T171	14		T187	1		T218	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T37	2		T212	4		T164	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17837	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T31	12		T28	1		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T165	8		T172	5		T32	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T158	15		T199	12		T210	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T34	1		T199	7		T36	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	8		T117	13		T131	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T117	11		T44	2		T35	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	2		T30	2		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	2		T217	10		T221	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	12		T125	17		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	12		T129	13		T131	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	4		T31	1		T172	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T188	3		T134	9		T162	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	1		T32	5		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T166	7		T120	11		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T8	6		T123	7		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	10		T30	2		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	1		T48	9		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T37	7		T129	11		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	8		T125	12		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T187	11		T242	1		T299	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T37	1		T212	4		T164	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	3		T120	12		T31	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T31	7		T300	2		T271	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T171	14		T129	11		T187	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T125	9		T187	1		T212	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T219	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T210	9		T224	9		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T23	21		T120	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T24	1		T31	12		T117	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T23	18		T171	13		T199	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	1		T183	1		T131	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T26	6		T38	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	11		T11	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T151	1		T117	14		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	18		T12	1		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T26	13		T155	1		T48	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	4		T24	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	8		T129	15		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	13		T121	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T38	12		T117	2		T186	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	1		T123	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T3	1		T4	18		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	10		T48	7		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1607	1			T5	11		T7	2		T9	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	1		T37	2		T139	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T129	11		T187	10		T299	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T125	12		T187	11		T212	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T219	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T210	12		T224	7		T301	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T120	12		T165	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T31	7		T117	13		T158	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T199	7		T36	14		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T131	12		T199	12		T194	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T44	2		T34	1		T35	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	8		T11	2		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T117	11		T42	2		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	2		T123	12		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	10		T131	5		T207	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	4		T31	1		T172	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	2		T129	13		T198	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T32	5		T33	1		T197	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T127	11		T195	15		T197	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	1		T123	7		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T136	10		T120	11		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	7		T48	9		T194	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T37	7		T166	7		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	8		T37	1		T131	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T23	2		T165	9		T172	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T24	1		T13	1		T158	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T23	1		T171	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	11		T117	14		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T26	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	1		T11	3		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T151	1		T205	1		T42	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T24	2		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T26	1		T155	1		T48	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	5		T121	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T186	1		T132	1		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	1		T11	2		T32	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T4	1		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T8	11		T123	8		T130	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	1		T4	1		T5	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	2		T140	1		T155	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	8		T129	12		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	9		T139	1		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T171	1		T187	12		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T37	2		T212	5		T164	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18003	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T31	10		T28	1		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T23	19		T172	1		T144	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	4		T158	14		T199	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T23	17		T171	12		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	8		T117	16		T131	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	5		T38	12		T117	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T6	17		T30	2		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T42	2		T159	6		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	16		T211	9		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T26	12		T48	19		T129	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	3		T38	8		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T186	2		T188	1		T244	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	12		T32	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T4	3		T9	25		T38	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	3		T86	12		T94	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	13		T5	10		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	1		T48	6		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T129	10		T158	14		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	9		T125	8		T131	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T171	13		T218	8		T242	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T37	1		T212	3		T164	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T91	1		T260	2		T219	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T31	9		T271	5		T224	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T171	1		T129	12		T187	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T125	13		T187	12		T212	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T219	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T210	13		T224	8		T301	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T23	2		T120	13		T165	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	1		T31	10		T117	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T23	1		T171	1		T199	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T130	1		T183	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T26	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	11		T11	3		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T151	1		T117	12		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T12	1		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	1		T155	1		T48	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	5		T24	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T48	3		T129	14		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	1		T121	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T38	1		T117	1		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	2		T123	8		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T3	1		T4	2		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	13		T48	10		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1434	1			T5	1		T7	2		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	9		T37	2		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T171	13		T129	10		T243	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T125	8		T212	3		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T219	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T210	8		T224	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T23	19		T172	1		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T31	9		T117	16		T13	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T23	17		T171	12		T199	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T131	13		T199	13		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T26	5		T38	12		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T3	8		T31	1		T211	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T117	13		T42	2		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T6	17		T30	2		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T26	12		T48	12		T144	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	3		T31	1		T172	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	7		T129	14		T198	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	12		T38	8		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T38	11		T117	1		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T195	7		T226	9		T200	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	16		T120	9		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	4		T48	6		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T5	10		T9	25		T170	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T37	1		T139	9		T131	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10