Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23617

1

T1

20

T2

19

T3

170

auto[ADC_CTRL_FILTER_COND_OUT]

3370

1

T3

8

T4

4

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21485

1

T1

20

T2

19

T3

169

auto[1]

5502

1

T3

9

T4

31

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	371	1			T3	19		T24	1		T140	1
values[0]	68	1			T4	13		T145	1		T79	1
values[1]	656	1			T30	3		T31	10		T123	8
values[2]	771	1			T6	18		T11	3		T23	11
values[3]	630	1			T11	9		T12	1		T23	18
values[4]	586	1			T37	8		T172	7		T129	22
values[5]	2920	1			T3	8		T4	14		T7	2
values[6]	809	1			T5	11		T8	3		T23	10
values[7]	697	1			T3	1		T4	4		T24	2
values[8]	461	1			T11	2		T120	13		T31	19
values[9]	1086	1			T26	13		T136	11		T38	13
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	580	1			T4	13		T6	18		T26	6
values[1]	766	1			T11	3		T12	1		T23	11
values[2]	571	1			T11	9		T23	18		T123	13
values[3]	2849	1			T4	14		T7	2		T9	27
values[4]	727	1			T3	8		T8	14		T12	1
values[5]	753	1			T5	11		T8	3		T23	10
values[6]	723	1			T3	1		T4	4		T24	2
values[7]	422	1			T11	2		T26	13		T38	13
values[8]	1203	1			T3	19		T24	1		T136	11
values[9]	163	1			T140	1		T172	30		T158	30
minimum	18230	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	13		T123	1		T48	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	18		T26	6		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	1		T12	1		T23	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T155	1		T48	13		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T123	1		T48	7		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T23	18		T129	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T4	14		T7	2		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	1		T172	2		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	8		T38	12		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	4		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	11		T8	2		T23	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	5		T27	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	1		T37	2		T38	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	4		T24	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T38	13		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T26	13		T31	12		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T3	11		T151	1		T131	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T24	1		T136	1		T117	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T140	1		T172	17		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T158	15		T221	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17902	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T214	14		T184	13		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T123	7		T48	2		T189	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	2		T31	3		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	2		T120	11		T130	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	10		T165	8		T125	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T123	12		T48	9		T189	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	8		T129	4		T200	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T166	7		T156	13		T157	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T37	7		T172	5		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	6		T129	13		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	4		T30	2		T211	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T117	11		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T199	7		T127	11		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	1		T125	2		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	12		T123	13		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T33	1		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T31	7		T130	8		T248	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	8		T131	12		T36	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T136	10		T117	13		T41	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T172	13		T240	12		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T158	15		T221	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T214	15		T271	5		T286	24

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	11		T140	1		T172	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T24	1		T41	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T4	13		T145	1		T79	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T242	2		T295	1		T297	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T123	1		T48	8		T186	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	1		T31	7		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	1		T23	11		T120	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	18		T26	6		T48	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T123	1		T48	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	1		T23	18		T165	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	11		T211	11		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	1		T172	2		T153	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T4	14		T7	2		T8	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	4		T12	1		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T8	2		T23	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T30	3		T27	1		T199	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	1		T37	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	4		T24	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	1		T125	3		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	1		T31	12		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T38	13		T151	1		T131	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T26	13		T136	1		T117	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T3	8		T172	13		T240	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	13		T236	14		T276	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T268	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T297	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T123	7		T48	2		T189	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	2		T31	3		T125	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	2		T120	11		T130	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	10		T125	15		T131	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T123	12		T48	9		T195	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	8		T165	8		T129	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T129	11		T211	11		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	7		T172	5		T197	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T8	6		T166	7		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	4		T211	4		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T117	11		T32	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T30	2		T199	7		T210	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	1		T211	2		T44	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T123	13		T187	10		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T11	1		T125	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T120	12		T31	7		T130	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T131	12		T36	14		T197	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	10		T117	13		T158	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	1		T123	8		T48	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T26	1		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	3		T12	1		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T155	1		T48	11		T165	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T123	13		T48	10		T205	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	9		T23	1		T129	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T4	1		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	8		T172	6		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	11		T38	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	5		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	1		T8	2		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T139	1		T27	1		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T37	2		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	1		T24	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T38	1		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T26	1		T31	10		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T3	11		T151	1		T131	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T24	1		T136	11		T117	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T140	1		T172	14		T240	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T158	16		T221	2		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17992	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T214	16		T184	1		T271	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	12		T48	7		T186	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	17		T26	5		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T23	10		T120	9		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	12		T172	7		T144	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T48	6		T244	14		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T23	17		T129	15		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T4	13		T9	25		T170	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T172	1		T34	1		T153	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	3		T38	11		T117	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	3		T30	2		T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	10		T8	1		T23	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T139	4		T199	10		T210	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	1		T38	8		T125	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	3		T139	9		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T38	12		T33	1		T210	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T26	12		T31	9		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	8		T131	13		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T117	16		T171	12		T230	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T172	16		T240	12		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T158	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T13	4		T181	15		T244	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T214	13		T184	12		T271	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	11		T140	1		T172	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	1		T41	14		T236	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T4	1		T145	1		T79	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	2		T295	1		T297	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T123	8		T48	3		T186	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T30	3		T31	8		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	3		T23	1		T120	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	1		T26	1		T48	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T123	13		T48	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	9		T23	1		T165	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T129	12		T211	12		T127	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	8		T172	6		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T4	1		T7	2		T8	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	5		T12	1		T155	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	1		T8	2		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	3		T27	1		T199	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	1		T37	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	1		T24	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	2		T125	3		T33	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T120	13		T31	10		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T38	1		T151	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T26	1		T136	11		T117	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	8		T172	16		T240	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T215	7		T276	16		T302	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T4	12		T268	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T303	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	7		T186	10		T13	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T31	2		T125	8		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T23	10		T120	9		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	17		T26	5		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T48	6		T195	7		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T23	17		T129	15		T144	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T129	10		T211	10		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T172	1		T153	9		T197	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T4	13		T8	3		T9	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T3	3		T211	5		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	10		T8	1		T23	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	2		T199	10		T210	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	1		T38	8		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	3		T139	4		T194	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T125	2		T33	1		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T31	9		T139	9		T171	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T38	12		T131	13		T159	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T26	12		T117	16		T171	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10