Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T23	2		T120	13		T165	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T24	1		T31	10		T117	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T23	1		T171	1		T41	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	11		T130	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	1		T26	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T11	3		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	1		T144	1		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T24	2		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T26	1		T155	1		T129	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	5		T122	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T117	1		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	1		T121	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T4	1		T7	2		T9	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T8	11		T123	8		T130	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T3	1		T4	1		T5	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	2		T140	1		T48	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	8		T129	12		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	9		T139	1		T125	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T37	2		T171	1		T187	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T212	5		T220	8		T164	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T23	19		T172	1		T32	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T31	9		T117	16		T144	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	17		T171	12		T34	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	8		T131	13		T194	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T26	5		T38	12		T35	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	17		T30	2		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T144	13		T42	2		T159	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T125	16		T211	9		T210	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	12		T129	14		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	3		T38	8		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T117	1		T186	2		T197	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	12		T32	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T4	3		T9	25		T38	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	3		T86	12		T94	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	13		T5	10		T120	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T8	1		T48	6		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T129	10		T158	14		T223	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	9		T125	8		T131	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T37	1		T171	13		T218	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T212	3		T220	6		T164	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T37	2		T187	11		T218	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T219	14		T179	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T210	13		T178	11		T222	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T23	2		T120	13		T165	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	1		T31	10		T117	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T171	1		T199	8		T36	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T183	1		T131	13		T199	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	1		T23	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	11		T11	3		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	1		T44	3		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	5		T6	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	1		T155	1		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	1		T122	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T129	14		T186	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	1		T121	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	2		T38	1		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T123	8		T130	14		T34	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	1		T4	2		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	13		T48	10		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T5	1		T7	2		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T11	9		T139	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T37	1		T218	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T219	12		T179	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T210	8		T178	12		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T23	19		T172	1		T32	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T31	9		T117	16		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T171	12		T199	10		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T131	13		T199	13		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T23	17		T26	5		T38	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	8		T31	1		T211	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T42	2		T221	1		T225	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	3		T6	17		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	12		T144	13		T131	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T31	1		T48	12		T172	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	14		T186	2		T198	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	12		T38	8		T48	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	11		T117	1		T195	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T195	7		T226	9		T200	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	16		T120	9		T139	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	4		T48	6		T194	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T5	10		T9	25		T170	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T139	9		T125	8		T131	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10