Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23299

1

T1

20

T2

19

T3

178

auto[ADC_CTRL_FILTER_COND_OUT]

3688

1

T4

27

T5

11

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20717

1

T1

20

T2

19

T3

150

auto[1]

6270

1

T3

28

T4

17

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	8	1			T165	1		T159	7		-	-
values[0]	14	1			T140	1		T227	1		T228	12
values[1]	745	1			T37	3		T136	11		T120	13
values[2]	744	1			T4	13		T23	11		T38	12
values[3]	588	1			T12	1		T23	18		T37	8
values[4]	736	1			T3	1		T8	3		T12	1
values[5]	722	1			T3	19		T4	14		T24	1
values[6]	627	1			T120	1		T31	4		T117	30
values[7]	712	1			T6	18		T8	14		T24	1
values[8]	2863	1			T3	8		T5	11		T7	2
values[9]	1296	1			T4	4		T122	1		T38	13
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T4	13		T37	3		T136	11
values[1]	716	1			T38	21		T123	13		T171	14
values[2]	723	1			T12	2		T23	29		T24	1
values[3]	635	1			T3	1		T8	3		T30	8
values[4]	769	1			T3	19		T4	14		T24	1
values[5]	643	1			T31	4		T117	32		T129	22
values[6]	2819	1			T6	18		T7	2		T8	14
values[7]	831	1			T3	8		T5	11		T11	11
values[8]	768	1			T38	13		T155	1		T165	1
values[9]	279	1			T4	4		T172	30		T129	48
minimum	17956	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T120	1		T117	14		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	13		T37	2		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	1		T127	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T38	21		T171	14		T194	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T23	29		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T37	1		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	1		T30	1		T32	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T8	2		T30	3		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	11		T24	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	14		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T117	2		T129	11		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T31	3		T117	17		T125	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T6	18		T7	2		T8	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	1		T24	1		T26	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	4		T11	1		T23	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	11		T11	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T38	13		T155	1		T172	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T165	1		T130	1		T32	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T4	4		T195	11		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T172	17		T129	31		T209	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17823	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T120	12		T117	11		T42	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	1		T136	10		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T123	12		T127	11		T208	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T194	8		T193	2		T198	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	10		T34	1		T195	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T37	7		T125	2		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	2		T32	5		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	1		T30	2		T123	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	8		T33	1		T196	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T130	8		T131	2		T199	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T129	11		T41	13		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T31	1		T117	13		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T8	6		T166	7		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	2		T36	14		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	4		T11	8		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T120	11		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T172	5		T211	2		T35	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T130	13		T32	23		T197	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T195	15		T94	14		T229	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T172	13		T129	17		T209	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T165	1		T159	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T227	1		T228	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T140	1		T228	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T120	1		T117	14		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T37	2		T136	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T23	11		T123	1		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	13		T38	12		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	1		T23	18		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T37	1		T38	9		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	1		T24	1		T211	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	2		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	11		T24	1		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	14		T140	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T120	1		T129	11		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	3		T117	17		T186	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	18		T8	8		T139	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	1		T26	6		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T3	4		T7	2		T9	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	11		T11	2		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T4	4		T38	13		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T122	1		T120	10		T31	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T228	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T120	12		T117	11		T197	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T136	10		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T123	12		T42	2		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	2		T131	5		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	10		T32	5		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T37	7		T194	8		T167	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T211	15		T210	11		T217	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	1		T30	2		T123	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	8		T30	2		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T130	8		T44	2		T199	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T129	11		T127	9		T94	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T31	1		T117	13		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	6		T48	2		T41	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T125	12		T43	11		T36	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T3	4		T11	8		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	3		T48	9		T197	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T172	5		T211	2		T158	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T120	11		T31	7		T123	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T120	13		T117	12		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T37	2		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T123	13		T127	12		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T38	2		T171	1		T194	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T23	2		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T37	8		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T30	3		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	2		T30	3		T123	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	11		T24	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	1		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T117	1		T129	12		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T31	3		T117	14		T125	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T6	1		T7	2		T8	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	3		T24	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T3	5		T11	9		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T11	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T38	1		T155	1		T172	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T165	1		T130	14		T32	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T4	1		T195	16		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T172	14		T129	19		T209	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17943	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T117	13		T42	2		T152	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T4	12		T37	1		T31	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T230	2		T208	10		T231	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	19		T171	13		T194	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	27		T48	12		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T125	2		T186	10		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T32	2		T125	14		T211	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	1		T30	2		T80	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T26	12		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	13		T186	2		T131	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T117	1		T129	10		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T31	1		T117	16		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T6	17		T8	3		T9	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	5		T172	7		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	3		T23	9		T158	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	10		T120	9		T31	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T38	12		T172	1		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T32	13		T159	15		T197	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T4	3		T195	10		T94	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T172	16		T129	29		T209	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T232	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T165	1		T159	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T227	1		T228	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T140	1		T228	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T120	13		T117	12		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	2		T136	11		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T23	1		T123	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	1		T38	1		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T23	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T37	8		T38	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	1		T24	1		T211	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T8	2		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	11		T24	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T4	1		T140	1		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T120	1		T129	12		T183	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T31	3		T117	14		T186	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T8	11		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T24	1		T26	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T3	5		T7	2		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	1		T11	5		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T4	1		T38	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T122	1		T120	12		T31	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T159	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T228	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T117	13		T159	3		T197	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T37	1		T194	7		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T23	10		T144	10		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	12		T38	11		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T23	17		T48	12		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T38	8		T194	10		T219	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T211	15		T210	11		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	1		T30	2		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	8		T26	12		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T4	13		T199	10		T94	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T129	10		T231	3		T168	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	1		T117	16		T186	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	17		T8	3		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	5		T172	7		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T3	3		T9	25		T23	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	10		T139	9		T48	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T4	3		T38	12		T172	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T120	9		T31	9		T172	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10