Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23196

1

T1

20

T2

19

T3

158

auto[ADC_CTRL_FILTER_COND_OUT]

3791

1

T3

20

T4

17

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21434

1

T1

20

T2

19

T3

178

auto[1]

5553

1

T4

14

T7

2

T9

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T23	18		T242	2		T243	4
values[0]	11	1			T8	3		T244	5		T19	3
values[1]	628	1			T8	14		T121	1		T31	4
values[2]	2956	1			T3	8		T5	11		T7	2
values[3]	672	1			T12	1		T23	11		T24	1
values[4]	569	1			T24	1		T151	1		T120	13
values[5]	725	1			T26	6		T37	11		T30	3
values[6]	737	1			T4	14		T24	1		T38	13
values[7]	550	1			T11	3		T12	1		T120	1
values[8]	497	1			T4	4		T11	9		T23	10
values[9]	1679	1			T3	20		T4	13		T6	18
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	787	1			T5	11		T8	17		T121	1
values[1]	2974	1			T7	2		T9	27		T10	1
values[2]	607	1			T3	8		T12	1		T24	1
values[3]	584	1			T23	11		T24	1		T30	3
values[4]	794	1			T26	6		T37	11		T38	13
values[5]	635	1			T4	14		T24	1		T140	1
values[6]	635	1			T11	3		T12	1		T120	1
values[7]	666	1			T3	19		T4	4		T11	9
values[8]	1158	1			T3	1		T4	13		T11	2
values[9]	195	1			T6	18		T31	6		T117	25
minimum	17952	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	11		T8	2		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	8		T123	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T7	2		T9	27		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T144	14		T130	1		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T139	5		T211	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T24	1		T38	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T23	11		T48	8		T187	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	1		T30	1		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	6		T37	3		T125	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T38	13		T32	4		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	14		T183	1		T186	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T24	1		T140	1		T129	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T129	16		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T120	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	13		T117	17		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	11		T4	4		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T11	1		T122	1		T139	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T3	1		T4	13		T23	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T125	3		T246	11		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T6	18		T31	4		T117	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17815	1			T1	20		T2	19		T3	147
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	1		T31	1		T210	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	6		T123	13		T165	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T136	10		T166	7		T120	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	13		T127	9		T197	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	4		T211	11		T134	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T120	12		T187	10		T196	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T48	2		T187	11		T36	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	2		T123	12		T172	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	8		T125	12		T131	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T32	5		T35	4		T248	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T216	7		T86	2		T91	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T129	13		T34	1		T158	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T129	4		T130	8		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	2		T30	2		T199	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T117	13		T194	13		T193	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	8		T11	8		T32	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	1		T211	6		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T31	7		T125	15		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T125	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T31	2		T117	11		T123	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T242	2		T243	2		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T23	18		T249	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T8	2		T244	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T19	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T121	1		T31	3		T131	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	8		T171	13		T152	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T3	4		T5	11		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T123	1		T165	1		T144	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T23	11		T139	5		T129	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T24	1		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	8		T131	12		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	1		T151	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T26	6		T37	3		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T30	1		T117	2		T32	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	14		T183	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T24	1		T38	13		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T129	16		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	1		T120	1		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T165	1		T171	14		T13	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	4		T11	1		T23	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T11	1		T26	13		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	602	1			T3	12		T4	13		T6	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T243	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T8	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T19	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T31	1		T131	2		T127	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	6		T152	2		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1081	1			T3	4		T136	10		T166	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T123	13		T165	8		T130	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T129	11		T134	2		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T187	10		T197	16		T196	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T48	2		T131	5		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	12		T123	12		T172	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	8		T125	12		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	2		T32	5		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T216	7		T86	2		T91	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T129	13		T34	1		T158	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T129	4		T130	8		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	2		T199	12		T209	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T158	6		T194	21		T200	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	8		T30	2		T189	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	1		T117	13		T125	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	444	1			T3	8		T31	9		T117	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	1		T8	2		T121	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	11		T123	14		T165	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T7	2		T9	2		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T144	1		T130	14		T127	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	5		T139	1		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T24	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T23	1		T48	3		T187	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	1		T30	3		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T26	1		T37	10		T125	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T38	1		T32	7		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T183	1		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	1		T140	1		T129	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T129	5		T130	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	3		T120	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	1		T117	14		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	11		T4	1		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	2		T122	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T3	1		T4	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T125	3		T246	1		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T6	1		T31	5		T117	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17951	1			T1	20		T2	19		T3	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	10		T8	1		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	3		T171	12		T152	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T9	25		T120	9		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	13		T223	7		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	3		T139	4		T211	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	11		T250	4		T251	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T23	10		T48	7		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T117	1		T172	8		T42	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	5		T37	1		T125	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	12		T32	2		T35	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	13		T186	10		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T129	14		T158	14		T197	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T129	15		T33	1		T158	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T30	2		T199	13		T209	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T26	12		T117	16		T171	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	8		T4	3		T23	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T139	9		T211	14		T194	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T4	12		T23	17		T38	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T125	2		T246	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T6	17		T31	1		T117	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T202	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T242	2		T243	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T23	1		T249	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T8	2		T244	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T121	1		T31	3		T131	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	11		T171	1		T152	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T3	5		T5	1		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	14		T165	9		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T23	1		T139	1		T129	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T24	1		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	3		T131	6		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T24	1		T151	1		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	1		T37	10		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	3		T117	1		T32	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T183	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T24	1		T38	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T129	5		T130	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	3		T120	1		T199	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	1		T171	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	1		T11	9		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T11	2		T26	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	542	1			T3	12		T4	1		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T23	17		T249	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T8	1		T244	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	1		T131	10		T210	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	3		T171	12		T152	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T3	3		T5	10		T9	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T144	13		T223	7		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T23	10		T139	4		T129	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	11		T197	18		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	7		T131	11		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T172	8		T195	10		T208	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T26	5		T37	1		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T117	1		T32	2		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	13		T216	9		T86	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	12		T129	14		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T129	15		T186	10		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T199	13		T209	1		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T171	13		T13	4		T158	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	3		T23	9		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T26	12		T139	9		T117	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	504	1			T3	8		T4	12		T6	17

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10