Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20967

1

T1

20

T2

19

T3

169

auto[ADC_CTRL_FILTER_COND_OUT]

6020

1

T3

9

T4

18

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21202

1

T1

20

T2

19

T3

151

auto[1]

5785

1

T3

27

T4

14

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T134	3		T252	1		T253	5
values[0]	19	1			T123	14		T186	3		T254	1
values[1]	718	1			T37	8		T139	15		T48	10
values[2]	794	1			T3	19		T8	14		T11	9
values[3]	736	1			T3	1		T5	11		T23	10
values[4]	658	1			T3	8		T23	18		T26	6
values[5]	736	1			T12	2		T26	13		T38	12
values[6]	622	1			T8	3		T11	2		T24	1
values[7]	691	1			T123	8		T48	23		T129	48
values[8]	753	1			T6	18		T11	3		T24	1
values[9]	3319	1			T4	31		T7	2		T9	27
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	868	1			T3	19		T11	9		T37	8
values[1]	2910	1			T3	1		T5	11		T7	2
values[2]	741	1			T37	3		T120	21		T30	3
values[3]	693	1			T3	8		T12	1		T23	18
values[4]	744	1			T12	1		T26	13		T121	1
values[5]	637	1			T8	3		T11	2		T24	1
values[6]	715	1			T6	18		T123	8		T48	39
values[7]	572	1			T11	3		T24	1		T122	1
values[8]	946	1			T4	31		T23	11		T151	1
values[9]	176	1			T205	1		T197	15		T92	14
minimum	17985	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T3	11		T37	1		T139	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	1		T139	10		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	8		T123	1		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1596	1			T3	1		T5	11		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T37	2		T120	10		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	1		T172	2		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T23	18		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	4		T30	3		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T117	31		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T26	13		T121	1		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T24	1		T165	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T8	2		T38	13		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	18		T48	7		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T123	1		T48	13		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T24	1		T122	1		T144	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	1		T144	14		T125	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	13		T23	11		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	18		T120	1		T31	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T218	2		T252	1		T250	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T205	1		T197	8		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17826	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T246	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	8		T37	7		T48	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	8		T123	13		T211	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T8	6		T123	12		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1038	1			T166	7		T156	13		T157	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T37	1		T120	11		T158	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T30	2		T172	5		T41	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T125	2		T158	15		T226	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T3	4		T30	2		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T117	24		T129	11		T211	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T136	10		T125	12		T131	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	1		T165	8		T129	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T187	11		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	9		T211	2		T131	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	7		T48	10		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T92	13		T255	7		T256	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	2		T125	15		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	1		T35	4		T43	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T120	12		T31	7		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T250	12		T243	3		T257	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T197	7		T92	13		T219	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T134	1		T253	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T254	1		T258	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T123	1		T186	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T37	1		T139	5		T48	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T139	10		T44	1		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	11		T8	8		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T11	1		T24	1		T38	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	2		T155	1		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	1		T5	11		T23	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T23	18		T26	6		T120	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	4		T121	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	2		T117	31		T165	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T26	13		T38	12		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	1		T24	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T8	2		T136	1		T38	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T129	31		T131	12		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T123	1		T48	13		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	18		T24	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T144	14		T125	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T4	13		T23	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1639	1			T4	18		T7	2		T9	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T134	2		T253	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T123	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	7		T48	2		T130	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	2		T197	16		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T8	6		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	8		T172	13		T211	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T37	1		T260	3		T261	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T30	2		T32	23		T41	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T120	11		T125	2		T158	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T3	4		T30	2		T31	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T117	24		T165	8		T129	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T131	2		T199	7		T193	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T11	1		T211	2		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T136	10		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T129	17		T131	5		T194	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T123	7		T48	10		T130	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	9		T35	4		T127	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	2		T125	15		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T31	1		T43	11		T210	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T166	7		T120	12		T31	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	11		T37	8		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T11	9		T139	1		T123	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	11		T123	13		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1366	1			T3	1		T5	1		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T37	2		T120	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T30	3		T172	6		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T12	1		T23	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	5		T30	3		T31	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T117	26		T129	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T26	1		T121	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	2		T24	1		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	2		T38	1		T205	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	1		T48	10		T211	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T123	8		T48	11		T130	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T24	1		T122	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	3		T144	1		T125	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	1		T23	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T4	2		T120	13		T31	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T218	1		T252	1		T250	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T205	1		T197	8		T92	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17961	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	8		T139	4		T48	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T139	9		T211	10		T186	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	3		T262	23		T80	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1268	1			T5	10		T9	25		T23	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	1		T120	9		T158	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T172	1		T13	4		T212	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T23	17		T26	5		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	3		T30	2		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T117	29		T129	10		T211	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T26	12		T38	11		T172	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T129	29		T159	3		T200	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T38	12		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	17		T48	6		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T48	12		T32	2		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T144	10		T263	10		T184	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T144	13		T125	14		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	12		T23	10		T31	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	16		T31	9		T131	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T218	1		T250	11		T243	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T197	7		T219	12		T242	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T94	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T246	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T252	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T134	3		T253	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T254	1		T258	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T123	14		T186	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	8		T139	1		T48	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T139	1		T44	3		T259	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	11		T8	11		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T11	9		T24	1		T38	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	2		T155	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	1		T5	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T23	1		T26	1		T120	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	5		T121	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	2		T117	26		T165	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T26	1		T38	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	2		T24	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	2		T136	11		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	19		T131	6		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T123	8		T48	11		T130	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T6	1		T24	1		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	3		T144	1		T125	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	1		T23	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1563	1			T4	2		T7	2		T9	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T186	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	4		T48	7		T86	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T139	9		T159	15		T197	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	8		T8	3		T264	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T38	8		T172	16		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	1		T153	9		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	10		T23	9		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T23	17		T26	5		T120	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	3		T30	2		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T117	29		T129	10		T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	12		T38	11		T186	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T211	9		T159	3		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T38	12		T172	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T129	29		T131	11		T194	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	12		T152	3		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	17		T117	1		T48	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T144	13		T125	14		T42	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	12		T23	10		T31	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1280	1			T4	16		T9	25		T31	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10