Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23332

1

T1

20

T2

19

T3

178

auto[ADC_CTRL_FILTER_COND_OUT]

3655

1

T4

31

T5

11

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20794

1

T1

20

T2

19

T3

150

auto[1]

6193

1

T3

28

T4

17

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	292	1			T38	13		T165	1		T172	37
values[0]	3	1			T140	1		T228	2		-	-
values[1]	782	1			T37	3		T136	11		T120	13
values[2]	707	1			T4	13		T23	11		T38	21
values[3]	671	1			T12	1		T23	18		T37	8
values[4]	659	1			T3	1		T8	3		T12	1
values[5]	763	1			T3	19		T4	14		T26	13
values[6]	517	1			T24	1		T120	1		T31	4
values[7]	768	1			T6	18		T8	14		T24	1
values[8]	2783	1			T3	8		T5	11		T7	2
values[9]	1110	1			T4	4		T122	1		T120	21
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	666	1			T37	3		T136	11		T120	13
values[1]	722	1			T4	13		T23	11		T38	21
values[2]	672	1			T12	2		T23	18		T24	1
values[3]	665	1			T3	1		T8	3		T30	3
values[4]	694	1			T3	19		T4	14		T24	1
values[5]	713	1			T120	1		T31	4		T117	32
values[6]	2772	1			T6	18		T7	2		T8	14
values[7]	825	1			T3	8		T5	11		T11	14
values[8]	911	1			T38	13		T155	1		T165	1
values[9]	165	1			T4	4		T172	30		T129	48
minimum	18182	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T120	1		T155	1		T42	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	2		T136	1		T31	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T23	11		T123	1		T152	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	13		T38	21		T171	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	1		T23	18		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T37	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T30	1		T125	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	2		T123	1		T125	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	11		T24	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	14		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T120	1		T117	2		T129	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T31	3		T117	17		T125	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T6	18		T7	2		T8	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T24	1		T26	6		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	4		T11	1		T23	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	11		T11	2		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T38	13		T155	1		T172	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T165	1		T32	17		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T195	11		T160	1		T265	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T4	4		T172	17		T129	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17885	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T140	1		T154	2		T161	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T120	12		T42	2		T197	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	1		T136	10		T31	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T123	12		T152	2		T127	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T187	11		T194	8		T193	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	10		T32	5		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T37	7		T30	2		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T30	2		T125	15		T211	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T123	13		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	8		T33	1		T234	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T130	8		T131	2		T199	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	11		T34	1		T127	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T31	1		T117	13		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	951	1			T8	6		T166	7		T156	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T165	8		T36	14		T216	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	4		T11	8		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	3		T120	11		T31	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T172	5		T130	13		T211	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	23		T197	16		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T195	15		T265	9		T266	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T172	13		T129	17		T209	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	3		T31	3		T117	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T91	1		T217	10		T221	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T38	13		T172	2		T35	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T165	1		T172	17		T129	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T140	1		T228	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T120	1		T117	14		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T37	2		T136	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T23	11		T123	1		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	13		T38	21		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T12	1		T23	18		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T37	1		T28	1		T194	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T3	1		T24	1		T211	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	2		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	11		T26	13		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T4	14		T140	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T24	1		T120	1		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	3		T117	17		T131	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	18		T8	8		T139	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T24	1		T26	6		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1481	1			T3	4		T7	2		T9	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	11		T11	2		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T155	1		T144	14		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T4	4		T122	1		T120	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T172	5		T35	4		T267	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T172	13		T129	4		T197	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T120	12		T117	11		T197	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T37	1		T136	10		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T123	12		T42	2		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T31	2		T131	5		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	10		T32	5		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T37	7		T194	8		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T211	15		T210	11		T175	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T30	2		T123	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	8		T30	2		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T130	8		T44	2		T199	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	11		T127	9		T94	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	1		T117	13		T131	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	6		T48	2		T34	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T125	12		T41	13		T43	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T3	4		T11	8		T166	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	3		T123	7		T48	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T130	13		T211	2		T195	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T120	11		T31	7		T129	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T120	13		T155	1		T42	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T37	2		T136	11		T31	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T23	1		T123	13		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	1		T38	2		T171	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T23	1		T24	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T37	8		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	1		T30	3		T125	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T8	2		T123	14		T125	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	11		T24	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T4	1		T140	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T120	1		T117	1		T129	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T31	3		T117	14		T125	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T6	1		T7	2		T8	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T24	1		T26	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	5		T11	9		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	1		T11	5		T122	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T38	1		T155	1		T172	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T165	1		T32	27		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T195	16		T160	1		T265	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T4	1		T172	14		T129	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18007	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T140	1		T154	2		T161	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T42	2		T159	3		T197	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T37	1		T31	1		T131	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T23	10		T152	3		T195	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	12		T38	19		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	17		T48	12		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	2		T186	10		T131	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T125	14		T211	15		T210	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T125	2		T80	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	8		T26	12		T186	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	13		T131	10		T199	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T117	1		T129	10		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T31	1		T117	16		T125	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T6	17		T8	3		T9	25
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	5		T172	7		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	3		T23	9		T158	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	10		T120	9		T31	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T38	12		T172	1		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T32	13		T159	6		T197	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T195	10		T265	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T4	3		T172	16		T129	29
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T117	13		T198	11		T268	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T91	1		T217	11		T269	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T38	1		T172	6		T35	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T165	1		T172	14		T129	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T140	1		T228	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T120	13		T117	12		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	2		T136	11		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T23	1		T123	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	1		T38	2		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T23	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T37	8		T28	1		T194	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T24	1		T211	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	2		T12	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	11		T26	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	1		T140	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	1		T120	1		T129	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T31	3		T117	14		T131	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T8	11		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T24	1		T26	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T3	5		T7	2		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	1		T11	5		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T155	1		T144	1		T130	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T4	1		T122	1		T120	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T38	12		T172	1		T35	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T172	16		T129	15		T159	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T117	13		T159	3		T197	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T37	1		T194	7		T91	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T23	10		T144	10		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	12		T38	19		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T23	17		T48	12		T171	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T194	10		T226	9		T219	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T211	15		T210	11		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	1		T30	2		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	8		T26	12		T186	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	13		T199	10		T194	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T129	10		T231	3		T168	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	1		T117	16		T131	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	17		T8	3		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	5		T172	7		T125	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T3	3		T9	25		T23	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	10		T139	9		T48	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T144	13		T211	9		T159	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	3		T120	9		T31	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10