Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23495

1

T1

20

T2

19

T3

150

auto[ADC_CTRL_FILTER_COND_OUT]

3492

1

T3

28

T4

14

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21040

1

T1

20

T2

19

T3

178

auto[1]

5947

1

T4

18

T6

18

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	306	1			T23	10		T26	13		T117	2
values[0]	25	1			T244	15		T233	10		-	-
values[1]	554	1			T5	11		T12	1		T123	8
values[2]	616	1			T3	19		T136	11		T38	9
values[3]	821	1			T23	18		T24	1		T26	6
values[4]	2808	1			T7	2		T8	3		T9	27
values[5]	877	1			T3	1		T4	27		T6	18
values[6]	751	1			T12	1		T24	1		T120	13
values[7]	824	1			T8	14		T11	5		T23	11
values[8]	678	1			T3	8		T4	4		T122	1
values[9]	795	1			T38	13		T31	6		T117	30
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	652	1			T3	19		T12	1		T123	8
values[1]	503	1			T26	6		T136	11		T38	9
values[2]	830	1			T23	18		T24	1		T37	8
values[3]	2936	1			T3	1		T7	2		T8	3
values[4]	897	1			T4	27		T6	18		T12	1
values[5]	737	1			T24	1		T120	13		T31	19
values[6]	762	1			T3	8		T4	4		T8	14
values[7]	651	1			T122	1		T30	3		T31	6
values[8]	892	1			T23	10		T26	13		T38	13
values[9]	39	1			T117	2		T200	6		T234	21
minimum	18088	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T171	14		T125	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	11		T123	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T136	1		T38	9		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	6		T139	10		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T37	1		T32	17		T125	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T23	18		T24	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T7	2		T8	2		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T37	2		T38	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	13		T6	18		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T4	14		T117	14		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T24	1		T31	12		T129	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T120	1		T139	5		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	4		T8	8		T11	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	4		T31	3		T32	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T31	4		T48	8		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T122	1		T30	1		T171	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T38	13		T144	14		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T23	10		T26	13		T117	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T117	2		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T200	3		T234	8		T21	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17863	1			T1	20		T2	19		T3	147
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T5	11		T48	13		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T125	12		T187	10		T158	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	8		T123	7		T210	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T136	10		T129	11		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T123	12		T129	4		T131	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	7		T32	23		T125	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T123	13		T158	6		T91	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T8	1		T11	8		T166	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T37	1		T30	2		T130	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T120	11		T41	13		T43	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T117	11		T36	14		T94	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T31	7		T129	13		T211	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T120	12		T165	8		T195	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	6		T11	3		T48	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	4		T31	1		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T31	2		T48	2		T211	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T30	2		T194	13		T197	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T210	12		T196	16		T94	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T117	13		T131	12		T236	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T200	3		T234	13		T21	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	3		T31	3		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T48	10		T248	7		T233	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T117	2		T200	1		T217	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T23	10		T26	13		T200	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T244	15		T233	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	1		T171	14		T125	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	11		T123	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T136	1		T38	9		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	11		T139	10		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T37	1		T32	17		T125	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T23	18		T24	1		T26	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T7	2		T8	2		T9	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T37	2		T38	12		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T4	13		T6	18		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	1		T4	14		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	1		T24	1		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	1		T117	14		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T8	8		T11	2		T23	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T31	3		T139	5		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	4		T48	15		T211	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	4		T122	1		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T38	13		T31	4		T144	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T117	17		T131	14		T194	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T217	15		T222	9		T237	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T200	3		T189	9		T261	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T125	12		T127	13		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T123	7		T48	10		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T136	10		T129	11		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	8		T123	12		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T37	7		T32	23		T125	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T123	13		T152	2		T158	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	944	1			T8	1		T11	8		T166	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T37	1		T30	2		T130	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T120	11		T41	13		T43	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T187	11		T226	13		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T31	7		T129	13		T211	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T120	12		T117	11		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	6		T11	3		T172	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T31	1		T32	5		T195	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	11		T211	11		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	4		T30	2		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	2		T210	12		T196	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T117	13		T131	12		T194	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T171	1		T125	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	11		T123	8		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T136	11		T38	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T26	1		T139	1		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T37	8		T32	27		T125	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T23	1		T24	1		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T7	2		T8	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	1		T37	2		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T6	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	1		T117	12		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T24	1		T31	10		T129	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T120	13		T139	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	1		T8	11		T11	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	5		T31	3		T32	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	5		T48	3		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	1		T30	3		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T38	1		T144	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T23	1		T26	1		T117	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T117	1		-	-		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T200	4		T234	14		T21	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17963	1			T1	20		T2	19		T3	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T5	1		T48	11		T248	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T171	13		T125	8		T158	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	8		T210	11		T240	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	8		T172	7		T129	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T26	5		T139	9		T129	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	13		T125	16		T211	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T23	17		T144	10		T186	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1152	1			T8	1		T9	25		T170	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	1		T38	11		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	12		T6	17		T120	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	13		T117	13		T94	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	9		T129	14		T211	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	4		T13	4		T195	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	3		T8	3		T23	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	3		T31	1		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T31	1		T48	7		T211	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T171	12		T186	10		T194	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	12		T144	13		T210	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T23	9		T26	12		T117	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T117	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T200	2		T234	7		T21	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T159	9		T225	11		T270	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T5	10		T48	12		T244	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T117	1		T200	1		T217	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T23	1		T26	1		T200	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T244	1		T233	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T171	1		T125	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	1		T123	8		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	11		T38	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	11		T139	1		T123	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T37	8		T32	27		T125	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T23	1		T24	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T7	2		T8	2		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T37	2		T38	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	1		T6	1		T24	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	1		T4	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T12	1		T24	1		T31	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T120	13		T117	12		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	11		T11	5		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	3		T139	1		T32	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	1		T48	13		T211	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	5		T122	1		T30	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T38	1		T31	5		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	14		T131	13		T194	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T117	1		T217	17		T213	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T23	9		T26	12		T200	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T244	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T171	13		T125	8		T159	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	10		T48	12		T210	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T38	8		T172	7		T129	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	8		T139	9		T129	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T32	13		T125	14		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T23	17		T26	5		T144	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T8	1		T9	25		T170	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	1		T38	11		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	12		T6	17		T120	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	13		T226	11		T189	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T31	9		T129	14		T211	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T117	13		T13	4		T94	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	3		T23	10		T172	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	1		T139	4		T32	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	3		T48	13		T211	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	3		T171	12		T186	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T38	12		T31	1		T144	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	16		T131	13		T194	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10