Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23567

1

T1

20

T2

19

T3

151

auto[ADC_CTRL_FILTER_COND_OUT]

3420

1

T3

27

T4

17

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21403

1

T1

20

T2

19

T3

150

auto[1]

5584

1

T3

28

T4

27

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T271	14		T272	9		-	-
values[0]	18	1			T252	1		T20	5		T273	1
values[1]	630	1			T24	1		T136	11		T31	19
values[2]	646	1			T3	19		T4	14		T6	18
values[3]	730	1			T4	13		T121	1		T120	1
values[4]	804	1			T24	1		T26	6		T30	3
values[5]	2939	1			T3	1		T7	2		T8	3
values[6]	722	1			T3	8		T4	4		T11	3
values[7]	696	1			T26	13		T122	1		T31	6
values[8]	551	1			T5	11		T12	1		T37	3
values[9]	1296	1			T8	14		T12	1		T23	39
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	777	1			T3	19		T6	18		T24	1
values[1]	757	1			T4	27		T139	10		T183	1
values[2]	658	1			T121	1		T120	1		T30	5
values[3]	3016	1			T3	1		T7	2		T9	27
values[4]	736	1			T4	4		T8	3		T120	13
values[5]	680	1			T26	13		T38	9		T151	1
values[6]	681	1			T3	8		T5	11		T11	3
values[7]	602	1			T8	14		T12	1		T23	11
values[8]	996	1			T12	1		T23	28		T37	8
values[9]	137	1			T38	13		T125	5		T205	1
minimum	17947	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	1		T120	10		T32	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	11		T6	18		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	14		T183	1		T131	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	13		T139	10		T127	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T121	1		T120	1		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T31	3		T123	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T3	1		T7	2		T9	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	2		T38	12		T171	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T120	1		T211	16		T186	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	4		T8	2		T139	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	13		T38	9		T172	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T151	1		T165	1		T129	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	11		T11	1		T172	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	4		T37	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	8		T12	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T23	11		T24	1		T31	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T23	18		T117	2		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	1		T23	10		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T274	1		T244	14		T275	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T38	13		T125	3		T205	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17815	1			T1	20		T2	19		T3	147
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T120	11		T32	23		T226	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	8		T136	10		T31	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T131	12		T168	10		T276	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T127	13		T226	13		T207	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	2		T32	5		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T31	1		T123	12		T165	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T166	7		T30	2		T156	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	9		T33	1		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T120	12		T211	6		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T130	13		T34	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T172	13		T197	6		T212	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T129	11		T130	8		T193	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	2		T172	5		T41	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T3	4		T37	1		T117	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T8	6		T44	2		T152	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T31	2		T117	13		T48	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T123	13		T48	10		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	7		T48	2		T158	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T275	6		T17	1		T243	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T125	2		T189	4		T221	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T271	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T272	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T252	1		T20	3		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T237	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	1		T159	7		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T136	1		T31	12		T172	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	14		T120	10		T32	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	11		T6	18		T129	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T121	1		T120	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	13		T31	3		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T24	1		T26	6		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T123	1		T171	14		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T3	1		T7	2		T9	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	2		T11	2		T38	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	1		T120	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	4		T4	4		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T26	13		T172	19		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	1		T31	4		T117	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	11		T12	1		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T37	2		T140	1		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	384	1			T8	8		T23	18		T117	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	418	1			T12	1		T23	21		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T271	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T272	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T20	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T237	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T226	12		T214	15		T275	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T136	10		T31	7		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	11		T32	23		T276	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	8		T129	13		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	2		T131	12		T194	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T31	1		T165	8		T131	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	2		T32	5		T125	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T123	12		T125	12		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T166	7		T156	13		T157	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T11	9		T130	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	2		T120	12		T211	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	4		T129	11		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T172	18		T41	13		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T31	2		T117	24		T123	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T187	10		T195	9		T92	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T37	1		T187	11		T34	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	6		T123	13		T48	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T37	7		T48	11		T125	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T24	1		T120	12		T32	27
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	11		T6	1		T136	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T183	1		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T4	1		T139	1		T127	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T121	1		T120	1		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	3		T123	13		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T3	1		T7	2		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	11		T38	1		T171	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T120	13		T211	8		T186	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T4	1		T8	2		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	1		T38	1		T172	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	1		T165	1		T129	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T11	3		T172	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	5		T37	2		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	11		T12	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T23	1		T24	1		T31	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T23	1		T117	1		T123	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T23	1		T37	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T274	1		T244	1		T275	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T38	1		T125	3		T205	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17944	1			T1	20		T2	19		T3	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T120	9		T32	13		T226	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	8		T6	17		T31	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	13		T131	13		T159	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	12		T139	9		T226	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T30	2		T171	12		T32	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T31	1		T125	8		T131	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T9	25		T26	5		T170	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	11		T171	13		T33	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T211	14		T186	12		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	3		T8	1		T139	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T26	12		T38	8		T172	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T129	10		T193	2		T94	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	10		T172	1		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T3	3		T37	1		T117	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	3		T152	3		T195	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T23	10		T31	1		T117	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T23	17		T117	1		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T23	9		T48	7		T144	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T244	13		T275	6		T243	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T38	12		T125	2		T189	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T220	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T271	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T272	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T252	1		T20	3		T273	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T237	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T24	1		T159	1		T160	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T136	11		T31	10		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T120	12		T32	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	11		T6	1		T129	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T121	1		T120	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	1		T31	3		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T24	1		T26	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T123	13		T171	1		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T3	1		T7	2		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	2		T11	11		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	3		T120	13		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	5		T4	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T26	1		T172	20		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T122	1		T31	5		T117	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T12	1		T187	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T37	2		T140	1		T187	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T8	11		T23	1		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T12	1		T23	2		T24	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17932	1			T1	20		T2	19		T3	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T271	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T272	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T20	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T159	6		T226	9		T214	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T31	9		T172	7		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	13		T120	9		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	8		T6	17		T129	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	2		T131	13		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	12		T31	1		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	5		T171	12		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T171	13		T125	8		T33	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T9	25		T38	8		T170	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	1		T38	11		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T144	10		T211	9		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	3		T4	3		T139	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T26	12		T172	17		T42	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T31	1		T117	29		T131	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	10		T195	7		T208	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T37	1		T35	5		T86	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T8	3		T23	17		T117	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T23	19		T38	12		T48	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10