Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 910
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T50 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4006516356 Mar 12 01:00:04 PM PDT 24 Mar 12 01:00:17 PM PDT 24 8505302058 ps
T56 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.521503420 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:18 PM PDT 24 392496065 ps
T57 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2855348180 Mar 12 12:58:50 PM PDT 24 Mar 12 12:58:52 PM PDT 24 404891358 ps
T67 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3421578632 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:16 PM PDT 24 747449130 ps
T794 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2306300238 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:06 PM PDT 24 391244376 ps
T795 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1782208968 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 671364777 ps
T796 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3088261049 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:11 PM PDT 24 546950713 ps
T95 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1439640742 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:02 PM PDT 24 728258509 ps
T797 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.348365260 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 550002219 ps
T51 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3864535417 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:19 PM PDT 24 8541282823 ps
T115 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.420887533 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:06 PM PDT 24 1237745410 ps
T69 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1877986653 Mar 12 12:59:06 PM PDT 24 Mar 12 12:59:07 PM PDT 24 502361523 ps
T64 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3101921041 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:25 PM PDT 24 8190609658 ps
T82 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2169061225 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:10 PM PDT 24 535990262 ps
T83 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3694274564 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:11 PM PDT 24 566932715 ps
T46 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1894658269 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:12 PM PDT 24 4940211780 ps
T47 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3993592169 Mar 12 12:59:01 PM PDT 24 Mar 12 12:59:07 PM PDT 24 2462479380 ps
T116 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1400519412 Mar 12 12:59:26 PM PDT 24 Mar 12 12:59:28 PM PDT 24 567515764 ps
T58 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3293893248 Mar 12 12:59:07 PM PDT 24 Mar 12 12:59:09 PM PDT 24 613247406 ps
T798 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3045751743 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:19 PM PDT 24 421079295 ps
T108 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3255880947 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:28 PM PDT 24 4838979508 ps
T799 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2866255141 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:17 PM PDT 24 390580174 ps
T800 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2491824182 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 465283618 ps
T59 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.625091098 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:08 PM PDT 24 1135545613 ps
T801 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.545138044 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:14 PM PDT 24 365987398 ps
T96 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4007691531 Mar 12 12:58:56 PM PDT 24 Mar 12 12:58:58 PM PDT 24 630479092 ps
T802 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3048970259 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:19 PM PDT 24 4504211779 ps
T63 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.481496626 Mar 12 12:58:51 PM PDT 24 Mar 12 12:58:54 PM PDT 24 477826149 ps
T60 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2535890752 Mar 12 12:59:00 PM PDT 24 Mar 12 12:59:02 PM PDT 24 345020313 ps
T803 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1138257060 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 427524878 ps
T109 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4155539679 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:12 PM PDT 24 2071285572 ps
T804 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4023684749 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:13 PM PDT 24 288179277 ps
T805 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3019724277 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:16 PM PDT 24 336677003 ps
T110 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1913848673 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:13 PM PDT 24 456537660 ps
T111 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1044850597 Mar 12 12:59:02 PM PDT 24 Mar 12 12:59:06 PM PDT 24 4317414658 ps
T66 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.552928481 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 432807189 ps
T112 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3296094371 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:17 PM PDT 24 415307882 ps
T113 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3896244380 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:17 PM PDT 24 513885808 ps
T806 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1183401628 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:05 PM PDT 24 394542512 ps
T114 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.539866529 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:14 PM PDT 24 2442613532 ps
T807 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1067952936 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:16 PM PDT 24 317017645 ps
T65 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2570718980 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:13 PM PDT 24 552059556 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2354551580 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:14 PM PDT 24 773874070 ps
T809 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1699213888 Mar 12 12:59:00 PM PDT 24 Mar 12 12:59:02 PM PDT 24 453666587 ps
T810 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3123846082 Mar 12 12:59:01 PM PDT 24 Mar 12 12:59:02 PM PDT 24 468452261 ps
T811 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.607225681 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:23 PM PDT 24 2381195203 ps
T812 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.690986392 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:11 PM PDT 24 881152539 ps
T813 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4225756695 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:10 PM PDT 24 335130084 ps
T814 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.278171322 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:12 PM PDT 24 527585324 ps
T815 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.801807056 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:13 PM PDT 24 2122197570 ps
T816 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.883307886 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 290648985 ps
T68 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1708143694 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:17 PM PDT 24 601302474 ps
T70 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1359975996 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:24 PM PDT 24 8274291617 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.74037715 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:10 PM PDT 24 430507388 ps
T818 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3001201430 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:18 PM PDT 24 522448387 ps
T819 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1831380429 Mar 12 12:59:48 PM PDT 24 Mar 12 12:59:50 PM PDT 24 504801541 ps
T820 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3400359036 Mar 12 12:59:48 PM PDT 24 Mar 12 12:59:53 PM PDT 24 4729506392 ps
T305 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1699552091 Mar 12 12:58:58 PM PDT 24 Mar 12 12:59:02 PM PDT 24 4432619133 ps
T821 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3959975722 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:22 PM PDT 24 2555236086 ps
T822 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1464480934 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 312684234 ps
T823 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2483773422 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:13 PM PDT 24 411770703 ps
T824 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3008734565 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 404761472 ps
T825 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2002082813 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:18 PM PDT 24 517561199 ps
T826 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.744223730 Mar 12 01:00:05 PM PDT 24 Mar 12 01:00:07 PM PDT 24 405702200 ps
T97 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2379175496 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:01 PM PDT 24 397537707 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.72189206 Mar 12 12:59:00 PM PDT 24 Mar 12 12:59:02 PM PDT 24 389736848 ps
T828 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1915363778 Mar 12 01:00:05 PM PDT 24 Mar 12 01:00:07 PM PDT 24 456018160 ps
T829 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3982140887 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:16 PM PDT 24 777058203 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.990292620 Mar 12 12:59:06 PM PDT 24 Mar 12 12:59:08 PM PDT 24 355348604 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3034690350 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:05 PM PDT 24 377102167 ps
T98 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1056626575 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:10 PM PDT 24 557493914 ps
T99 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1278454848 Mar 12 01:00:05 PM PDT 24 Mar 12 01:00:07 PM PDT 24 806451644 ps
T832 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1617847128 Mar 12 12:59:06 PM PDT 24 Mar 12 12:59:09 PM PDT 24 4995118062 ps
T833 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1939114959 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:14 PM PDT 24 2077300278 ps
T834 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3291231424 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:20 PM PDT 24 4383994518 ps
T835 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3337936224 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:16 PM PDT 24 390506375 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.95562765 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:13 PM PDT 24 531522080 ps
T837 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1054656291 Mar 12 12:58:57 PM PDT 24 Mar 12 12:58:58 PM PDT 24 622368895 ps
T838 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1613472423 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:16 PM PDT 24 385365808 ps
T100 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1383595469 Mar 12 12:59:04 PM PDT 24 Mar 12 12:59:07 PM PDT 24 1110081750 ps
T839 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1859553635 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:10 PM PDT 24 8310607347 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1072036330 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:19 PM PDT 24 512776407 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2679699122 Mar 12 12:59:06 PM PDT 24 Mar 12 12:59:09 PM PDT 24 520103449 ps
T842 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3537273278 Mar 12 01:01:23 PM PDT 24 Mar 12 01:01:25 PM PDT 24 509341038 ps
T843 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3621930959 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:23 PM PDT 24 8445139379 ps
T844 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.607248217 Mar 12 12:59:08 PM PDT 24 Mar 12 12:59:12 PM PDT 24 676158863 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3695427150 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 523183886 ps
T846 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3941019803 Mar 12 12:59:02 PM PDT 24 Mar 12 12:59:07 PM PDT 24 2263362776 ps
T847 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2524009512 Mar 12 01:00:04 PM PDT 24 Mar 12 01:00:09 PM PDT 24 8656866483 ps
T848 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.606503545 Mar 12 12:58:58 PM PDT 24 Mar 12 12:58:59 PM PDT 24 365344084 ps
T849 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1613179196 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 425758749 ps
T850 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2589359654 Mar 12 12:59:07 PM PDT 24 Mar 12 12:59:09 PM PDT 24 529802780 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.74314315 Mar 12 01:00:07 PM PDT 24 Mar 12 01:00:10 PM PDT 24 390220877 ps
T852 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3721487519 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 288861685 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2546019871 Mar 12 12:58:50 PM PDT 24 Mar 12 12:58:54 PM PDT 24 1190315511 ps
T854 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1422128842 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:16 PM PDT 24 395480919 ps
T855 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1667584858 Mar 12 12:59:02 PM PDT 24 Mar 12 12:59:05 PM PDT 24 1369053178 ps
T856 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.618767858 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 302542904 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3415983219 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 436241111 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3158742049 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 494125116 ps
T101 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4161288513 Mar 12 12:59:14 PM PDT 24 Mar 12 12:59:15 PM PDT 24 719895816 ps
T859 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3701745416 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:14 PM PDT 24 556101666 ps
T102 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4042825283 Mar 12 12:59:01 PM PDT 24 Mar 12 01:00:25 PM PDT 24 52028572242 ps
T860 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2886559243 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 441796660 ps
T861 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1095870118 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:20 PM PDT 24 4596743354 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2216991669 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:10 PM PDT 24 5143972581 ps
T103 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.579183653 Mar 12 12:58:57 PM PDT 24 Mar 12 12:58:58 PM PDT 24 396623774 ps
T863 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3471671622 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:12 PM PDT 24 983046754 ps
T864 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.286058537 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:14 PM PDT 24 4428957245 ps
T865 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3538623883 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 351549201 ps
T866 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1102550738 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:07 PM PDT 24 475231104 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.523876490 Mar 12 12:59:06 PM PDT 24 Mar 12 12:59:08 PM PDT 24 747817525 ps
T868 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.50359644 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:00 PM PDT 24 523197746 ps
T304 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3730898871 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:23 PM PDT 24 8632940846 ps
T869 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1843115729 Mar 12 12:59:04 PM PDT 24 Mar 12 01:00:00 PM PDT 24 26295135786 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.7143417 Mar 12 12:59:04 PM PDT 24 Mar 12 12:59:06 PM PDT 24 773567617 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.614572044 Mar 12 12:59:00 PM PDT 24 Mar 12 12:59:01 PM PDT 24 458158877 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3728647852 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:08 PM PDT 24 525902817 ps
T873 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2986374425 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:22 PM PDT 24 450064135 ps
T874 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1562496239 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:19 PM PDT 24 2370606414 ps
T875 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1875643124 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:12 PM PDT 24 898666300 ps
T876 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3210646393 Mar 12 12:59:07 PM PDT 24 Mar 12 12:59:18 PM PDT 24 4159640841 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3659066634 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:14 PM PDT 24 481900994 ps
T878 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.986461731 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:20 PM PDT 24 2046344569 ps
T879 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.883618806 Mar 12 12:59:05 PM PDT 24 Mar 12 12:59:06 PM PDT 24 311685639 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4189794031 Mar 12 12:58:45 PM PDT 24 Mar 12 12:58:46 PM PDT 24 551517958 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2031182598 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:00 PM PDT 24 381694600 ps
T882 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4142724554 Mar 12 12:59:02 PM PDT 24 Mar 12 12:59:10 PM PDT 24 2147260093 ps
T883 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1843805167 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 528929881 ps
T104 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3355751560 Mar 12 12:58:48 PM PDT 24 Mar 12 12:58:53 PM PDT 24 868582979 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3877076396 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:17 PM PDT 24 8558672187 ps
T885 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1585446788 Mar 12 12:59:15 PM PDT 24 Mar 12 12:59:17 PM PDT 24 528536839 ps
T886 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1716322673 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:13 PM PDT 24 1016690883 ps
T887 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.279249273 Mar 12 12:59:10 PM PDT 24 Mar 12 12:59:16 PM PDT 24 2455838852 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.210786385 Mar 12 12:58:50 PM PDT 24 Mar 12 12:58:53 PM PDT 24 385258329 ps
T889 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2910064856 Mar 12 12:59:16 PM PDT 24 Mar 12 12:59:18 PM PDT 24 446838032 ps
T890 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.560572055 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:22 PM PDT 24 8045789224 ps
T891 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.37668007 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 539110693 ps
T892 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1385359839 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:14 PM PDT 24 343342613 ps
T893 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2545388751 Mar 12 12:58:38 PM PDT 24 Mar 12 12:59:43 PM PDT 24 26595635452 ps
T894 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3157418240 Mar 12 01:00:05 PM PDT 24 Mar 12 01:00:07 PM PDT 24 454121590 ps
T106 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2031388405 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 425790880 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2155983631 Mar 12 12:58:53 PM PDT 24 Mar 12 12:58:56 PM PDT 24 4724470639 ps
T107 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1057962121 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:13 PM PDT 24 352695291 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2712735052 Mar 12 12:58:56 PM PDT 24 Mar 12 12:58:58 PM PDT 24 414163800 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1525740163 Mar 12 12:58:57 PM PDT 24 Mar 12 12:59:17 PM PDT 24 26205889190 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1438680839 Mar 12 01:00:07 PM PDT 24 Mar 12 01:00:13 PM PDT 24 9099795857 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1159098999 Mar 12 12:58:59 PM PDT 24 Mar 12 12:59:01 PM PDT 24 700206478 ps
T900 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3135457389 Mar 12 01:00:54 PM PDT 24 Mar 12 01:00:55 PM PDT 24 492732387 ps
T901 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1778453427 Mar 12 12:59:13 PM PDT 24 Mar 12 12:59:19 PM PDT 24 1984266425 ps
T902 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2941001200 Mar 12 12:59:11 PM PDT 24 Mar 12 12:59:12 PM PDT 24 399418996 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2051345676 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:08 PM PDT 24 1189951965 ps
T904 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.826955684 Mar 12 12:59:17 PM PDT 24 Mar 12 12:59:20 PM PDT 24 364076102 ps
T905 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3802212299 Mar 12 12:59:18 PM PDT 24 Mar 12 12:59:20 PM PDT 24 322932809 ps
T906 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2233825650 Mar 12 12:59:09 PM PDT 24 Mar 12 12:59:11 PM PDT 24 584376480 ps
T907 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.875720302 Mar 12 12:59:03 PM PDT 24 Mar 12 12:59:05 PM PDT 24 561107961 ps
T105 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.553846928 Mar 12 01:00:05 PM PDT 24 Mar 12 01:00:08 PM PDT 24 2643496330 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.674834571 Mar 12 12:59:12 PM PDT 24 Mar 12 12:59:13 PM PDT 24 499827317 ps
T909 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3098319454 Mar 12 12:59:02 PM PDT 24 Mar 12 12:59:18 PM PDT 24 4902987531 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2198703439 Mar 12 12:58:58 PM PDT 24 Mar 12 12:58:59 PM PDT 24 478624415 ps

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1891901241
Short name T8
Test name
Test status
Simulation time 275264046795 ps
CPU time 217.83 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:42:33 PM PDT 24
Peak memory 218056 kb
Host smart-26a60e9b-8a89-422b-9c38-269748b24b9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891901241 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1891901241
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.417849206
Short name T4
Test name
Test status
Simulation time 548769566884 ps
CPU time 616.23 seconds
Started Mar 12 12:37:37 PM PDT 24
Finished Mar 12 12:47:54 PM PDT 24
Peak memory 201872 kb
Host smart-47d9dbb6-46c5-4940-a722-bbd7077c6a96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417849206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.417849206
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.120114656
Short name T42
Test name
Test status
Simulation time 408974053058 ps
CPU time 1148.97 seconds
Started Mar 12 12:42:37 PM PDT 24
Finished Mar 12 01:01:48 PM PDT 24
Peak memory 209484 kb
Host smart-262e4ba8-41e2-41c2-b58c-fe4f0a089e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120114656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
120114656
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.218681839
Short name T125
Test name
Test status
Simulation time 517621975912 ps
CPU time 187.43 seconds
Started Mar 12 12:38:56 PM PDT 24
Finished Mar 12 12:42:05 PM PDT 24
Peak memory 201768 kb
Host smart-520a1c53-41a1-46e3-9f13-7a0fa9bbb3b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218681839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.218681839
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1422607998
Short name T129
Test name
Test status
Simulation time 504990546369 ps
CPU time 322.23 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:42:07 PM PDT 24
Peak memory 201896 kb
Host smart-dbf34b1f-adb7-4cea-93dd-32cea77eaaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422607998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1422607998
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.990401206
Short name T48
Test name
Test status
Simulation time 605369456999 ps
CPU time 1278.46 seconds
Started Mar 12 12:39:28 PM PDT 24
Finished Mar 12 01:00:47 PM PDT 24
Peak memory 201708 kb
Host smart-ceb40b37-a6d7-4353-bd43-6a0faf40e91f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990401206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.990401206
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.388844587
Short name T3
Test name
Test status
Simulation time 375108455246 ps
CPU time 346.63 seconds
Started Mar 12 12:37:39 PM PDT 24
Finished Mar 12 12:43:26 PM PDT 24
Peak memory 217672 kb
Host smart-daaeef32-36b9-49f4-8f4d-05ac0a960dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388844587 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.388844587
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.568890404
Short name T117
Test name
Test status
Simulation time 539202298108 ps
CPU time 1256.14 seconds
Started Mar 12 12:37:08 PM PDT 24
Finished Mar 12 12:58:05 PM PDT 24
Peak memory 201908 kb
Host smart-a5c176d7-380d-45eb-af78-769212f94676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568890404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.568890404
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2371214597
Short name T34
Test name
Test status
Simulation time 58591569509 ps
CPU time 184.9 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:41:51 PM PDT 24
Peak memory 218484 kb
Host smart-536c14d6-0a06-4538-aa11-a3ab415747d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371214597 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2371214597
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1309447260
Short name T120
Test name
Test status
Simulation time 496381260303 ps
CPU time 1174.28 seconds
Started Mar 12 12:37:06 PM PDT 24
Finished Mar 12 12:56:41 PM PDT 24
Peak memory 201676 kb
Host smart-28197587-a203-480b-9d3e-50eed3cc4d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309447260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1309447260
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3864535417
Short name T51
Test name
Test status
Simulation time 8541282823 ps
CPU time 7.31 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200896 kb
Host smart-0cedfa30-10ae-42a3-86ff-cc95bb81dd1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864535417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3864535417
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.434084647
Short name T194
Test name
Test status
Simulation time 495288935313 ps
CPU time 305.75 seconds
Started Mar 12 12:38:14 PM PDT 24
Finished Mar 12 12:43:20 PM PDT 24
Peak memory 201892 kb
Host smart-6ab1e96c-f222-4f5f-a2fa-927fe948c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434084647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.434084647
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1693312671
Short name T172
Test name
Test status
Simulation time 629731465928 ps
CPU time 352.82 seconds
Started Mar 12 12:40:27 PM PDT 24
Finished Mar 12 12:46:20 PM PDT 24
Peak memory 201792 kb
Host smart-ca8b616d-ec75-4672-a364-ed01fbabc958
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693312671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1693312671
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2675891301
Short name T127
Test name
Test status
Simulation time 484389420147 ps
CPU time 303.94 seconds
Started Mar 12 12:38:17 PM PDT 24
Finished Mar 12 12:43:21 PM PDT 24
Peak memory 201768 kb
Host smart-f12e2bfd-30c4-4850-9308-ea822f78753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675891301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2675891301
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4072905229
Short name T159
Test name
Test status
Simulation time 544709649047 ps
CPU time 1031.29 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:54:09 PM PDT 24
Peak memory 201880 kb
Host smart-5bf6076f-5fcb-4515-9278-ea0fc133b1f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072905229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4072905229
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3960379055
Short name T353
Test name
Test status
Simulation time 503055132 ps
CPU time 0.87 seconds
Started Mar 12 12:36:59 PM PDT 24
Finished Mar 12 12:37:00 PM PDT 24
Peak memory 201608 kb
Host smart-80b13ea7-111e-4a8b-a49d-0f0a1b7d7155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960379055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3960379055
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3293893248
Short name T58
Test name
Test status
Simulation time 613247406 ps
CPU time 2.26 seconds
Started Mar 12 12:59:07 PM PDT 24
Finished Mar 12 12:59:09 PM PDT 24
Peak memory 210048 kb
Host smart-9cb02dee-d2b6-4790-9663-3618293e571a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293893248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3293893248
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3556732921
Short name T210
Test name
Test status
Simulation time 383362737443 ps
CPU time 475.9 seconds
Started Mar 12 12:37:48 PM PDT 24
Finished Mar 12 12:45:44 PM PDT 24
Peak memory 201868 kb
Host smart-2a897d84-ab5a-4c6b-94ae-c7c9a009b5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556732921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3556732921
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3006256056
Short name T243
Test name
Test status
Simulation time 500073807260 ps
CPU time 98.34 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:41:27 PM PDT 24
Peak memory 201868 kb
Host smart-70e772fe-5f48-436b-87a1-6b1bb5025956
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006256056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3006256056
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2268672639
Short name T200
Test name
Test status
Simulation time 503490667119 ps
CPU time 583.87 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:46:28 PM PDT 24
Peak memory 201744 kb
Host smart-66d51b09-c910-4850-abbd-fb854841fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268672639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2268672639
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4007691531
Short name T96
Test name
Test status
Simulation time 630479092 ps
CPU time 1.87 seconds
Started Mar 12 12:58:56 PM PDT 24
Finished Mar 12 12:58:58 PM PDT 24
Peak memory 200732 kb
Host smart-f89daacd-a2bc-4495-b6b7-4b463baa042a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007691531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4007691531
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.199134070
Short name T37
Test name
Test status
Simulation time 498305128640 ps
CPU time 385.67 seconds
Started Mar 12 12:41:48 PM PDT 24
Finished Mar 12 12:48:14 PM PDT 24
Peak memory 201820 kb
Host smart-e03e49af-c857-41dc-a6a0-e86ffbf15944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199134070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
199134070
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2499032906
Short name T271
Test name
Test status
Simulation time 251848215647 ps
CPU time 376.39 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:42:33 PM PDT 24
Peak memory 218524 kb
Host smart-0b208355-2399-447c-a103-887156752bf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499032906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2499032906
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1847475661
Short name T32
Test name
Test status
Simulation time 874504217574 ps
CPU time 615.89 seconds
Started Mar 12 12:38:14 PM PDT 24
Finished Mar 12 12:48:30 PM PDT 24
Peak memory 210512 kb
Host smart-4ba144a8-5de9-4698-ad8f-454f1021b4bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847475661 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1847475661
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3255880947
Short name T108
Test name
Test status
Simulation time 4838979508 ps
CPU time 15.38 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:28 PM PDT 24
Peak memory 200836 kb
Host smart-258b327a-bb18-4ca1-8021-4e52f25fa20d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255880947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3255880947
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2905062004
Short name T242
Test name
Test status
Simulation time 92447849625 ps
CPU time 214.06 seconds
Started Mar 12 12:36:33 PM PDT 24
Finished Mar 12 12:40:07 PM PDT 24
Peak memory 212024 kb
Host smart-6f3baa17-68c1-4e1a-a92b-d0a68f5b5ae1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905062004 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2905062004
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1158487985
Short name T186
Test name
Test status
Simulation time 363308498025 ps
CPU time 195.7 seconds
Started Mar 12 12:38:34 PM PDT 24
Finished Mar 12 12:41:51 PM PDT 24
Peak memory 201808 kb
Host smart-558638b1-8dbd-4387-b328-1f325b963106
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158487985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1158487985
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3368351864
Short name T191
Test name
Test status
Simulation time 359966275880 ps
CPU time 888.47 seconds
Started Mar 12 12:40:10 PM PDT 24
Finished Mar 12 12:54:58 PM PDT 24
Peak memory 201724 kb
Host smart-4e8fcc92-e815-4e8c-a4eb-e5476e7871ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368351864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3368351864
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.472565581
Short name T53
Test name
Test status
Simulation time 7719202349 ps
CPU time 17.7 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:34 PM PDT 24
Peak memory 217852 kb
Host smart-2854724c-d5c7-44b8-8869-df94abfe2c99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472565581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.472565581
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1375598199
Short name T195
Test name
Test status
Simulation time 342527077592 ps
CPU time 199.47 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:44:16 PM PDT 24
Peak memory 201880 kb
Host smart-c323468c-6c9d-4a4b-96d2-af6720699f5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375598199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1375598199
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.790812127
Short name T31
Test name
Test status
Simulation time 498869993348 ps
CPU time 341.09 seconds
Started Mar 12 12:41:50 PM PDT 24
Finished Mar 12 12:47:31 PM PDT 24
Peak memory 210500 kb
Host smart-c0deaff6-6eb6-4e60-a245-628db97e5c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790812127 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.790812127
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2561852346
Short name T238
Test name
Test status
Simulation time 561032461043 ps
CPU time 1235.67 seconds
Started Mar 12 12:37:09 PM PDT 24
Finished Mar 12 12:57:46 PM PDT 24
Peak memory 201784 kb
Host smart-9ee6c8ca-d7ef-40d3-9924-c76e934fdc96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561852346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2561852346
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.832853498
Short name T228
Test name
Test status
Simulation time 348256908628 ps
CPU time 215.53 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:40:12 PM PDT 24
Peak memory 217612 kb
Host smart-ca137ce7-5632-422f-b5df-3bb7f15dcf16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832853498 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.832853498
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.222563344
Short name T197
Test name
Test status
Simulation time 556941153534 ps
CPU time 1388.9 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 01:00:36 PM PDT 24
Peak memory 201940 kb
Host smart-dc97ef6e-cf8e-4dac-8344-57bcb443ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222563344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.222563344
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.621807000
Short name T189
Test name
Test status
Simulation time 356853019948 ps
CPU time 839.62 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 201940 kb
Host smart-7c24b7c7-b82a-473c-910e-2595bc6d74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621807000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.621807000
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.99690848
Short name T217
Test name
Test status
Simulation time 501235096624 ps
CPU time 1148.15 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:57:44 PM PDT 24
Peak memory 201812 kb
Host smart-5994e1c3-3d13-4782-907d-9bdbeaa86559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99690848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.99690848
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3219621028
Short name T233
Test name
Test status
Simulation time 351168719161 ps
CPU time 110.18 seconds
Started Mar 12 12:40:18 PM PDT 24
Finished Mar 12 12:42:09 PM PDT 24
Peak memory 201800 kb
Host smart-329c6265-59c0-4739-a0be-75d4a7402666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219621028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3219621028
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.4149007962
Short name T219
Test name
Test status
Simulation time 336160417718 ps
CPU time 78.77 seconds
Started Mar 12 12:40:08 PM PDT 24
Finished Mar 12 12:41:28 PM PDT 24
Peak memory 201812 kb
Host smart-48e89f4b-eb7d-4612-88a0-33f4dd3fbc15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149007962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.4149007962
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2273094361
Short name T20
Test name
Test status
Simulation time 387621687737 ps
CPU time 376.04 seconds
Started Mar 12 12:37:34 PM PDT 24
Finished Mar 12 12:43:50 PM PDT 24
Peak memory 210384 kb
Host smart-fad281bb-903a-4ebc-ad5f-c135cc08eb05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273094361 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2273094361
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4157119384
Short name T158
Test name
Test status
Simulation time 324871511308 ps
CPU time 802.35 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:50:39 PM PDT 24
Peak memory 201792 kb
Host smart-368d0d48-e528-4494-b52c-0354d11af433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157119384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4157119384
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1046390166
Short name T282
Test name
Test status
Simulation time 32180549716 ps
CPU time 64.27 seconds
Started Mar 12 12:37:17 PM PDT 24
Finished Mar 12 12:38:22 PM PDT 24
Peak memory 210060 kb
Host smart-8a53d730-8794-4c57-a1c5-95ab1d544cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046390166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1046390166
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3725294295
Short name T11
Test name
Test status
Simulation time 493142762203 ps
CPU time 1100.4 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:54:46 PM PDT 24
Peak memory 201896 kb
Host smart-30dac956-7797-47a4-97b8-293f4d0aa57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725294295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3725294295
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4247967106
Short name T249
Test name
Test status
Simulation time 502966517620 ps
CPU time 234.46 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:40:38 PM PDT 24
Peak memory 201756 kb
Host smart-128d9d5d-0f65-436c-97c8-54a48da6e6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247967106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4247967106
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4042825283
Short name T102
Test name
Test status
Simulation time 52028572242 ps
CPU time 84.07 seconds
Started Mar 12 12:59:01 PM PDT 24
Finished Mar 12 01:00:25 PM PDT 24
Peak memory 200832 kb
Host smart-49014c3a-6576-46ec-9eb3-f1aa25a4294c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042825283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4042825283
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3471695343
Short name T19
Test name
Test status
Simulation time 326453569576 ps
CPU time 497.56 seconds
Started Mar 12 12:38:33 PM PDT 24
Finished Mar 12 12:46:51 PM PDT 24
Peak memory 209632 kb
Host smart-b7fcf0ca-590b-4095-9ee7-a1e7d5cba4cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471695343 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3471695343
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2424142177
Short name T286
Test name
Test status
Simulation time 519915372850 ps
CPU time 1337.17 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:58:44 PM PDT 24
Peak memory 201792 kb
Host smart-e75d6759-699f-4ac4-8044-f8cc044225d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424142177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2424142177
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1897381566
Short name T134
Test name
Test status
Simulation time 494186948059 ps
CPU time 325.04 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:43:01 PM PDT 24
Peak memory 201808 kb
Host smart-d7b9e7f4-f47a-4f42-adf1-c4aac5c4c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897381566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1897381566
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1758017141
Short name T272
Test name
Test status
Simulation time 273418474205 ps
CPU time 683.99 seconds
Started Mar 12 12:39:19 PM PDT 24
Finished Mar 12 12:50:44 PM PDT 24
Peak memory 210512 kb
Host smart-07ac9162-1713-45d9-acfb-e168f2f915f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758017141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1758017141
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.4124563060
Short name T246
Test name
Test status
Simulation time 554214998823 ps
CPU time 1190.46 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:59:49 PM PDT 24
Peak memory 201776 kb
Host smart-154e2030-e0dd-4081-81a0-76ea308238df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124563060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.4124563060
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.260570225
Short name T310
Test name
Test status
Simulation time 128139726243 ps
CPU time 462.13 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 201916 kb
Host smart-b3212cbc-8c40-436f-8294-34384f64d340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260570225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.260570225
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1359975996
Short name T70
Test name
Test status
Simulation time 8274291617 ps
CPU time 16.26 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:24 PM PDT 24
Peak memory 200844 kb
Host smart-410d5e05-aeb0-41fa-a83c-29bd3241c823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359975996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1359975996
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2570718980
Short name T65
Test name
Test status
Simulation time 552059556 ps
CPU time 2.3 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200872 kb
Host smart-b8d8a050-11de-4de8-b0b5-7f64089a3c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570718980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2570718980
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1621771568
Short name T220
Test name
Test status
Simulation time 514224387470 ps
CPU time 361.34 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:42:18 PM PDT 24
Peak memory 201908 kb
Host smart-031f557a-0cfe-4772-b3b0-48cf1d3d6846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621771568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1621771568
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2031903764
Short name T224
Test name
Test status
Simulation time 529822850625 ps
CPU time 431.97 seconds
Started Mar 12 12:36:59 PM PDT 24
Finished Mar 12 12:44:12 PM PDT 24
Peak memory 201760 kb
Host smart-9b86318e-d01f-49f2-8852-d2b268637b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031903764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2031903764
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2472809767
Short name T256
Test name
Test status
Simulation time 517017095761 ps
CPU time 1177.81 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:57:17 PM PDT 24
Peak memory 201844 kb
Host smart-239164c9-d687-4c09-87ac-ea44d876d318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472809767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2472809767
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.786580081
Short name T237
Test name
Test status
Simulation time 320487307496 ps
CPU time 391.08 seconds
Started Mar 12 12:39:10 PM PDT 24
Finished Mar 12 12:45:42 PM PDT 24
Peak memory 201932 kb
Host smart-5c9225b0-f7fc-4222-913d-3b28b4f01bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786580081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.786580081
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.366240198
Short name T297
Test name
Test status
Simulation time 492059779506 ps
CPU time 305.99 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:41:50 PM PDT 24
Peak memory 201872 kb
Host smart-c329cec8-2cb0-4070-b4ab-ef8ce794d476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366240198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.366240198
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3661474455
Short name T309
Test name
Test status
Simulation time 144434917676 ps
CPU time 731.01 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:48:57 PM PDT 24
Peak memory 201980 kb
Host smart-809f8a4d-2f43-4622-9905-04d11668d3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661474455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3661474455
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.271835516
Short name T140
Test name
Test status
Simulation time 333719747690 ps
CPU time 843.55 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 201752 kb
Host smart-f6139269-cf2a-486d-8644-823a180b99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271835516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.271835516
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.52679413
Short name T485
Test name
Test status
Simulation time 194239592099 ps
CPU time 121.52 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:39:05 PM PDT 24
Peak memory 201884 kb
Host smart-8987b6d9-6e14-4912-b2c6-b046178b7a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52679413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.52679413
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3344694336
Short name T258
Test name
Test status
Simulation time 495958982808 ps
CPU time 1142.08 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:55:21 PM PDT 24
Peak memory 201952 kb
Host smart-e30cdc3d-6228-4700-bf55-d849120d4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344694336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3344694336
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1827703503
Short name T268
Test name
Test status
Simulation time 327931169338 ps
CPU time 196.76 seconds
Started Mar 12 12:37:25 PM PDT 24
Finished Mar 12 12:40:43 PM PDT 24
Peak memory 201780 kb
Host smart-e1380378-e5dd-4224-acce-04e1ed319158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827703503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1827703503
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3933251683
Short name T252
Test name
Test status
Simulation time 339379299394 ps
CPU time 680.87 seconds
Started Mar 12 12:38:21 PM PDT 24
Finished Mar 12 12:49:43 PM PDT 24
Peak memory 201808 kb
Host smart-04eddb09-7694-45ac-94d2-64a45c2c1901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933251683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3933251683
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3819830009
Short name T202
Test name
Test status
Simulation time 378669099629 ps
CPU time 129.73 seconds
Started Mar 12 12:40:18 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 201984 kb
Host smart-4bcf2e22-358b-43ed-9cc3-bc375a749e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819830009 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3819830009
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2855348180
Short name T57
Test name
Test status
Simulation time 404891358 ps
CPU time 1.77 seconds
Started Mar 12 12:58:50 PM PDT 24
Finished Mar 12 12:58:52 PM PDT 24
Peak memory 200700 kb
Host smart-de5152f6-06bd-4841-805b-01d63b39442f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855348180 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2855348180
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.4026410761
Short name T303
Test name
Test status
Simulation time 428668800207 ps
CPU time 223.85 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:40:40 PM PDT 24
Peak memory 201848 kb
Host smart-b7f4f605-171c-4cbb-bcee-6c29346fd475
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026410761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.4026410761
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.551266691
Short name T44
Test name
Test status
Simulation time 372760100945 ps
CPU time 813.51 seconds
Started Mar 12 12:38:28 PM PDT 24
Finished Mar 12 12:52:01 PM PDT 24
Peak memory 210196 kb
Host smart-d7e8cba0-474f-4de2-8cc7-b3b3a6ece443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551266691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
551266691
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2285982497
Short name T225
Test name
Test status
Simulation time 562306843406 ps
CPU time 651.78 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:47:08 PM PDT 24
Peak memory 201888 kb
Host smart-d1429f6c-5d7a-4ce2-b64f-b0ba01ded2a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285982497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2285982497
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1371956015
Short name T123
Test name
Test status
Simulation time 491669174186 ps
CPU time 328.98 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 201904 kb
Host smart-855817f6-89fe-47d9-bd7c-440633a87fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371956015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1371956015
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2664641692
Short name T308
Test name
Test status
Simulation time 79835785657 ps
CPU time 418.79 seconds
Started Mar 12 12:37:36 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 202204 kb
Host smart-b56f33ed-b5ac-4fe1-b8b7-aae297dec53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664641692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2664641692
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2392947399
Short name T244
Test name
Test status
Simulation time 619507441719 ps
CPU time 1484.47 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 01:02:41 PM PDT 24
Peak memory 201936 kb
Host smart-4dafc998-baaf-4a0c-9e01-20709840bc5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392947399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2392947399
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.649037186
Short name T317
Test name
Test status
Simulation time 129210626427 ps
CPU time 467.92 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:45:54 PM PDT 24
Peak memory 202136 kb
Host smart-e0f0ca7b-946f-45e2-9e42-2d6879086b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649037186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.649037186
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3806121522
Short name T227
Test name
Test status
Simulation time 274358073503 ps
CPU time 433.62 seconds
Started Mar 12 12:38:36 PM PDT 24
Finished Mar 12 12:45:50 PM PDT 24
Peak memory 202084 kb
Host smart-9ba19e30-2ace-4db9-a6e0-d036b7765a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806121522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3806121522
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.626451014
Short name T204
Test name
Test status
Simulation time 508449129971 ps
CPU time 518.35 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 201876 kb
Host smart-cf093474-97da-4017-a16c-0f59643ddb3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626451014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.626451014
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.435293513
Short name T284
Test name
Test status
Simulation time 491636334377 ps
CPU time 1183.91 seconds
Started Mar 12 12:38:58 PM PDT 24
Finished Mar 12 12:58:43 PM PDT 24
Peak memory 201924 kb
Host smart-e29fdb84-eff8-4d6d-9d8c-a753e05ca4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435293513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.435293513
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.3165225003
Short name T232
Test name
Test status
Simulation time 197405657343 ps
CPU time 250.31 seconds
Started Mar 12 12:39:48 PM PDT 24
Finished Mar 12 12:43:58 PM PDT 24
Peak memory 201896 kb
Host smart-114bf104-38f4-42b1-a616-5e8badf0bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165225003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.3165225003
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1936521168
Short name T314
Test name
Test status
Simulation time 90682095715 ps
CPU time 398.05 seconds
Started Mar 12 12:40:08 PM PDT 24
Finished Mar 12 12:46:47 PM PDT 24
Peak memory 202016 kb
Host smart-e530ee5d-bb56-460b-b4bc-5be096b8d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936521168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1936521168
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.316232478
Short name T94
Test name
Test status
Simulation time 505173387961 ps
CPU time 1199.79 seconds
Started Mar 12 12:41:28 PM PDT 24
Finished Mar 12 01:01:29 PM PDT 24
Peak memory 201764 kb
Host smart-c37179ad-520d-4087-8267-af41b0d869ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316232478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.316232478
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2546019871
Short name T853
Test name
Test status
Simulation time 1190315511 ps
CPU time 3.03 seconds
Started Mar 12 12:58:50 PM PDT 24
Finished Mar 12 12:58:54 PM PDT 24
Peak memory 200732 kb
Host smart-4dff6217-7b92-4b1a-abbc-ca10b870afa5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546019871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2546019871
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2545388751
Short name T893
Test name
Test status
Simulation time 26595635452 ps
CPU time 64.95 seconds
Started Mar 12 12:58:38 PM PDT 24
Finished Mar 12 12:59:43 PM PDT 24
Peak memory 200728 kb
Host smart-9b198123-9df6-4ad9-b37a-08bcf660bcf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545388751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2545388751
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2051345676
Short name T903
Test name
Test status
Simulation time 1189951965 ps
CPU time 3.74 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 200428 kb
Host smart-3a347728-9e2d-42b6-a6b3-3a1f6b73b61d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051345676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2051345676
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4189794031
Short name T880
Test name
Test status
Simulation time 551517958 ps
CPU time 1.09 seconds
Started Mar 12 12:58:45 PM PDT 24
Finished Mar 12 12:58:46 PM PDT 24
Peak memory 200536 kb
Host smart-b645859b-03bd-4cce-9bcd-369b26a2486f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189794031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4189794031
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1831380429
Short name T819
Test name
Test status
Simulation time 504801541 ps
CPU time 0.99 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:50 PM PDT 24
Peak memory 199168 kb
Host smart-445797bf-92ba-4674-8037-3df0bc53e92d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831380429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1831380429
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2155983631
Short name T895
Test name
Test status
Simulation time 4724470639 ps
CPU time 2.06 seconds
Started Mar 12 12:58:53 PM PDT 24
Finished Mar 12 12:58:56 PM PDT 24
Peak memory 200904 kb
Host smart-62c7a5dd-6b56-497b-9f7f-0103334ef0f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155983631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2155983631
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3728647852
Short name T872
Test name
Test status
Simulation time 525902817 ps
CPU time 2.73 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 200908 kb
Host smart-800696b9-2f33-4b22-8d2a-2b6693da6a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728647852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3728647852
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3400359036
Short name T820
Test name
Test status
Simulation time 4729506392 ps
CPU time 4.28 seconds
Started Mar 12 12:59:48 PM PDT 24
Finished Mar 12 12:59:53 PM PDT 24
Peak memory 199464 kb
Host smart-afe926bf-1860-41c2-ab9e-bcb885ef2c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400359036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3400359036
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.420887533
Short name T115
Test name
Test status
Simulation time 1237745410 ps
CPU time 2.25 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 200556 kb
Host smart-a5b02d2c-a555-4958-b5e8-1eb2c8165242
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420887533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.420887533
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2535890752
Short name T60
Test name
Test status
Simulation time 345020313 ps
CPU time 1.58 seconds
Started Mar 12 12:59:00 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200732 kb
Host smart-071e6e6a-8a5b-4990-a1ad-578a37ce18cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535890752 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2535890752
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2198703439
Short name T910
Test name
Test status
Simulation time 478624415 ps
CPU time 1.06 seconds
Started Mar 12 12:58:58 PM PDT 24
Finished Mar 12 12:58:59 PM PDT 24
Peak memory 200564 kb
Host smart-a6aa77f5-7914-40e6-b556-9007fc54cd50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198703439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2198703439
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.606503545
Short name T848
Test name
Test status
Simulation time 365344084 ps
CPU time 1.09 seconds
Started Mar 12 12:58:58 PM PDT 24
Finished Mar 12 12:58:59 PM PDT 24
Peak memory 200592 kb
Host smart-1602c830-1d6a-4ce8-9e7b-2527f59b1f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606503545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.606503545
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3941019803
Short name T846
Test name
Test status
Simulation time 2263362776 ps
CPU time 3.66 seconds
Started Mar 12 12:59:02 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 200732 kb
Host smart-d76ecdca-c245-4660-97f1-a9d1991d3859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941019803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3941019803
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.210786385
Short name T888
Test name
Test status
Simulation time 385258329 ps
CPU time 2.66 seconds
Started Mar 12 12:58:50 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 200868 kb
Host smart-52b30603-2c7c-4990-a057-6230c883a2ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210786385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.210786385
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1699552091
Short name T305
Test name
Test status
Simulation time 4432619133 ps
CPU time 4.39 seconds
Started Mar 12 12:58:58 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200900 kb
Host smart-3d4fd7f6-4330-4570-b813-a4a712ef742d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699552091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1699552091
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3694274564
Short name T83
Test name
Test status
Simulation time 566932715 ps
CPU time 2.05 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200704 kb
Host smart-dcb80aec-4821-4019-9cd5-b5893dbec761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694274564 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3694274564
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3158742049
Short name T858
Test name
Test status
Simulation time 494125116 ps
CPU time 1.26 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200556 kb
Host smart-01a1f3be-5ce1-4f3e-9ad5-95dd9994d295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158742049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3158742049
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1183401628
Short name T806
Test name
Test status
Simulation time 394542512 ps
CPU time 0.86 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:05 PM PDT 24
Peak memory 200532 kb
Host smart-2ce71655-daf5-4973-b66e-c80c854690e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183401628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1183401628
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.986461731
Short name T878
Test name
Test status
Simulation time 2046344569 ps
CPU time 1.55 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 200640 kb
Host smart-098c75d9-f38f-4b24-bec6-18b58465aa13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986461731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.986461731
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2589359654
Short name T850
Test name
Test status
Simulation time 529802780 ps
CPU time 2.11 seconds
Started Mar 12 12:59:07 PM PDT 24
Finished Mar 12 12:59:09 PM PDT 24
Peak memory 200868 kb
Host smart-c31f85e3-27c3-41b9-b5c7-4946ef3c0158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589359654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2589359654
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1859553635
Short name T839
Test name
Test status
Simulation time 8310607347 ps
CPU time 6.22 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200832 kb
Host smart-078b8e70-900b-40e4-80ee-dc1c60706ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859553635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1859553635
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.4225756695
Short name T813
Test name
Test status
Simulation time 335130084 ps
CPU time 1.2 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200700 kb
Host smart-75e16af5-e073-46e2-b62b-54456bd99d3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225756695 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.4225756695
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3695427150
Short name T845
Test name
Test status
Simulation time 523183886 ps
CPU time 0.87 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200568 kb
Host smart-26f83f6a-4093-48f1-9f5d-8e2a27e8ba57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695427150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3695427150
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.95562765
Short name T836
Test name
Test status
Simulation time 531522080 ps
CPU time 1.02 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200516 kb
Host smart-fcddf016-c55c-42e3-91c7-113f712e02d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95562765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.95562765
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1044850597
Short name T111
Test name
Test status
Simulation time 4317414658 ps
CPU time 3.68 seconds
Started Mar 12 12:59:02 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 200920 kb
Host smart-c3d962a8-f8e0-4cc0-a5d8-c8bc4255ef74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044850597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1044850597
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1102550738
Short name T866
Test name
Test status
Simulation time 475231104 ps
CPU time 3.65 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 217192 kb
Host smart-d88ef6ef-9ae9-4777-ac8e-0f8d3c72b2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102550738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1102550738
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.286058537
Short name T864
Test name
Test status
Simulation time 4428957245 ps
CPU time 4.25 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 201188 kb
Host smart-b6f189b2-21ca-48cc-ae64-bc2da5267f13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286058537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.286058537
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.690986392
Short name T812
Test name
Test status
Simulation time 881152539 ps
CPU time 1.23 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200700 kb
Host smart-b66968f2-9dfc-45e1-9a33-b37b82d66883
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690986392 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.690986392
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1057962121
Short name T107
Test name
Test status
Simulation time 352695291 ps
CPU time 1.1 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200572 kb
Host smart-1ce73ba0-7abd-4fa3-ae69-846c303298e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057962121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1057962121
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3415983219
Short name T857
Test name
Test status
Simulation time 436241111 ps
CPU time 1.82 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200564 kb
Host smart-1fbdb102-48a4-4d53-a581-fc7a3d0f304e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415983219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3415983219
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1617847128
Short name T832
Test name
Test status
Simulation time 4995118062 ps
CPU time 2.93 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:09 PM PDT 24
Peak memory 200884 kb
Host smart-d54223dd-4881-438b-bb9c-c09baa872e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617847128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1617847128
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3471671622
Short name T863
Test name
Test status
Simulation time 983046754 ps
CPU time 2.61 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200936 kb
Host smart-b0b8759e-c17c-4f7c-9a76-059d45344ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471671622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3471671622
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2679699122
Short name T841
Test name
Test status
Simulation time 520103449 ps
CPU time 2.05 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:09 PM PDT 24
Peak memory 200664 kb
Host smart-fc361ef5-1437-4aa1-9d4c-8df902fdbb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679699122 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2679699122
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.875720302
Short name T907
Test name
Test status
Simulation time 561107961 ps
CPU time 1.34 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:05 PM PDT 24
Peak memory 200572 kb
Host smart-1ca7171d-7070-494e-a7a0-56486687bfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875720302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.875720302
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.883618806
Short name T879
Test name
Test status
Simulation time 311685639 ps
CPU time 0.95 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 200548 kb
Host smart-7cc94e97-77f5-4397-91ba-7cf285c29a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883618806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.883618806
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.801807056
Short name T815
Test name
Test status
Simulation time 2122197570 ps
CPU time 2.56 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200516 kb
Host smart-34020898-3b86-4a7d-ab90-3ae0e4f78383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801807056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.801807056
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3982140887
Short name T829
Test name
Test status
Simulation time 777058203 ps
CPU time 2.69 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200832 kb
Host smart-3a3c1382-8db8-4b89-9ee5-2f1fed2e41ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982140887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3982140887
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.560572055
Short name T890
Test name
Test status
Simulation time 8045789224 ps
CPU time 11.45 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 200896 kb
Host smart-05803581-b5ea-4717-9931-29dccb0203ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560572055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.560572055
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1716322673
Short name T886
Test name
Test status
Simulation time 1016690883 ps
CPU time 1.15 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200720 kb
Host smart-b155583a-0126-42df-ba79-59593d3dc9ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716322673 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1716322673
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.674834571
Short name T908
Test name
Test status
Simulation time 499827317 ps
CPU time 1.02 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200536 kb
Host smart-6269c608-7832-4d02-83f7-4b77f29c0756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674834571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.674834571
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.74037715
Short name T817
Test name
Test status
Simulation time 430507388 ps
CPU time 0.86 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200564 kb
Host smart-c8818ffb-90cc-4a72-8bad-3c9e6836cad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74037715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.74037715
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1562496239
Short name T874
Test name
Test status
Simulation time 2370606414 ps
CPU time 8.73 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200700 kb
Host smart-450b5014-e16a-4816-a1d7-501baf981ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562496239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1562496239
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3701745416
Short name T859
Test name
Test status
Simulation time 556101666 ps
CPU time 3.56 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200892 kb
Host smart-48c3367e-9f2f-443c-8a5a-fa8e7fa66d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701745416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3701745416
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3101921041
Short name T64
Test name
Test status
Simulation time 8190609658 ps
CPU time 20 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:25 PM PDT 24
Peak memory 201188 kb
Host smart-ea53e87c-01a9-4796-afc1-152e2d777ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101921041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3101921041
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2169061225
Short name T82
Test name
Test status
Simulation time 535990262 ps
CPU time 2.1 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200712 kb
Host smart-2517d9fe-f35a-4367-94b9-f7f6897c63d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169061225 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2169061225
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1056626575
Short name T98
Test name
Test status
Simulation time 557493914 ps
CPU time 1.45 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200448 kb
Host smart-11195bce-5ae1-497f-837a-92e1d39019c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056626575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1056626575
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1563340856
Short name T793
Test name
Test status
Simulation time 395927765 ps
CPU time 1.08 seconds
Started Mar 12 12:59:07 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 200612 kb
Host smart-f5751d5d-a1a5-4f81-b86b-536a9a6397ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563340856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1563340856
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1778453427
Short name T901
Test name
Test status
Simulation time 1984266425 ps
CPU time 5.26 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200608 kb
Host smart-9b0e8eff-4edb-4fd6-bd92-07bcc7d9195b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778453427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1778453427
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1667584858
Short name T855
Test name
Test status
Simulation time 1369053178 ps
CPU time 2.14 seconds
Started Mar 12 12:59:02 PM PDT 24
Finished Mar 12 12:59:05 PM PDT 24
Peak memory 200816 kb
Host smart-579e1e33-0db2-4d9d-9d50-f72d772f2ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667584858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1667584858
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3877076396
Short name T884
Test name
Test status
Simulation time 8558672187 ps
CPU time 6.43 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200896 kb
Host smart-b5e6eccf-efd7-49eb-b4f9-83ac7ec47415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877076396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3877076396
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2560136569
Short name T52
Test name
Test status
Simulation time 449337290 ps
CPU time 1.45 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200700 kb
Host smart-afd2d1c1-f51b-4ee4-aee0-c7dd2d641ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560136569 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2560136569
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1913848673
Short name T110
Test name
Test status
Simulation time 456537660 ps
CPU time 1.95 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200448 kb
Host smart-7e88100a-6391-42d0-b62a-e98a52031ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913848673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1913848673
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.366572220
Short name T792
Test name
Test status
Simulation time 471127318 ps
CPU time 1.71 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200556 kb
Host smart-e4933959-a067-463b-bc87-bffd10de5429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366572220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.366572220
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3959975722
Short name T821
Test name
Test status
Simulation time 2555236086 ps
CPU time 5.54 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 200684 kb
Host smart-f016aa01-7e71-40df-8740-9821bb8c6fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959975722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3959975722
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1875643124
Short name T875
Test name
Test status
Simulation time 898666300 ps
CPU time 2.22 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200864 kb
Host smart-4bf9bba5-753b-4e9b-bdb8-5e6c1cb344d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875643124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1875643124
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1095870118
Short name T861
Test name
Test status
Simulation time 4596743354 ps
CPU time 6.98 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 200912 kb
Host smart-3d89887a-d9e3-4489-97e7-f5b0bbd1e2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095870118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1095870118
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2233825650
Short name T906
Test name
Test status
Simulation time 584376480 ps
CPU time 1.3 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200380 kb
Host smart-ee577439-18e0-4b22-897f-cf0fa4b34349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233825650 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2233825650
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1400519412
Short name T116
Test name
Test status
Simulation time 567515764 ps
CPU time 2.03 seconds
Started Mar 12 12:59:26 PM PDT 24
Finished Mar 12 12:59:28 PM PDT 24
Peak memory 200604 kb
Host smart-3ede3624-e32f-4406-bdd0-253ed06d26fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400519412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1400519412
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3045751743
Short name T798
Test name
Test status
Simulation time 421079295 ps
CPU time 1.59 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200596 kb
Host smart-9be8e87d-01f4-4584-b8e6-a70eceba830b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045751743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3045751743
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1708143694
Short name T68
Test name
Test status
Simulation time 601302474 ps
CPU time 2.46 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 210104 kb
Host smart-deb60c4e-7520-4559-95bc-8641d5022ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708143694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1708143694
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3048970259
Short name T802
Test name
Test status
Simulation time 4504211779 ps
CPU time 4.61 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200936 kb
Host smart-b4d7b97a-bff5-4135-aaba-9f20f5d39753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048970259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3048970259
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1422128842
Short name T854
Test name
Test status
Simulation time 395480919 ps
CPU time 1.08 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200724 kb
Host smart-c9a89d8a-5a57-4f6a-8c40-148a05f011c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422128842 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1422128842
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4161288513
Short name T101
Test name
Test status
Simulation time 719895816 ps
CPU time 0.86 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 200560 kb
Host smart-7f77275c-2c39-41cb-a1c2-57dfd485e410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161288513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4161288513
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3008734565
Short name T824
Test name
Test status
Simulation time 404761472 ps
CPU time 0.92 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200600 kb
Host smart-f835bbac-b8fd-492f-ae21-56e21dcdc782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008734565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3008734565
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.279249273
Short name T887
Test name
Test status
Simulation time 2455838852 ps
CPU time 6.38 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200688 kb
Host smart-e873b45d-8c4e-412e-a036-4501dcdf0554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279249273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.279249273
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3730898871
Short name T304
Test name
Test status
Simulation time 8632940846 ps
CPU time 12.22 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:23 PM PDT 24
Peak memory 200864 kb
Host smart-2817ea92-7868-4031-a1bf-2744c5ae0a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730898871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3730898871
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3421578632
Short name T67
Test name
Test status
Simulation time 747449130 ps
CPU time 0.92 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200752 kb
Host smart-eeb958a8-c587-443d-9c0e-68efff334c1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421578632 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3421578632
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3896244380
Short name T113
Test name
Test status
Simulation time 513885808 ps
CPU time 1.86 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200624 kb
Host smart-561abf02-a200-4785-a53e-b479f1909300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896244380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3896244380
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2483773422
Short name T823
Test name
Test status
Simulation time 411770703 ps
CPU time 0.86 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200584 kb
Host smart-814b0235-a5ac-47cb-b680-0bcb9e05f278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483773422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2483773422
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.539866529
Short name T114
Test name
Test status
Simulation time 2442613532 ps
CPU time 2.2 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200696 kb
Host smart-c8c9e965-5133-4f8c-88bd-331e83653c6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539866529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.539866529
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1072036330
Short name T840
Test name
Test status
Simulation time 512776407 ps
CPU time 2.35 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:19 PM PDT 24
Peak memory 200868 kb
Host smart-6c420fdb-8c2f-4aec-bdea-ed7859e36f04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072036330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1072036330
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3291231424
Short name T834
Test name
Test status
Simulation time 4383994518 ps
CPU time 6.43 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 200880 kb
Host smart-198a4d9b-e0f6-4f6a-b297-189c6118a743
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291231424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3291231424
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1439640742
Short name T95
Test name
Test status
Simulation time 728258509 ps
CPU time 2.46 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200708 kb
Host smart-2efa8027-0f7d-4ff3-ac68-d60f4493a761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439640742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1439640742
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1525740163
Short name T897
Test name
Test status
Simulation time 26205889190 ps
CPU time 19.65 seconds
Started Mar 12 12:58:57 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200812 kb
Host smart-634c9316-e6f9-455e-a79e-ee5337e95b66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525740163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1525740163
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.523876490
Short name T867
Test name
Test status
Simulation time 747817525 ps
CPU time 1.5 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 200592 kb
Host smart-c79d2fc0-77d0-416d-ab9a-70149babe67e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523876490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.523876490
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1877986653
Short name T69
Test name
Test status
Simulation time 502361523 ps
CPU time 1.08 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 200700 kb
Host smart-121f69d6-fc51-474d-992c-c11afb91976d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877986653 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1877986653
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2031182598
Short name T881
Test name
Test status
Simulation time 381694600 ps
CPU time 0.89 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:00 PM PDT 24
Peak memory 200580 kb
Host smart-df5082ac-4414-4fc7-bac3-f77e0fb357f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031182598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2031182598
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3538623883
Short name T865
Test name
Test status
Simulation time 351549201 ps
CPU time 1.45 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200548 kb
Host smart-ff93f04f-556c-4d21-aee1-825894669009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538623883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3538623883
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1939114959
Short name T833
Test name
Test status
Simulation time 2077300278 ps
CPU time 5.78 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200616 kb
Host smart-44bdf154-4610-4cc2-9c7b-570bfd181d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939114959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1939114959
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.625091098
Short name T59
Test name
Test status
Simulation time 1135545613 ps
CPU time 2.26 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 217000 kb
Host smart-7eb88d30-b753-4500-a948-eb9723d034b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625091098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.625091098
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3199311015
Short name T49
Test name
Test status
Simulation time 9096321685 ps
CPU time 5.56 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 200856 kb
Host smart-a03ec282-edd9-42c4-b251-a34423877221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199311015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3199311015
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1585446788
Short name T885
Test name
Test status
Simulation time 528536839 ps
CPU time 1.7 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200548 kb
Host smart-63b0469e-6885-4bb1-98b2-afac34d87c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585446788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1585446788
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.278171322
Short name T814
Test name
Test status
Simulation time 527585324 ps
CPU time 1.72 seconds
Started Mar 12 12:59:10 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200588 kb
Host smart-e7adfd48-ae81-4917-8747-dd2fd161da70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278171322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.278171322
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.883307886
Short name T816
Test name
Test status
Simulation time 290648985 ps
CPU time 0.89 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200596 kb
Host smart-74e953d1-5529-48b4-8e92-5a0a380f406d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883307886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.883307886
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3802212299
Short name T905
Test name
Test status
Simulation time 322932809 ps
CPU time 1.32 seconds
Started Mar 12 12:59:18 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 200568 kb
Host smart-2d95f438-2f0e-4670-a6b4-b6277a23389a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802212299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3802212299
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.348365260
Short name T797
Test name
Test status
Simulation time 550002219 ps
CPU time 0.97 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200564 kb
Host smart-99f66207-2b36-4d06-8310-b9ba1a2fe95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348365260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.348365260
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.37668007
Short name T891
Test name
Test status
Simulation time 539110693 ps
CPU time 0.93 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200536 kb
Host smart-b128b2e2-fb46-4217-a03f-0857e486a1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.37668007
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2491824182
Short name T800
Test name
Test status
Simulation time 465283618 ps
CPU time 1.81 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200592 kb
Host smart-15cfc427-16f1-4670-9ec8-6501acfc6992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491824182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2491824182
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2941001200
Short name T902
Test name
Test status
Simulation time 399418996 ps
CPU time 0.8 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200552 kb
Host smart-fce096e7-6988-4c81-a273-27ad5d0538f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941001200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2941001200
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1385359839
Short name T892
Test name
Test status
Simulation time 343342613 ps
CPU time 0.95 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200424 kb
Host smart-2f186efb-5d1d-413b-b922-dcb29803df2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385359839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1385359839
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1843805167
Short name T883
Test name
Test status
Simulation time 528929881 ps
CPU time 0.95 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200576 kb
Host smart-999e5996-1535-47cf-88f9-150d63a6bb1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843805167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1843805167
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3355751560
Short name T104
Test name
Test status
Simulation time 868582979 ps
CPU time 4.54 seconds
Started Mar 12 12:58:48 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 200736 kb
Host smart-57ab1f63-dd6f-470f-8264-f947a9ec54b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355751560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3355751560
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.553846928
Short name T105
Test name
Test status
Simulation time 2643496330 ps
CPU time 3.5 seconds
Started Mar 12 01:00:05 PM PDT 24
Finished Mar 12 01:00:08 PM PDT 24
Peak memory 200628 kb
Host smart-9ffc5cb9-1af7-426d-bf84-8d6d98b34d79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553846928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.553846928
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1159098999
Short name T899
Test name
Test status
Simulation time 700206478 ps
CPU time 1.81 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:01 PM PDT 24
Peak memory 200588 kb
Host smart-42a9cbd9-6433-4e39-9b84-88754dcf110f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159098999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1159098999
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.74314315
Short name T851
Test name
Test status
Simulation time 390220877 ps
CPU time 1.75 seconds
Started Mar 12 01:00:07 PM PDT 24
Finished Mar 12 01:00:10 PM PDT 24
Peak memory 200520 kb
Host smart-2816c0f5-5350-401e-8e3a-6863f0454472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74314315 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.74314315
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2379175496
Short name T97
Test name
Test status
Simulation time 397537707 ps
CPU time 1.26 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:01 PM PDT 24
Peak memory 200588 kb
Host smart-2b6aed22-91d4-46ff-ad87-e921d5b0cb8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379175496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2379175496
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2712735052
Short name T896
Test name
Test status
Simulation time 414163800 ps
CPU time 1.6 seconds
Started Mar 12 12:58:56 PM PDT 24
Finished Mar 12 12:58:58 PM PDT 24
Peak memory 200512 kb
Host smart-b2269488-7f47-44fc-b834-30c2a32041d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712735052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2712735052
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3993592169
Short name T47
Test name
Test status
Simulation time 2462479380 ps
CPU time 6.14 seconds
Started Mar 12 12:59:01 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 200560 kb
Host smart-3bec902f-8c7a-49c6-a6f6-c506c3b9453a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993592169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3993592169
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.481496626
Short name T63
Test name
Test status
Simulation time 477826149 ps
CPU time 2.29 seconds
Started Mar 12 12:58:51 PM PDT 24
Finished Mar 12 12:58:54 PM PDT 24
Peak memory 200896 kb
Host smart-5a2228eb-4122-4b32-879d-17f303e70c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481496626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.481496626
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2216991669
Short name T862
Test name
Test status
Simulation time 5143972581 ps
CPU time 4.77 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200864 kb
Host smart-8b226e86-a8a1-49ed-b042-e1100d7368bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216991669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2216991669
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2002082813
Short name T825
Test name
Test status
Simulation time 517561199 ps
CPU time 0.95 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200564 kb
Host smart-6610e362-e87a-459c-a4d0-759bdf430f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002082813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2002082813
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3337936224
Short name T835
Test name
Test status
Simulation time 390506375 ps
CPU time 1.54 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200548 kb
Host smart-b3160509-049e-4f86-9aed-71d1246098e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337936224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3337936224
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1067952936
Short name T807
Test name
Test status
Simulation time 317017645 ps
CPU time 1.33 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200516 kb
Host smart-af449832-5a0e-4574-9184-1f3cc7cdab4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067952936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1067952936
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2910064856
Short name T889
Test name
Test status
Simulation time 446838032 ps
CPU time 1.34 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200552 kb
Host smart-277929d1-2050-48cc-8d48-1f2f218b9343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910064856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2910064856
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1613472423
Short name T838
Test name
Test status
Simulation time 385365808 ps
CPU time 0.89 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200496 kb
Host smart-5a7c8ab7-d6a9-411b-bdf8-03a492ee9664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613472423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1613472423
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1464480934
Short name T822
Test name
Test status
Simulation time 312684234 ps
CPU time 1.35 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200588 kb
Host smart-463f771f-a454-4ae8-a0c4-c73099198af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464480934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1464480934
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1782208968
Short name T795
Test name
Test status
Simulation time 671364777 ps
CPU time 0.75 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 200588 kb
Host smart-2566d549-2705-4807-8c1e-bb47fdf6c5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782208968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1782208968
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2886559243
Short name T860
Test name
Test status
Simulation time 441796660 ps
CPU time 1.18 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200552 kb
Host smart-7ac7800d-b38a-4baf-bc2c-4b4ee705fee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886559243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2886559243
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3135457389
Short name T900
Test name
Test status
Simulation time 492732387 ps
CPU time 0.93 seconds
Started Mar 12 01:00:54 PM PDT 24
Finished Mar 12 01:00:55 PM PDT 24
Peak memory 199396 kb
Host smart-0fb6ea3f-3f8d-47f3-b35b-f08c7c19887f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135457389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3135457389
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2986374425
Short name T873
Test name
Test status
Simulation time 450064135 ps
CPU time 0.9 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:22 PM PDT 24
Peak memory 200540 kb
Host smart-5265b696-b2bf-4be8-a36e-a0bfcfda3df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986374425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2986374425
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1383595469
Short name T100
Test name
Test status
Simulation time 1110081750 ps
CPU time 2.57 seconds
Started Mar 12 12:59:04 PM PDT 24
Finished Mar 12 12:59:07 PM PDT 24
Peak memory 200740 kb
Host smart-b3571094-386a-4c54-885d-acf7dff64058
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383595469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1383595469
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1843115729
Short name T869
Test name
Test status
Simulation time 26295135786 ps
CPU time 55.97 seconds
Started Mar 12 12:59:04 PM PDT 24
Finished Mar 12 01:00:00 PM PDT 24
Peak memory 200772 kb
Host smart-81f6ad31-d7cc-4d89-9eba-dedeaf2692ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843115729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1843115729
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1278454848
Short name T99
Test name
Test status
Simulation time 806451644 ps
CPU time 1.17 seconds
Started Mar 12 01:00:05 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 200384 kb
Host smart-b0e67dff-bd7e-48fe-80d3-9fabaa66ba58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278454848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1278454848
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1054656291
Short name T837
Test name
Test status
Simulation time 622368895 ps
CPU time 1.21 seconds
Started Mar 12 12:58:57 PM PDT 24
Finished Mar 12 12:58:58 PM PDT 24
Peak memory 200624 kb
Host smart-1e0bf060-f174-401b-a569-3f039614c9e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054656291 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1054656291
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.744223730
Short name T826
Test name
Test status
Simulation time 405702200 ps
CPU time 1.68 seconds
Started Mar 12 01:00:05 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 200376 kb
Host smart-1918b6bf-95d2-4f35-b02f-758d9d4e65f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744223730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.744223730
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.72189206
Short name T827
Test name
Test status
Simulation time 389736848 ps
CPU time 1.53 seconds
Started Mar 12 12:59:00 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200544 kb
Host smart-25922fd6-1578-47c7-819e-92cb12a1a92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72189206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.72189206
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1552203789
Short name T45
Test name
Test status
Simulation time 4265656729 ps
CPU time 15.08 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 200720 kb
Host smart-1639f0b9-8061-4a5d-9d8f-f97d2693bb19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552203789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1552203789
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2354551580
Short name T808
Test name
Test status
Simulation time 773874070 ps
CPU time 2.15 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200732 kb
Host smart-163302f2-aee7-48f3-aa1a-9d932649c011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354551580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2354551580
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4006516356
Short name T50
Test name
Test status
Simulation time 8505302058 ps
CPU time 13.18 seconds
Started Mar 12 01:00:04 PM PDT 24
Finished Mar 12 01:00:17 PM PDT 24
Peak memory 200656 kb
Host smart-2ff6b750-4758-4170-ba09-b28825a44bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006516356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4006516356
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3088261049
Short name T796
Test name
Test status
Simulation time 546950713 ps
CPU time 0.71 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200592 kb
Host smart-2d1c6728-2136-4392-8bfe-058471e58503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088261049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3088261049
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2866255141
Short name T799
Test name
Test status
Simulation time 390580174 ps
CPU time 0.87 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200536 kb
Host smart-865bc885-4a0b-415f-9a35-23c9141a0942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866255141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2866255141
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.618767858
Short name T856
Test name
Test status
Simulation time 302542904 ps
CPU time 1.36 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:11 PM PDT 24
Peak memory 200336 kb
Host smart-88656b11-af15-41fc-a0a7-5c77c2828950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618767858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.618767858
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3019724277
Short name T805
Test name
Test status
Simulation time 336677003 ps
CPU time 1.35 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:16 PM PDT 24
Peak memory 200528 kb
Host smart-17af72de-bea7-45e5-8874-9e1974e3e2fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019724277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3019724277
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.545138044
Short name T801
Test name
Test status
Simulation time 365987398 ps
CPU time 1.46 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200584 kb
Host smart-fc8fc045-4181-4e03-929b-03148e10c03c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545138044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.545138044
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3537273278
Short name T842
Test name
Test status
Simulation time 509341038 ps
CPU time 1.19 seconds
Started Mar 12 01:01:23 PM PDT 24
Finished Mar 12 01:01:25 PM PDT 24
Peak memory 200416 kb
Host smart-8edabf57-ce23-4a98-a0ee-5d5605a48173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537273278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3537273278
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1613179196
Short name T849
Test name
Test status
Simulation time 425758749 ps
CPU time 1.15 seconds
Started Mar 12 12:59:14 PM PDT 24
Finished Mar 12 12:59:15 PM PDT 24
Peak memory 200516 kb
Host smart-9c77af05-6c47-42d1-a925-76ee5d1f1bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613179196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1613179196
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1138257060
Short name T803
Test name
Test status
Simulation time 427524878 ps
CPU time 1.11 seconds
Started Mar 12 12:59:13 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200532 kb
Host smart-1a7a7113-8c7a-4ab2-b748-004ebc3250d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138257060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1138257060
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3721487519
Short name T852
Test name
Test status
Simulation time 288861685 ps
CPU time 1.32 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200508 kb
Host smart-f8a5fcd9-0b11-452b-ae55-47234aecaa8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721487519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3721487519
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4023684749
Short name T804
Test name
Test status
Simulation time 288179277 ps
CPU time 1.21 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:13 PM PDT 24
Peak memory 200572 kb
Host smart-5498f3d2-4bc3-4669-8a12-858eb24f454e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023684749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4023684749
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3157418240
Short name T894
Test name
Test status
Simulation time 454121590 ps
CPU time 1.27 seconds
Started Mar 12 01:00:05 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 200508 kb
Host smart-678261b4-dbba-4657-a50c-d0ecdfd940f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157418240 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3157418240
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.579183653
Short name T103
Test name
Test status
Simulation time 396623774 ps
CPU time 1.03 seconds
Started Mar 12 12:58:57 PM PDT 24
Finished Mar 12 12:58:58 PM PDT 24
Peak memory 200568 kb
Host smart-513ed1e6-254c-4c77-b7b6-5ee3af1578b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579183653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.579183653
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1915363778
Short name T828
Test name
Test status
Simulation time 456018160 ps
CPU time 1.57 seconds
Started Mar 12 01:00:05 PM PDT 24
Finished Mar 12 01:00:07 PM PDT 24
Peak memory 200368 kb
Host smart-50596d79-8069-473c-810d-6e38c315e52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915363778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1915363778
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.4142724554
Short name T882
Test name
Test status
Simulation time 2147260093 ps
CPU time 7.37 seconds
Started Mar 12 12:59:02 PM PDT 24
Finished Mar 12 12:59:10 PM PDT 24
Peak memory 200616 kb
Host smart-5ad85f97-6389-4759-9334-1bb126215dcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142724554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.4142724554
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.7143417
Short name T870
Test name
Test status
Simulation time 773567617 ps
CPU time 1.96 seconds
Started Mar 12 12:59:04 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 200828 kb
Host smart-7f5eed56-61cd-406c-b4cd-c56d09a4150c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7143417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.7143417
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2524009512
Short name T847
Test name
Test status
Simulation time 8656866483 ps
CPU time 4.61 seconds
Started Mar 12 01:00:04 PM PDT 24
Finished Mar 12 01:00:09 PM PDT 24
Peak memory 200652 kb
Host smart-035a5f38-a9ae-453c-ba3c-1902ee1aa9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524009512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2524009512
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1699213888
Short name T809
Test name
Test status
Simulation time 453666587 ps
CPU time 1.64 seconds
Started Mar 12 12:59:00 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200624 kb
Host smart-4691bd46-f6eb-4b54-b912-7c5823cf4f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699213888 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1699213888
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.614572044
Short name T871
Test name
Test status
Simulation time 458158877 ps
CPU time 1 seconds
Started Mar 12 12:59:00 PM PDT 24
Finished Mar 12 12:59:01 PM PDT 24
Peak memory 200480 kb
Host smart-7154b42c-9aba-4dc9-90bd-4dd29afedbed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614572044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.614572044
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.50359644
Short name T868
Test name
Test status
Simulation time 523197746 ps
CPU time 0.9 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:00 PM PDT 24
Peak memory 200556 kb
Host smart-df9f53fa-bd4c-4fde-b58b-68297abc3a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50359644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.50359644
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.4155539679
Short name T109
Test name
Test status
Simulation time 2071285572 ps
CPU time 3 seconds
Started Mar 12 12:59:09 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200612 kb
Host smart-f03d513f-f2f2-4827-b5bd-758a010700b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155539679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.4155539679
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.607248217
Short name T844
Test name
Test status
Simulation time 676158863 ps
CPU time 2.98 seconds
Started Mar 12 12:59:08 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 217308 kb
Host smart-c9e3aa59-e411-485b-b23d-2382945abe84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607248217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.607248217
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1438680839
Short name T898
Test name
Test status
Simulation time 9099795857 ps
CPU time 4.95 seconds
Started Mar 12 01:00:07 PM PDT 24
Finished Mar 12 01:00:13 PM PDT 24
Peak memory 200688 kb
Host smart-53e5ed24-5171-4274-8503-4d37721fc752
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438680839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1438680839
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.552928481
Short name T66
Test name
Test status
Simulation time 432807189 ps
CPU time 1 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200724 kb
Host smart-f06b0c32-beb5-4597-b9e7-3b66a72ec3a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552928481 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.552928481
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2031388405
Short name T106
Test name
Test status
Simulation time 425790880 ps
CPU time 0.94 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200576 kb
Host smart-dc544425-50fd-4f85-ba10-efafdf18d4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031388405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2031388405
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.990292620
Short name T830
Test name
Test status
Simulation time 355348604 ps
CPU time 1.2 seconds
Started Mar 12 12:59:06 PM PDT 24
Finished Mar 12 12:59:08 PM PDT 24
Peak memory 200532 kb
Host smart-d1f7f7ad-08ca-4a44-b92f-5a113384d096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990292620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.990292620
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.607225681
Short name T811
Test name
Test status
Simulation time 2381195203 ps
CPU time 3.02 seconds
Started Mar 12 12:59:15 PM PDT 24
Finished Mar 12 12:59:23 PM PDT 24
Peak memory 200756 kb
Host smart-123d7b6f-5b31-44dc-89cd-9ddc3fcbe058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607225681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.607225681
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3659066634
Short name T877
Test name
Test status
Simulation time 481900994 ps
CPU time 2.76 seconds
Started Mar 12 12:59:12 PM PDT 24
Finished Mar 12 12:59:14 PM PDT 24
Peak memory 200864 kb
Host smart-741e57c5-ea75-444a-8473-0fad232ca2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659066634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3659066634
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3210646393
Short name T876
Test name
Test status
Simulation time 4159640841 ps
CPU time 10.35 seconds
Started Mar 12 12:59:07 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200840 kb
Host smart-14c6cad0-b584-4aa5-8ff5-367874c906e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210646393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3210646393
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3001201430
Short name T818
Test name
Test status
Simulation time 522448387 ps
CPU time 2.01 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200736 kb
Host smart-6f578a56-7a67-4f47-9bab-15c1e0aca38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001201430 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3001201430
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3034690350
Short name T831
Test name
Test status
Simulation time 377102167 ps
CPU time 1.18 seconds
Started Mar 12 12:59:03 PM PDT 24
Finished Mar 12 12:59:05 PM PDT 24
Peak memory 200588 kb
Host smart-a0221b9a-483f-49f2-92be-5e6a2308e1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034690350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3034690350
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2306300238
Short name T794
Test name
Test status
Simulation time 391244376 ps
CPU time 0.85 seconds
Started Mar 12 12:59:05 PM PDT 24
Finished Mar 12 12:59:06 PM PDT 24
Peak memory 200480 kb
Host smart-1278a491-8428-46cd-8a5e-a5435e6e0323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306300238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2306300238
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1894658269
Short name T46
Test name
Test status
Simulation time 4940211780 ps
CPU time 11.77 seconds
Started Mar 12 12:58:59 PM PDT 24
Finished Mar 12 12:59:12 PM PDT 24
Peak memory 200872 kb
Host smart-eae76471-ab04-4fb4-a888-d0d33940c820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894658269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1894658269
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.826955684
Short name T904
Test name
Test status
Simulation time 364076102 ps
CPU time 2.58 seconds
Started Mar 12 12:59:17 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 200900 kb
Host smart-a18bdc5a-3292-477b-8854-9345cefafd2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826955684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.826955684
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3621930959
Short name T843
Test name
Test status
Simulation time 8445139379 ps
CPU time 12.44 seconds
Started Mar 12 12:59:11 PM PDT 24
Finished Mar 12 12:59:23 PM PDT 24
Peak memory 200720 kb
Host smart-0e285d5c-c356-4033-b7c6-a0ac27a01150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621930959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3621930959
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.521503420
Short name T56
Test name
Test status
Simulation time 392496065 ps
CPU time 1.64 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200672 kb
Host smart-122e3a66-131b-42f9-82f2-e4130adf1eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521503420 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.521503420
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3296094371
Short name T112
Test name
Test status
Simulation time 415307882 ps
CPU time 0.93 seconds
Started Mar 12 12:59:16 PM PDT 24
Finished Mar 12 12:59:17 PM PDT 24
Peak memory 200612 kb
Host smart-8247cab1-899d-4d00-a24b-547d12f601e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296094371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3296094371
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3123846082
Short name T810
Test name
Test status
Simulation time 468452261 ps
CPU time 0.92 seconds
Started Mar 12 12:59:01 PM PDT 24
Finished Mar 12 12:59:02 PM PDT 24
Peak memory 200600 kb
Host smart-bbf415cb-1964-44b6-baed-d4dc0229521c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123846082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3123846082
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3098319454
Short name T909
Test name
Test status
Simulation time 4902987531 ps
CPU time 16.03 seconds
Started Mar 12 12:59:02 PM PDT 24
Finished Mar 12 12:59:18 PM PDT 24
Peak memory 200884 kb
Host smart-5ef78582-4a77-4ec7-a0d2-59f5130607af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098319454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3098319454
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2947723571
Short name T572
Test name
Test status
Simulation time 402883936 ps
CPU time 0.88 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 201720 kb
Host smart-a387eade-9a29-4715-96db-9cfce200a319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947723571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2947723571
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4267198176
Short name T211
Test name
Test status
Simulation time 524497251081 ps
CPU time 320.19 seconds
Started Mar 12 12:36:23 PM PDT 24
Finished Mar 12 12:41:44 PM PDT 24
Peak memory 201812 kb
Host smart-fad3ed9d-e238-4890-90cc-25cb32b6f153
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267198176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4267198176
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1113445189
Short name T175
Test name
Test status
Simulation time 327638236920 ps
CPU time 215.58 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:39:52 PM PDT 24
Peak memory 201864 kb
Host smart-fe17ce8f-cfd3-4648-9cdb-7ba0b47c2ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113445189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1113445189
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1390560098
Short name T708
Test name
Test status
Simulation time 167237540817 ps
CPU time 195.21 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:39:33 PM PDT 24
Peak memory 201876 kb
Host smart-998b6b51-3f45-428c-84ae-9433db121121
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390560098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1390560098
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2149662774
Short name T24
Test name
Test status
Simulation time 491250920649 ps
CPU time 1182.93 seconds
Started Mar 12 12:36:21 PM PDT 24
Finished Mar 12 12:56:04 PM PDT 24
Peak memory 201660 kb
Host smart-b9989be7-06f2-4bf2-aaac-6d5e993dee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149662774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2149662774
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2805623607
Short name T429
Test name
Test status
Simulation time 326374215361 ps
CPU time 200.6 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:39:39 PM PDT 24
Peak memory 201856 kb
Host smart-6c26a205-cec4-4958-84d0-aa3d499e641a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805623607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2805623607
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3004185678
Short name T23
Test name
Test status
Simulation time 522740440344 ps
CPU time 622.16 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:46:49 PM PDT 24
Peak memory 201800 kb
Host smart-baeab89a-c51e-46e7-8bf4-2bac622039bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004185678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3004185678
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1754044571
Short name T323
Test name
Test status
Simulation time 601195405685 ps
CPU time 312.46 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:41:39 PM PDT 24
Peak memory 201512 kb
Host smart-e94289d6-a74b-45df-9ce6-d00a9bc280d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754044571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1754044571
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.340066122
Short name T605
Test name
Test status
Simulation time 89421557801 ps
CPU time 292.76 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:41:11 PM PDT 24
Peak memory 202124 kb
Host smart-e72d58cf-ef53-4957-8dc0-7a0fd5611f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340066122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.340066122
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3286822905
Short name T386
Test name
Test status
Simulation time 38930073223 ps
CPU time 23.58 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:40 PM PDT 24
Peak memory 201684 kb
Host smart-e705a29f-ff63-4305-9be9-83a39179b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286822905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3286822905
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.4029046437
Short name T141
Test name
Test status
Simulation time 3558888466 ps
CPU time 1.86 seconds
Started Mar 12 12:36:20 PM PDT 24
Finished Mar 12 12:36:22 PM PDT 24
Peak memory 201584 kb
Host smart-f834aaa2-ebb4-4bb1-a742-6ad14258ac2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029046437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.4029046437
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2589599098
Short name T587
Test name
Test status
Simulation time 5785678636 ps
CPU time 2.15 seconds
Started Mar 12 12:36:21 PM PDT 24
Finished Mar 12 12:36:24 PM PDT 24
Peak memory 201600 kb
Host smart-2cc52f91-b38d-48d1-bd2b-9bcb164a8e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589599098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2589599098
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2651174479
Short name T85
Test name
Test status
Simulation time 611062137680 ps
CPU time 207.85 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:39:46 PM PDT 24
Peak memory 211340 kb
Host smart-8e60eb88-740e-4ec3-874b-17418ca97cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651174479 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2651174479
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.156450345
Short name T762
Test name
Test status
Simulation time 410878960 ps
CPU time 1.54 seconds
Started Mar 12 12:36:19 PM PDT 24
Finished Mar 12 12:36:21 PM PDT 24
Peak memory 201504 kb
Host smart-18ab9406-48ef-420d-8986-bdf75b20f515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156450345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.156450345
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4227887380
Short name T178
Test name
Test status
Simulation time 513934856464 ps
CPU time 279.41 seconds
Started Mar 12 12:37:52 PM PDT 24
Finished Mar 12 12:42:32 PM PDT 24
Peak memory 200892 kb
Host smart-031ed979-c97f-42de-b6ca-2d3204a65e22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227887380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4227887380
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3293404193
Short name T266
Test name
Test status
Simulation time 497099075584 ps
CPU time 612.66 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:46:27 PM PDT 24
Peak memory 201852 kb
Host smart-50fa5535-aade-4cb2-b902-756b9c8e4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293404193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3293404193
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1757231523
Short name T646
Test name
Test status
Simulation time 161250340859 ps
CPU time 357.57 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:42:15 PM PDT 24
Peak memory 201816 kb
Host smart-871903f5-842f-4ab8-ab6d-2e8d04624997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757231523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1757231523
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2447596765
Short name T693
Test name
Test status
Simulation time 484878404088 ps
CPU time 1069.3 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:54:06 PM PDT 24
Peak memory 201832 kb
Host smart-270b3638-0f61-4c04-836f-24bf03bca422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447596765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2447596765
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3989143106
Short name T717
Test name
Test status
Simulation time 493465114768 ps
CPU time 288.86 seconds
Started Mar 12 12:36:24 PM PDT 24
Finished Mar 12 12:41:13 PM PDT 24
Peak memory 201736 kb
Host smart-80133ecd-e26e-4413-878b-2fe90347b60f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989143106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3989143106
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1271224229
Short name T291
Test name
Test status
Simulation time 179267928975 ps
CPU time 433.65 seconds
Started Mar 12 12:36:22 PM PDT 24
Finished Mar 12 12:43:36 PM PDT 24
Peak memory 201756 kb
Host smart-80138c4e-7208-4931-82b8-c75c1a379455
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271224229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1271224229
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4083517722
Short name T412
Test name
Test status
Simulation time 190509570445 ps
CPU time 126.77 seconds
Started Mar 12 12:36:20 PM PDT 24
Finished Mar 12 12:38:27 PM PDT 24
Peak memory 201740 kb
Host smart-7b3c5700-65ee-4761-908a-e984d7f95d9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083517722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4083517722
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3249112886
Short name T452
Test name
Test status
Simulation time 90174152504 ps
CPU time 351.75 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:42:08 PM PDT 24
Peak memory 202032 kb
Host smart-22b4cbb5-ae49-4461-8edd-4ba456df88a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249112886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3249112886
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1406066486
Short name T2
Test name
Test status
Simulation time 43697930156 ps
CPU time 28.05 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:45 PM PDT 24
Peak memory 201688 kb
Host smart-7cb94e1e-7a01-49e9-b101-6801e7adb0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406066486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1406066486
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1555964148
Short name T493
Test name
Test status
Simulation time 5166723637 ps
CPU time 12.99 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:28 PM PDT 24
Peak memory 201532 kb
Host smart-8be04ac2-1970-4c66-b773-6fd54d0e906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555964148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1555964148
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1430081483
Short name T55
Test name
Test status
Simulation time 8035634920 ps
CPU time 9.07 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:36:27 PM PDT 24
Peak memory 218040 kb
Host smart-28adb081-c0c5-4a10-986e-327dd37dbcb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430081483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1430081483
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3381152337
Short name T363
Test name
Test status
Simulation time 5797893154 ps
CPU time 2.55 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:19 PM PDT 24
Peak memory 201600 kb
Host smart-d5da817c-cf98-4e08-9529-f08cfa28da42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381152337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3381152337
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1740190210
Short name T43
Test name
Test status
Simulation time 241246170624 ps
CPU time 531.83 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:45:18 PM PDT 24
Peak memory 211824 kb
Host smart-696ea4ab-2b30-4ad6-b9e6-e95dd825538e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740190210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1740190210
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2708243367
Short name T650
Test name
Test status
Simulation time 463778618 ps
CPU time 0.84 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:36:46 PM PDT 24
Peak memory 201580 kb
Host smart-c064ab9b-9ec0-41a2-8a5e-0ed931ca0ae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708243367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2708243367
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1889574106
Short name T714
Test name
Test status
Simulation time 394927319373 ps
CPU time 460.41 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:44:27 PM PDT 24
Peak memory 201700 kb
Host smart-90997975-1694-4515-a4dc-bd41ae0f8c93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889574106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1889574106
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2499740963
Short name T431
Test name
Test status
Simulation time 208194013046 ps
CPU time 494.7 seconds
Started Mar 12 12:36:52 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 201876 kb
Host smart-9aad2af2-a159-4dd2-a1d3-3156af351d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499740963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2499740963
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3316891969
Short name T330
Test name
Test status
Simulation time 329537734475 ps
CPU time 548.93 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:45:47 PM PDT 24
Peak memory 201724 kb
Host smart-7f3fa518-67ed-4522-bb79-e7ed1bbcc912
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316891969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3316891969
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.727450792
Short name T639
Test name
Test status
Simulation time 331392151428 ps
CPU time 776.68 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:49:40 PM PDT 24
Peak memory 201760 kb
Host smart-ad1c9158-a690-4a88-b2c2-630ec0445358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727450792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.727450792
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4220624647
Short name T543
Test name
Test status
Simulation time 163942769797 ps
CPU time 100.02 seconds
Started Mar 12 12:36:41 PM PDT 24
Finished Mar 12 12:38:22 PM PDT 24
Peak memory 201768 kb
Host smart-52f82184-70a9-4dc3-8e88-99ada2a0e918
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220624647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4220624647
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1946902143
Short name T614
Test name
Test status
Simulation time 179772109888 ps
CPU time 405.56 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:43:29 PM PDT 24
Peak memory 201828 kb
Host smart-bea3ddc3-38ad-4832-8daf-93c637024b2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946902143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1946902143
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.484249741
Short name T481
Test name
Test status
Simulation time 606483476031 ps
CPU time 1479.11 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 01:01:23 PM PDT 24
Peak memory 201932 kb
Host smart-571e6880-d4bb-4520-a286-91fb5dd1d4ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484249741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.484249741
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3572292463
Short name T319
Test name
Test status
Simulation time 107834967240 ps
CPU time 567.94 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:46:14 PM PDT 24
Peak memory 202020 kb
Host smart-db0443e9-4e84-4903-9dae-265be1a2defb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572292463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3572292463
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.846094184
Short name T527
Test name
Test status
Simulation time 40541556228 ps
CPU time 23.45 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:37:09 PM PDT 24
Peak memory 201680 kb
Host smart-911f6513-0156-49ea-ac45-42260b26c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846094184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.846094184
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3523760392
Short name T512
Test name
Test status
Simulation time 3528773049 ps
CPU time 6.46 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:51 PM PDT 24
Peak memory 201572 kb
Host smart-aaf177bc-e3b5-49e4-9180-8411fe061ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523760392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3523760392
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.874763224
Short name T513
Test name
Test status
Simulation time 5969209254 ps
CPU time 8.04 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:52 PM PDT 24
Peak memory 201608 kb
Host smart-3a77e50e-6d8c-4fa2-8c4a-cc5242e6c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874763224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.874763224
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1328008000
Short name T257
Test name
Test status
Simulation time 508666179694 ps
CPU time 629.18 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:47:13 PM PDT 24
Peak memory 201872 kb
Host smart-1039539e-8c1b-43cf-b9f5-d70d6de56384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328008000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1328008000
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1155202702
Short name T591
Test name
Test status
Simulation time 62667440518 ps
CPU time 153.19 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:39:17 PM PDT 24
Peak memory 210384 kb
Host smart-392b232f-c55d-498a-8e1f-d50f53d4923e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155202702 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1155202702
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1137451575
Short name T666
Test name
Test status
Simulation time 400241741 ps
CPU time 1.51 seconds
Started Mar 12 12:36:48 PM PDT 24
Finished Mar 12 12:36:52 PM PDT 24
Peak memory 201712 kb
Host smart-2cf1b9ed-a6e0-4a45-9075-d6c371f3868b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137451575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1137451575
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1097504192
Short name T656
Test name
Test status
Simulation time 350347673518 ps
CPU time 633.43 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:47:17 PM PDT 24
Peak memory 201868 kb
Host smart-ae897670-64d0-4bba-a5bd-cbb2c9416bcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097504192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1097504192
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4010340375
Short name T743
Test name
Test status
Simulation time 482881399977 ps
CPU time 1061.73 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:54:27 PM PDT 24
Peak memory 201752 kb
Host smart-e0069fb0-9106-490b-9427-63f8644330dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010340375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4010340375
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3737863217
Short name T676
Test name
Test status
Simulation time 495743731181 ps
CPU time 617.14 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:47:03 PM PDT 24
Peak memory 201920 kb
Host smart-d5d927f0-7945-4016-acd8-c0af00414af9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737863217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3737863217
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.638729058
Short name T163
Test name
Test status
Simulation time 167017581500 ps
CPU time 203.4 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:40:08 PM PDT 24
Peak memory 201936 kb
Host smart-bb11ef0b-b5ad-49c6-907b-79132ac9a686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638729058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.638729058
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2665761534
Short name T670
Test name
Test status
Simulation time 490674291412 ps
CPU time 1107.98 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:55:12 PM PDT 24
Peak memory 201776 kb
Host smart-e06ea1d7-ad6a-43b4-92cf-568b2df0ca24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665761534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2665761534
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.676764080
Short name T778
Test name
Test status
Simulation time 366852065444 ps
CPU time 900 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 201788 kb
Host smart-2a6154aa-a36b-4997-82ac-0b547b74e0e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676764080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.676764080
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3785694832
Short name T759
Test name
Test status
Simulation time 205776729084 ps
CPU time 461.09 seconds
Started Mar 12 12:36:48 PM PDT 24
Finished Mar 12 12:44:32 PM PDT 24
Peak memory 201920 kb
Host smart-65e91af1-c028-4d6a-aa1f-e947e865ef6a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785694832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3785694832
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3436956882
Short name T318
Test name
Test status
Simulation time 132811534775 ps
CPU time 469.4 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:44:34 PM PDT 24
Peak memory 202096 kb
Host smart-08bd5c91-82ab-4ae8-b973-487fd224b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436956882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3436956882
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3215824883
Short name T354
Test name
Test status
Simulation time 42264164593 ps
CPU time 94.43 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:38:18 PM PDT 24
Peak memory 201704 kb
Host smart-87f90d1d-4eb7-4c4e-9b1e-f28376e3a363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215824883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3215824883
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.992493529
Short name T327
Test name
Test status
Simulation time 4179916550 ps
CPU time 2.14 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:47 PM PDT 24
Peak memory 201728 kb
Host smart-a8b8d684-0e1d-44f7-ad99-25d3711b6703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992493529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.992493529
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3311856211
Short name T555
Test name
Test status
Simulation time 5614517850 ps
CPU time 3.96 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:48 PM PDT 24
Peak memory 201708 kb
Host smart-643db998-52ef-402b-a579-e25987bc40f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311856211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3311856211
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3826677890
Short name T41
Test name
Test status
Simulation time 249396615188 ps
CPU time 376.72 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:43:03 PM PDT 24
Peak memory 202076 kb
Host smart-71cb0009-bf05-4997-be29-cb78a27a7927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826677890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3826677890
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3563101460
Short name T209
Test name
Test status
Simulation time 1247643797648 ps
CPU time 162.21 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:39:28 PM PDT 24
Peak memory 210284 kb
Host smart-9ada11d5-8d03-49fc-859f-e3730afb814a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563101460 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3563101460
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1502253933
Short name T631
Test name
Test status
Simulation time 472242271 ps
CPU time 1.72 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:36:45 PM PDT 24
Peak memory 201592 kb
Host smart-72def326-7d98-4bcc-8c51-35c68e875078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502253933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1502253933
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2600341546
Short name T756
Test name
Test status
Simulation time 160959385980 ps
CPU time 87.63 seconds
Started Mar 12 12:36:52 PM PDT 24
Finished Mar 12 12:38:20 PM PDT 24
Peak memory 201764 kb
Host smart-6d178199-74e5-4747-a9a0-2d7d9d6951df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600341546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2600341546
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2043547067
Short name T179
Test name
Test status
Simulation time 563604691987 ps
CPU time 219.59 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:40:24 PM PDT 24
Peak memory 201780 kb
Host smart-a436226b-f6e7-4a39-abb6-91cf0597a0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043547067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2043547067
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.4046784061
Short name T619
Test name
Test status
Simulation time 324827143195 ps
CPU time 753.49 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 201712 kb
Host smart-068ba758-ce6a-4e49-ac26-7ae5cd897db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046784061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4046784061
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3235074098
Short name T615
Test name
Test status
Simulation time 165503695863 ps
CPU time 413.9 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 201820 kb
Host smart-8bc5b978-6a57-4053-9324-9b8864fe4a02
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235074098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3235074098
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3413011328
Short name T516
Test name
Test status
Simulation time 318677118790 ps
CPU time 706.91 seconds
Started Mar 12 12:36:50 PM PDT 24
Finished Mar 12 12:48:39 PM PDT 24
Peak memory 201852 kb
Host smart-7c41ef1a-6fe4-4567-ab5d-cc5914499b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413011328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3413011328
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2739242741
Short name T93
Test name
Test status
Simulation time 161390214501 ps
CPU time 397.39 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:43:25 PM PDT 24
Peak memory 201864 kb
Host smart-b0c9f26f-7df1-4c36-a6ba-d5f79500ec96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739242741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2739242741
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2960753998
Short name T674
Test name
Test status
Simulation time 271788272205 ps
CPU time 611.95 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:46:58 PM PDT 24
Peak memory 202128 kb
Host smart-7db4c03b-859d-4832-86fc-f4ed7ffdea5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960753998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2960753998
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1524388410
Short name T729
Test name
Test status
Simulation time 203741697282 ps
CPU time 508.25 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:45:14 PM PDT 24
Peak memory 201876 kb
Host smart-f8bbde66-d618-456d-9dfb-79986ae38c62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524388410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1524388410
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1874870197
Short name T520
Test name
Test status
Simulation time 119905198749 ps
CPU time 662.35 seconds
Started Mar 12 12:36:48 PM PDT 24
Finished Mar 12 12:47:50 PM PDT 24
Peak memory 202052 kb
Host smart-e1ca233e-73be-4f68-b354-bd6037b9c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874870197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1874870197
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1122176985
Short name T667
Test name
Test status
Simulation time 40311014863 ps
CPU time 93.75 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:38:21 PM PDT 24
Peak memory 201408 kb
Host smart-b3a41a06-b57f-44f6-bd80-40c7b71b55c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122176985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1122176985
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2939108530
Short name T118
Test name
Test status
Simulation time 4215386686 ps
CPU time 2.96 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:36:50 PM PDT 24
Peak memory 201676 kb
Host smart-23c111a1-75b6-44e4-92c6-13f463d8d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939108530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2939108530
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2036869570
Short name T782
Test name
Test status
Simulation time 5685020416 ps
CPU time 14.38 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:37:00 PM PDT 24
Peak memory 201624 kb
Host smart-8e4f155b-a1bd-49ab-b5b8-44e9a1ef93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036869570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2036869570
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1299435247
Short name T613
Test name
Test status
Simulation time 6359968759 ps
CPU time 15.53 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:36:59 PM PDT 24
Peak memory 201688 kb
Host smart-abba485c-48b3-4822-a1cd-1b14630cd067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299435247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1299435247
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2418263851
Short name T776
Test name
Test status
Simulation time 148244873627 ps
CPU time 77.21 seconds
Started Mar 12 12:36:42 PM PDT 24
Finished Mar 12 12:38:01 PM PDT 24
Peak memory 202188 kb
Host smart-a1bc4a09-17f2-4c4b-abcc-d9dcaacee98b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418263851 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2418263851
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3152909805
Short name T387
Test name
Test status
Simulation time 469233567 ps
CPU time 1.57 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:36:48 PM PDT 24
Peak memory 201580 kb
Host smart-2e92f568-b3c6-46e5-9525-d4d694de1120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152909805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3152909805
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3408042151
Short name T688
Test name
Test status
Simulation time 167336673403 ps
CPU time 9.93 seconds
Started Mar 12 12:36:53 PM PDT 24
Finished Mar 12 12:37:04 PM PDT 24
Peak memory 201792 kb
Host smart-2c6a8fb5-4751-42d9-a7c4-f3d24397949a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408042151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3408042151
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3328320794
Short name T658
Test name
Test status
Simulation time 164864456793 ps
CPU time 105.57 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:38:32 PM PDT 24
Peak memory 201864 kb
Host smart-307103b7-3543-4021-957f-887551bbefdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328320794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3328320794
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.526031057
Short name T92
Test name
Test status
Simulation time 324302408603 ps
CPU time 731.68 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:48:59 PM PDT 24
Peak memory 201832 kb
Host smart-c4257aa4-d0ac-45e3-8468-6fd292afa53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526031057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.526031057
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.354197940
Short name T771
Test name
Test status
Simulation time 161268661398 ps
CPU time 202.95 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:40:09 PM PDT 24
Peak memory 201756 kb
Host smart-2dc1d656-87f1-426f-830c-f3acba088d04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=354197940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.354197940
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1729927524
Short name T599
Test name
Test status
Simulation time 492645072114 ps
CPU time 1084.93 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:54:52 PM PDT 24
Peak memory 201868 kb
Host smart-a7eaf3a3-fcb4-49a8-a6d4-f4367a6a9527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729927524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1729927524
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1215647327
Short name T760
Test name
Test status
Simulation time 331588668555 ps
CPU time 103.95 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:38:28 PM PDT 24
Peak memory 201748 kb
Host smart-dd722c3d-6bcb-4747-b184-8523ce46abf9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215647327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1215647327
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1912804458
Short name T669
Test name
Test status
Simulation time 372721460017 ps
CPU time 324.13 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:42:11 PM PDT 24
Peak memory 201620 kb
Host smart-8692c16f-4795-4cc9-b352-2666b847946e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912804458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1912804458
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3711277165
Short name T537
Test name
Test status
Simulation time 602326110808 ps
CPU time 747.12 seconds
Started Mar 12 12:36:53 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 201840 kb
Host smart-d46cff51-ae96-4dc1-9dce-9085167f3a9c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711277165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3711277165
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.201278106
Short name T436
Test name
Test status
Simulation time 29419087903 ps
CPU time 17.38 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:37:02 PM PDT 24
Peak memory 201680 kb
Host smart-e197b17d-32d1-48a8-8f8e-cc098fd41b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201278106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.201278106
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2422940292
Short name T424
Test name
Test status
Simulation time 3870809609 ps
CPU time 9.87 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:36:57 PM PDT 24
Peak memory 201676 kb
Host smart-0176612f-7db0-4bd1-b649-e3f45b71c2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422940292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2422940292
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.78098209
Short name T474
Test name
Test status
Simulation time 5868572923 ps
CPU time 7.63 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:36:53 PM PDT 24
Peak memory 201568 kb
Host smart-81278e60-0e97-45e5-a384-2c735f4ffc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78098209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.78098209
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1542024379
Short name T519
Test name
Test status
Simulation time 178039023404 ps
CPU time 195.14 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:40:00 PM PDT 24
Peak memory 201748 kb
Host smart-214f5b1f-c957-4909-8c8b-f5fffd08f2cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542024379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1542024379
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3750607811
Short name T18
Test name
Test status
Simulation time 179670460057 ps
CPU time 104.89 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:38:32 PM PDT 24
Peak memory 201960 kb
Host smart-8112aa9d-543d-4fbc-81de-dcf656ae3f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750607811 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3750607811
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1950956082
Short name T430
Test name
Test status
Simulation time 163190661788 ps
CPU time 234.93 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:40:42 PM PDT 24
Peak memory 201852 kb
Host smart-2621a200-4c48-421a-a96f-95c87184cc04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950956082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1950956082
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1868127238
Short name T710
Test name
Test status
Simulation time 494904666122 ps
CPU time 582.4 seconds
Started Mar 12 12:36:56 PM PDT 24
Finished Mar 12 12:46:40 PM PDT 24
Peak memory 201772 kb
Host smart-e91eeb62-2eea-4dd2-af0f-6892ab11bf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868127238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1868127238
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1153227825
Short name T253
Test name
Test status
Simulation time 169996140672 ps
CPU time 58.63 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:37:45 PM PDT 24
Peak memory 201852 kb
Host smart-b2017052-10ac-4b38-b59c-6ffb97afca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153227825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1153227825
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1088091976
Short name T578
Test name
Test status
Simulation time 331008215985 ps
CPU time 724.62 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:48:52 PM PDT 24
Peak memory 201780 kb
Host smart-90fd0ae8-d423-4000-83e1-901ee94be5b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088091976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1088091976
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1677106335
Short name T259
Test name
Test status
Simulation time 162958316966 ps
CPU time 388.35 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:43:16 PM PDT 24
Peak memory 201856 kb
Host smart-740e2f59-14c0-47a7-ab5a-5009315daec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677106335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1677106335
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3328450953
Short name T738
Test name
Test status
Simulation time 334414343313 ps
CPU time 398.06 seconds
Started Mar 12 12:36:45 PM PDT 24
Finished Mar 12 12:43:23 PM PDT 24
Peak memory 201852 kb
Host smart-5c6b619b-013c-4981-9864-eb89353b3a93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328450953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3328450953
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.664426753
Short name T223
Test name
Test status
Simulation time 195961183427 ps
CPU time 474.13 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 201736 kb
Host smart-7a95cb4a-3c5d-40db-a36e-67f06b8eedf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664426753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.664426753
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1884753317
Short name T332
Test name
Test status
Simulation time 587530149037 ps
CPU time 728.16 seconds
Started Mar 12 12:36:47 PM PDT 24
Finished Mar 12 12:48:56 PM PDT 24
Peak memory 201852 kb
Host smart-22777345-3f27-4d3c-8e82-000eded43cc0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884753317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1884753317
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.958794549
Short name T492
Test name
Test status
Simulation time 81079328412 ps
CPU time 413.63 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 201984 kb
Host smart-ec50bf87-4884-4e09-8655-13139639a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958794549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.958794549
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2677407078
Short name T511
Test name
Test status
Simulation time 40652309813 ps
CPU time 47.84 seconds
Started Mar 12 12:36:54 PM PDT 24
Finished Mar 12 12:37:43 PM PDT 24
Peak memory 201540 kb
Host smart-dc10902f-9067-409b-a0b0-51e02524a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677407078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2677407078
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3161007065
Short name T334
Test name
Test status
Simulation time 4908594996 ps
CPU time 2.53 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:37:19 PM PDT 24
Peak memory 201604 kb
Host smart-57629458-7683-46ef-96b5-388d574b15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161007065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3161007065
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2095204721
Short name T22
Test name
Test status
Simulation time 5621242468 ps
CPU time 4.41 seconds
Started Mar 12 12:36:46 PM PDT 24
Finished Mar 12 12:36:51 PM PDT 24
Peak memory 201708 kb
Host smart-9b208859-01e9-4f50-9f1d-b0964b1537c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095204721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2095204721
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2632713121
Short name T190
Test name
Test status
Simulation time 162354781042 ps
CPU time 389.9 seconds
Started Mar 12 12:36:54 PM PDT 24
Finished Mar 12 12:43:25 PM PDT 24
Peak memory 201876 kb
Host smart-17a35974-e7d9-4476-835a-8fa6b0e733af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632713121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2632713121
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2409537530
Short name T154
Test name
Test status
Simulation time 13770908891 ps
CPU time 28.87 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:37:24 PM PDT 24
Peak memory 202024 kb
Host smart-43c589d9-45eb-4443-9de3-ed9dc85c99ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409537530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2409537530
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3573994414
Short name T495
Test name
Test status
Simulation time 336371352 ps
CPU time 1.4 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:36:58 PM PDT 24
Peak memory 201512 kb
Host smart-0ea1d875-ad9a-4b66-827f-7f7c89fb206a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573994414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3573994414
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.148914080
Short name T655
Test name
Test status
Simulation time 166365912229 ps
CPU time 188.8 seconds
Started Mar 12 12:36:53 PM PDT 24
Finished Mar 12 12:40:02 PM PDT 24
Peak memory 201860 kb
Host smart-694dda25-5771-474a-9590-853ef9162f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148914080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.148914080
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4266499441
Short name T226
Test name
Test status
Simulation time 345663489676 ps
CPU time 822.75 seconds
Started Mar 12 12:36:53 PM PDT 24
Finished Mar 12 12:50:37 PM PDT 24
Peak memory 201824 kb
Host smart-ef35820c-d4cd-4d64-b3e8-30bee237363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266499441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4266499441
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3114874205
Short name T294
Test name
Test status
Simulation time 166380775267 ps
CPU time 158.57 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:39:42 PM PDT 24
Peak memory 201660 kb
Host smart-46e0a3ed-9afe-42c3-9e6f-593eb57ec4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114874205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3114874205
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1000298974
Short name T573
Test name
Test status
Simulation time 168005562599 ps
CPU time 383.08 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:43:40 PM PDT 24
Peak memory 201840 kb
Host smart-6d94ff16-3f63-42b6-9d2a-599881915cdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000298974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1000298974
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2622256735
Short name T339
Test name
Test status
Simulation time 331717324385 ps
CPU time 199.97 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:40:16 PM PDT 24
Peak memory 201772 kb
Host smart-39ba344a-d4d7-4dee-acb2-5ad3f47efb67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622256735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2622256735
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1074891392
Short name T344
Test name
Test status
Simulation time 408691685967 ps
CPU time 1027.51 seconds
Started Mar 12 12:36:54 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 201856 kb
Host smart-454275b4-b289-4452-a045-5fe92ef955e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074891392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1074891392
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.932321887
Short name T88
Test name
Test status
Simulation time 120344894545 ps
CPU time 624.12 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:47:27 PM PDT 24
Peak memory 201892 kb
Host smart-485e7c0b-1244-49bf-89a8-0fe8de75f35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932321887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.932321887
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2768469832
Short name T529
Test name
Test status
Simulation time 43525865174 ps
CPU time 95.2 seconds
Started Mar 12 12:36:56 PM PDT 24
Finished Mar 12 12:38:31 PM PDT 24
Peak memory 201652 kb
Host smart-bd3e2262-1c04-4435-8c95-ca6ab55decac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768469832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2768469832
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2616855333
Short name T523
Test name
Test status
Simulation time 3093525277 ps
CPU time 3.04 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:37:00 PM PDT 24
Peak memory 201580 kb
Host smart-c7e9b6cf-e9c7-4310-87dd-f01212eaf4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616855333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2616855333
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.372896183
Short name T373
Test name
Test status
Simulation time 5690591789 ps
CPU time 14.07 seconds
Started Mar 12 12:37:02 PM PDT 24
Finished Mar 12 12:37:16 PM PDT 24
Peak memory 201644 kb
Host smart-f79580e7-6a02-4e29-b227-0e935a40fdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372896183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.372896183
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2568774834
Short name T91
Test name
Test status
Simulation time 58432840449 ps
CPU time 35.62 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:37:31 PM PDT 24
Peak memory 201832 kb
Host smart-342fc075-c10b-4853-ad8b-2cccf4dddbac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568774834 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2568774834
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1667549207
Short name T649
Test name
Test status
Simulation time 489237494 ps
CPU time 0.76 seconds
Started Mar 12 12:36:58 PM PDT 24
Finished Mar 12 12:37:00 PM PDT 24
Peak memory 201740 kb
Host smart-c5c68534-67b3-4c08-a42d-ac7938513922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667549207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1667549207
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3609333671
Short name T706
Test name
Test status
Simulation time 514134758622 ps
CPU time 106.12 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:39:03 PM PDT 24
Peak memory 201780 kb
Host smart-92f92d15-2c07-4c06-b1c1-0867714c0df0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609333671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3609333671
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3241301334
Short name T222
Test name
Test status
Simulation time 489439711578 ps
CPU time 613.01 seconds
Started Mar 12 12:36:56 PM PDT 24
Finished Mar 12 12:47:10 PM PDT 24
Peak memory 201912 kb
Host smart-70f065f6-a729-4106-9aaa-42a83ce25e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241301334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3241301334
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.83770463
Short name T157
Test name
Test status
Simulation time 486535063539 ps
CPU time 1119.52 seconds
Started Mar 12 12:36:55 PM PDT 24
Finished Mar 12 12:55:35 PM PDT 24
Peak memory 201740 kb
Host smart-0589bcd5-7045-4045-840f-af1620adab01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=83770463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt
_fixed.83770463
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2191244696
Short name T176
Test name
Test status
Simulation time 486177786155 ps
CPU time 282.75 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:41:40 PM PDT 24
Peak memory 201728 kb
Host smart-07282cc4-0f91-4c8d-86d1-ec006af65af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191244696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2191244696
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1923744710
Short name T675
Test name
Test status
Simulation time 167525524319 ps
CPU time 389.49 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:43:27 PM PDT 24
Peak memory 201848 kb
Host smart-2fd3bae3-9e3c-4c63-8ff9-af61acc7587a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923744710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1923744710
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1197922950
Short name T626
Test name
Test status
Simulation time 202850853561 ps
CPU time 101.56 seconds
Started Mar 12 12:36:59 PM PDT 24
Finished Mar 12 12:38:41 PM PDT 24
Peak memory 201824 kb
Host smart-7b454aef-551e-4bca-bf9f-eaf0db357b24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197922950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1197922950
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3352495801
Short name T641
Test name
Test status
Simulation time 103471953382 ps
CPU time 405.82 seconds
Started Mar 12 12:37:00 PM PDT 24
Finished Mar 12 12:43:46 PM PDT 24
Peak memory 202144 kb
Host smart-2b5ea215-78a9-49c2-9801-dfd3e25fab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352495801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3352495801
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.41760694
Short name T329
Test name
Test status
Simulation time 22597475605 ps
CPU time 36.12 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:37:34 PM PDT 24
Peak memory 201704 kb
Host smart-1207125e-8e8a-423e-a99c-7d339a4f07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41760694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.41760694
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.4227571137
Short name T786
Test name
Test status
Simulation time 4440162634 ps
CPU time 6.11 seconds
Started Mar 12 12:36:56 PM PDT 24
Finished Mar 12 12:37:03 PM PDT 24
Peak memory 201664 kb
Host smart-2ba02709-4c23-4a5a-901d-f9308964d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227571137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.4227571137
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2881652419
Short name T361
Test name
Test status
Simulation time 5946348948 ps
CPU time 3.02 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:37:00 PM PDT 24
Peak memory 201544 kb
Host smart-95f5fcf9-74aa-40a5-a40d-0738b9771f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881652419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2881652419
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1378297321
Short name T168
Test name
Test status
Simulation time 734384652462 ps
CPU time 1778.84 seconds
Started Mar 12 12:37:14 PM PDT 24
Finished Mar 12 01:06:53 PM PDT 24
Peak memory 201800 kb
Host smart-11f466ea-5597-4ec9-9b3a-6a664d7dbde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378297321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1378297321
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2802407569
Short name T36
Test name
Test status
Simulation time 218314402094 ps
CPU time 221.91 seconds
Started Mar 12 12:37:00 PM PDT 24
Finished Mar 12 12:40:43 PM PDT 24
Peak memory 210396 kb
Host smart-b60dd733-2c86-4df8-9db8-1f8dc8dc667c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802407569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2802407569
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.4288674007
Short name T610
Test name
Test status
Simulation time 319005231 ps
CPU time 0.8 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:37:05 PM PDT 24
Peak memory 201708 kb
Host smart-e6d45436-e0b8-44a2-958e-e93ddd8988cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288674007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4288674007
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.826269673
Short name T196
Test name
Test status
Simulation time 325457134236 ps
CPU time 382.99 seconds
Started Mar 12 12:36:56 PM PDT 24
Finished Mar 12 12:43:19 PM PDT 24
Peak memory 201856 kb
Host smart-caff6da7-0ffa-417b-8671-784ed6bdb3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826269673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.826269673
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3119252438
Short name T77
Test name
Test status
Simulation time 500285570388 ps
CPU time 1249.77 seconds
Started Mar 12 12:36:57 PM PDT 24
Finished Mar 12 12:57:47 PM PDT 24
Peak memory 201904 kb
Host smart-ce34f740-d02d-4dcd-8f69-5258fc7e3e77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119252438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3119252438
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3296988043
Short name T205
Test name
Test status
Simulation time 336514258255 ps
CPU time 369.27 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:43:26 PM PDT 24
Peak memory 201784 kb
Host smart-da031901-3e54-4d10-aa01-ae9b90f8c1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296988043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3296988043
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.122257410
Short name T569
Test name
Test status
Simulation time 158686662062 ps
CPU time 184.85 seconds
Started Mar 12 12:37:02 PM PDT 24
Finished Mar 12 12:40:07 PM PDT 24
Peak memory 201784 kb
Host smart-35a15b14-38c7-4dfc-870c-c1c7b1226ef1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=122257410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.122257410
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1098535363
Short name T559
Test name
Test status
Simulation time 169847456448 ps
CPU time 363.78 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 201796 kb
Host smart-6ec3aa24-9a4a-44d7-b51c-776ac8f334d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098535363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1098535363
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2804789700
Short name T581
Test name
Test status
Simulation time 207125516364 ps
CPU time 125.74 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:39:10 PM PDT 24
Peak memory 201800 kb
Host smart-94a75601-f79a-4f14-ae38-ebdff79fe28c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804789700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2804789700
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3104133195
Short name T695
Test name
Test status
Simulation time 124539150665 ps
CPU time 544.52 seconds
Started Mar 12 12:37:08 PM PDT 24
Finished Mar 12 12:46:13 PM PDT 24
Peak memory 202156 kb
Host smart-53945056-801e-4eff-a4c7-5b3e40288459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104133195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3104133195
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.174057282
Short name T510
Test name
Test status
Simulation time 29653078558 ps
CPU time 37.34 seconds
Started Mar 12 12:37:09 PM PDT 24
Finished Mar 12 12:37:47 PM PDT 24
Peak memory 201608 kb
Host smart-3cfd0969-6b53-44fc-b1ec-822a818cfda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174057282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.174057282
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1250498535
Short name T403
Test name
Test status
Simulation time 4705658707 ps
CPU time 2.33 seconds
Started Mar 12 12:37:14 PM PDT 24
Finished Mar 12 12:37:17 PM PDT 24
Peak memory 201608 kb
Host smart-09a6efbb-46fd-41cf-a2da-05e2325b6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250498535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1250498535
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2519295122
Short name T392
Test name
Test status
Simulation time 6054661328 ps
CPU time 2.71 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:37:20 PM PDT 24
Peak memory 201624 kb
Host smart-7ea69b90-f1bc-448b-ae9e-e2d1d44147a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519295122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2519295122
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3233037524
Short name T193
Test name
Test status
Simulation time 22762380640 ps
CPU time 76.88 seconds
Started Mar 12 12:38:41 PM PDT 24
Finished Mar 12 12:39:59 PM PDT 24
Peak memory 210144 kb
Host smart-2f878040-8878-44b8-83d0-ab1f80b21b16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233037524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3233037524
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4196379231
Short name T62
Test name
Test status
Simulation time 359647109 ps
CPU time 1 seconds
Started Mar 12 12:38:41 PM PDT 24
Finished Mar 12 12:38:43 PM PDT 24
Peak memory 201348 kb
Host smart-d9caa7ed-60c9-46c3-a1de-8148872b03cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196379231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4196379231
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2992926902
Short name T146
Test name
Test status
Simulation time 321679969397 ps
CPU time 171.36 seconds
Started Mar 12 12:38:41 PM PDT 24
Finished Mar 12 12:41:33 PM PDT 24
Peak memory 201508 kb
Host smart-be106159-2dff-4988-8cf4-f420c79d58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992926902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2992926902
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1854728552
Short name T715
Test name
Test status
Simulation time 164452034634 ps
CPU time 391.69 seconds
Started Mar 12 12:37:06 PM PDT 24
Finished Mar 12 12:43:39 PM PDT 24
Peak memory 201700 kb
Host smart-0472764c-63f2-4786-a94b-568fcc12ef98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854728552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1854728552
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1936980525
Short name T292
Test name
Test status
Simulation time 481287515062 ps
CPU time 1079.19 seconds
Started Mar 12 12:38:42 PM PDT 24
Finished Mar 12 12:56:42 PM PDT 24
Peak memory 201644 kb
Host smart-265b2522-a779-48cf-bea7-6328a21db376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936980525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1936980525
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1756593705
Short name T434
Test name
Test status
Simulation time 493860257116 ps
CPU time 1114.37 seconds
Started Mar 12 12:37:05 PM PDT 24
Finished Mar 12 12:55:40 PM PDT 24
Peak memory 201852 kb
Host smart-7fd770ca-fb68-4a70-af79-6933b962d8e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756593705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1756593705
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2354742046
Short name T215
Test name
Test status
Simulation time 549489786978 ps
CPU time 1327.38 seconds
Started Mar 12 12:38:42 PM PDT 24
Finished Mar 12 01:00:50 PM PDT 24
Peak memory 201652 kb
Host smart-a54c24f4-f529-4afa-acb9-f27f84946982
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354742046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2354742046
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2351897183
Short name T551
Test name
Test status
Simulation time 406433525291 ps
CPU time 233.53 seconds
Started Mar 12 12:37:03 PM PDT 24
Finished Mar 12 12:40:57 PM PDT 24
Peak memory 201740 kb
Host smart-9c50ed14-af4e-4798-9fb7-4c7e57be9a32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351897183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2351897183
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2886521336
Short name T526
Test name
Test status
Simulation time 122429692511 ps
CPU time 686.38 seconds
Started Mar 12 12:38:33 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 201740 kb
Host smart-c74f39d5-ab0f-4528-9aab-1519e747f819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886521336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2886521336
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.271033345
Short name T747
Test name
Test status
Simulation time 32125292507 ps
CPU time 74.73 seconds
Started Mar 12 12:37:10 PM PDT 24
Finished Mar 12 12:38:25 PM PDT 24
Peak memory 201604 kb
Host smart-85ac09a5-fef5-4025-bc2f-7f7b5ad59582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271033345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.271033345
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4241436334
Short name T698
Test name
Test status
Simulation time 5139980117 ps
CPU time 3.51 seconds
Started Mar 12 12:37:02 PM PDT 24
Finished Mar 12 12:37:06 PM PDT 24
Peak memory 201572 kb
Host smart-9e15c6dd-1139-4b19-bda0-c43222a8f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241436334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4241436334
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4055250125
Short name T502
Test name
Test status
Simulation time 5652049040 ps
CPU time 14.4 seconds
Started Mar 12 12:37:04 PM PDT 24
Finished Mar 12 12:37:19 PM PDT 24
Peak memory 201564 kb
Host smart-b37c3e58-b139-4ecd-a11e-a99954fbf763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055250125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4055250125
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1746454921
Short name T328
Test name
Test status
Simulation time 401086844 ps
CPU time 0.8 seconds
Started Mar 12 12:37:17 PM PDT 24
Finished Mar 12 12:37:19 PM PDT 24
Peak memory 201592 kb
Host smart-1fe1b896-380a-4a50-b338-f554d2d144d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746454921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1746454921
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.1138671629
Short name T723
Test name
Test status
Simulation time 569131366036 ps
CPU time 1299.39 seconds
Started Mar 12 12:37:08 PM PDT 24
Finished Mar 12 12:58:48 PM PDT 24
Peak memory 201912 kb
Host smart-ac5ffab5-bdc6-4f20-83b4-171d984bb3a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138671629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.1138671629
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.59018928
Short name T293
Test name
Test status
Simulation time 335771199305 ps
CPU time 511.59 seconds
Started Mar 12 12:37:06 PM PDT 24
Finished Mar 12 12:45:39 PM PDT 24
Peak memory 201664 kb
Host smart-f6db1b2b-d24b-4076-a874-203d21c54568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59018928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.59018928
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.122184253
Short name T390
Test name
Test status
Simulation time 329370517521 ps
CPU time 788.33 seconds
Started Mar 12 12:37:04 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 201928 kb
Host smart-b3f47e43-f366-4928-83e8-afdab75828eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=122184253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.122184253
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.391546284
Short name T554
Test name
Test status
Simulation time 167811543162 ps
CPU time 36.08 seconds
Started Mar 12 12:37:09 PM PDT 24
Finished Mar 12 12:37:45 PM PDT 24
Peak memory 201788 kb
Host smart-539e8d95-d16e-499d-acb9-e2af7652ca90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391546284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.391546284
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3845921015
Short name T716
Test name
Test status
Simulation time 318590576841 ps
CPU time 740.61 seconds
Started Mar 12 12:37:04 PM PDT 24
Finished Mar 12 12:49:25 PM PDT 24
Peak memory 201764 kb
Host smart-a8bdf50c-1978-4af8-b38d-75866b1cbd9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845921015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3845921015
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.4134454623
Short name T6
Test name
Test status
Simulation time 171674510546 ps
CPU time 374.2 seconds
Started Mar 12 12:37:04 PM PDT 24
Finished Mar 12 12:43:19 PM PDT 24
Peak memory 201856 kb
Host smart-93479081-736d-443b-bd78-fee3dc014429
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134454623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.4134454623
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.424549376
Short name T603
Test name
Test status
Simulation time 585954560369 ps
CPU time 347.45 seconds
Started Mar 12 12:37:10 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 201776 kb
Host smart-6f93f749-2de6-4853-b97f-ba8e4bb2edc7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424549376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.424549376
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3323046739
Short name T320
Test name
Test status
Simulation time 135238612487 ps
CPU time 454.39 seconds
Started Mar 12 12:37:18 PM PDT 24
Finished Mar 12 12:44:52 PM PDT 24
Peak memory 201940 kb
Host smart-60e0c9c7-93a7-4f60-8e26-cae75ecd3bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323046739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3323046739
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.802445366
Short name T124
Test name
Test status
Simulation time 43112302942 ps
CPU time 105.89 seconds
Started Mar 12 12:37:19 PM PDT 24
Finished Mar 12 12:39:05 PM PDT 24
Peak memory 201716 kb
Host smart-69311449-7066-4917-b13c-aa613e394a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802445366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.802445366
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1792380703
Short name T453
Test name
Test status
Simulation time 3617999033 ps
CPU time 1.23 seconds
Started Mar 12 12:37:19 PM PDT 24
Finished Mar 12 12:37:20 PM PDT 24
Peak memory 201688 kb
Host smart-b83d0ba8-41ef-4498-ab0a-b9506f488c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792380703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1792380703
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4116927336
Short name T372
Test name
Test status
Simulation time 5701132315 ps
CPU time 13.73 seconds
Started Mar 12 12:38:42 PM PDT 24
Finished Mar 12 12:38:56 PM PDT 24
Peak memory 201436 kb
Host smart-a28c567e-fb4f-4d18-bb87-582a2fc3080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116927336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4116927336
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1517957799
Short name T508
Test name
Test status
Simulation time 487316779743 ps
CPU time 1912.34 seconds
Started Mar 12 12:37:22 PM PDT 24
Finished Mar 12 01:09:16 PM PDT 24
Peak memory 210396 kb
Host smart-ca727aa8-b334-48bd-9bc3-e3c3025d3b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517957799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1517957799
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.392345947
Short name T739
Test name
Test status
Simulation time 342263305 ps
CPU time 0.74 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:36:29 PM PDT 24
Peak memory 201596 kb
Host smart-e3e7fe4d-2bd9-4cd4-bd18-ba4ac6a506e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392345947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.392345947
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.795219565
Short name T719
Test name
Test status
Simulation time 166414882702 ps
CPU time 379.71 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:42:36 PM PDT 24
Peak memory 201904 kb
Host smart-3d86f0fe-c2ff-4159-b714-cc9b2a5fec73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795219565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.795219565
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1254999008
Short name T302
Test name
Test status
Simulation time 195688742692 ps
CPU time 78.39 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:37:35 PM PDT 24
Peak memory 201864 kb
Host smart-93228759-1265-4fe3-9283-d18f7a583c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254999008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1254999008
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3205346665
Short name T612
Test name
Test status
Simulation time 157887770200 ps
CPU time 251.39 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:40:38 PM PDT 24
Peak memory 201556 kb
Host smart-eea4d16b-3564-4107-ab5f-95eb7fbb4244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205346665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3205346665
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3535639980
Short name T397
Test name
Test status
Simulation time 329032086041 ps
CPU time 801.5 seconds
Started Mar 12 12:36:20 PM PDT 24
Finished Mar 12 12:49:42 PM PDT 24
Peak memory 201700 kb
Host smart-4dc11805-ca65-408e-ac91-49e5b09f8a48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535639980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3535639980
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.697477561
Short name T705
Test name
Test status
Simulation time 166594689265 ps
CPU time 98.48 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:37:55 PM PDT 24
Peak memory 201852 kb
Host smart-ab9e8824-f557-437d-8385-3bca30cf6567
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=697477561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.697477561
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2849470497
Short name T9
Test name
Test status
Simulation time 393717028957 ps
CPU time 850.32 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:50:27 PM PDT 24
Peak memory 201756 kb
Host smart-39a291fe-f41e-4121-9948-ea3a0fbb11e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849470497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2849470497
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3816640216
Short name T657
Test name
Test status
Simulation time 79339870008 ps
CPU time 254.74 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:40:31 PM PDT 24
Peak memory 202204 kb
Host smart-cd7f7bda-2b22-40a3-96d3-1cad883afae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816640216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3816640216
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.47777466
Short name T524
Test name
Test status
Simulation time 30919273369 ps
CPU time 18.53 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:36:37 PM PDT 24
Peak memory 201580 kb
Host smart-522e76fb-31d6-4c54-987d-9b4eb991cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47777466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.47777466
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4013534504
Short name T471
Test name
Test status
Simulation time 2782855447 ps
CPU time 3.97 seconds
Started Mar 12 12:38:02 PM PDT 24
Finished Mar 12 12:38:06 PM PDT 24
Peak memory 201568 kb
Host smart-bcca38d4-5e07-4e19-a52b-e95c84a50fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013534504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4013534504
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2678803685
Short name T72
Test name
Test status
Simulation time 8142998480 ps
CPU time 9.58 seconds
Started Mar 12 12:36:20 PM PDT 24
Finished Mar 12 12:36:30 PM PDT 24
Peak memory 218008 kb
Host smart-f4b717b4-5183-4645-a81e-99b3116f77b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678803685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2678803685
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.26492064
Short name T754
Test name
Test status
Simulation time 5801252230 ps
CPU time 14.87 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:36:33 PM PDT 24
Peak memory 201712 kb
Host smart-de3f7bd5-0838-43f2-a880-7ee8c65d2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26492064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.26492064
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2998102343
Short name T594
Test name
Test status
Simulation time 180299520943 ps
CPU time 170.27 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:39:08 PM PDT 24
Peak memory 201880 kb
Host smart-1e7330bd-56d8-4668-bf61-85e57b2a9d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998102343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2998102343
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.412330439
Short name T35
Test name
Test status
Simulation time 315069525492 ps
CPU time 69.33 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:37:26 PM PDT 24
Peak memory 210236 kb
Host smart-0a1d64e9-3957-4fb7-963b-fa55a3521cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412330439 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.412330439
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3845953978
Short name T735
Test name
Test status
Simulation time 342383806 ps
CPU time 1.35 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:37:28 PM PDT 24
Peak memory 201540 kb
Host smart-65f190e3-0fd9-4db8-951b-0e2590095ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845953978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3845953978
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.399753163
Short name T541
Test name
Test status
Simulation time 503289119880 ps
CPU time 195.7 seconds
Started Mar 12 12:37:18 PM PDT 24
Finished Mar 12 12:40:34 PM PDT 24
Peak memory 201872 kb
Host smart-b0a72272-268a-4296-b73e-4f4f31d60d6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399753163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.399753163
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.743479498
Short name T718
Test name
Test status
Simulation time 161812786518 ps
CPU time 357.84 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 201848 kb
Host smart-32ca3d2f-ed4b-4026-a1f8-70998608f837
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743479498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.743479498
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2780688955
Short name T132
Test name
Test status
Simulation time 328494845973 ps
CPU time 775.79 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 201864 kb
Host smart-983c5423-1a1b-416c-8472-9024cbb26223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780688955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2780688955
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2560065080
Short name T384
Test name
Test status
Simulation time 166094169280 ps
CPU time 182.29 seconds
Started Mar 12 12:37:16 PM PDT 24
Finished Mar 12 12:40:19 PM PDT 24
Peak memory 201888 kb
Host smart-2323be82-bea6-451e-bf10-7761f65e676b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560065080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2560065080
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3297057862
Short name T5
Test name
Test status
Simulation time 184405561189 ps
CPU time 407.08 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:44:08 PM PDT 24
Peak memory 201980 kb
Host smart-114c817a-e3f5-4fea-9e2a-3d62eb7a853e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297057862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3297057862
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.709110568
Short name T324
Test name
Test status
Simulation time 409272609833 ps
CPU time 1010.34 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:54:11 PM PDT 24
Peak memory 201760 kb
Host smart-5e3ccd93-ff8d-4c44-87c5-d5a34c694b6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709110568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.709110568
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.157319864
Short name T307
Test name
Test status
Simulation time 79788123178 ps
CPU time 303.88 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:42:24 PM PDT 24
Peak memory 202056 kb
Host smart-52cdb324-3bbf-4f9a-8688-1bc277c17003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157319864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.157319864
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3382061699
Short name T689
Test name
Test status
Simulation time 43944180966 ps
CPU time 26.07 seconds
Started Mar 12 12:37:17 PM PDT 24
Finished Mar 12 12:37:44 PM PDT 24
Peak memory 201640 kb
Host smart-d8e86dba-8eab-4f14-a521-0e6fe6be6fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382061699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3382061699
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3522061623
Short name T692
Test name
Test status
Simulation time 4883644968 ps
CPU time 3.35 seconds
Started Mar 12 12:37:19 PM PDT 24
Finished Mar 12 12:37:23 PM PDT 24
Peak memory 201572 kb
Host smart-469be522-c56e-434c-8d1c-9b198e580816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522061623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3522061623
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1858489043
Short name T463
Test name
Test status
Simulation time 5726621145 ps
CPU time 15.35 seconds
Started Mar 12 12:37:20 PM PDT 24
Finished Mar 12 12:37:36 PM PDT 24
Peak memory 201708 kb
Host smart-84536fdf-6484-4f07-893c-b75ed6742ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858489043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1858489043
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3067089829
Short name T393
Test name
Test status
Simulation time 175688781346 ps
CPU time 416.57 seconds
Started Mar 12 12:37:17 PM PDT 24
Finished Mar 12 12:44:14 PM PDT 24
Peak memory 201712 kb
Host smart-a84793cb-ef72-43fa-a36f-c14897f50b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067089829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3067089829
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2808314430
Short name T679
Test name
Test status
Simulation time 37638822585 ps
CPU time 70.62 seconds
Started Mar 12 12:37:18 PM PDT 24
Finished Mar 12 12:38:29 PM PDT 24
Peak memory 210524 kb
Host smart-a03fe647-5f90-427e-af0a-2131cb91d20b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808314430 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2808314430
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2389776026
Short name T368
Test name
Test status
Simulation time 421187983 ps
CPU time 0.71 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:37:28 PM PDT 24
Peak memory 201580 kb
Host smart-e6d21d3e-a878-4274-9375-927fa22f8fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389776026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2389776026
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.487603939
Short name T671
Test name
Test status
Simulation time 162991552289 ps
CPU time 394.53 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 201836 kb
Host smart-80da7b41-aa44-44d9-b104-7afed87cfefd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487603939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.487603939
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2791189292
Short name T570
Test name
Test status
Simulation time 163042279109 ps
CPU time 385.48 seconds
Started Mar 12 12:37:25 PM PDT 24
Finished Mar 12 12:43:52 PM PDT 24
Peak memory 201872 kb
Host smart-2cc25292-d6f6-4839-9fde-a8b2d8d795e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791189292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2791189292
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.853632643
Short name T790
Test name
Test status
Simulation time 493132294762 ps
CPU time 1080.78 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:55:36 PM PDT 24
Peak memory 201720 kb
Host smart-ef005a56-cf9e-4e43-8b18-9d00e2072ece
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853632643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.853632643
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.4102449038
Short name T122
Test name
Test status
Simulation time 163593330211 ps
CPU time 370.81 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:43:38 PM PDT 24
Peak memory 201952 kb
Host smart-75ce51cf-3b44-4ac6-90ff-350383740716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102449038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.4102449038
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1036096041
Short name T514
Test name
Test status
Simulation time 485361270450 ps
CPU time 1182.94 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:57:09 PM PDT 24
Peak memory 201756 kb
Host smart-e3449bdf-05d2-4d46-a6d5-eb5ce5831ead
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036096041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1036096041
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1421879535
Short name T545
Test name
Test status
Simulation time 194312185606 ps
CPU time 485.53 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:45:41 PM PDT 24
Peak memory 201780 kb
Host smart-bbe0872d-00cf-4208-a592-430617ab9d67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421879535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1421879535
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2645133203
Short name T408
Test name
Test status
Simulation time 207135784907 ps
CPU time 105.25 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:39:11 PM PDT 24
Peak memory 201824 kb
Host smart-8f4da95d-0203-4ccb-b743-e5dd2a34f5a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645133203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2645133203
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2635281848
Short name T503
Test name
Test status
Simulation time 96944420944 ps
CPU time 536.11 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:46:22 PM PDT 24
Peak memory 202184 kb
Host smart-ebff3f9c-0aad-40ea-8abd-7d7a34e9b71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635281848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2635281848
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.277357659
Short name T522
Test name
Test status
Simulation time 40333334069 ps
CPU time 23.93 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:37:52 PM PDT 24
Peak memory 201724 kb
Host smart-4c3af80e-f329-43c2-932a-e905e5eb30c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277357659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.277357659
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1489804655
Short name T789
Test name
Test status
Simulation time 3753020481 ps
CPU time 9.42 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:37:36 PM PDT 24
Peak memory 201592 kb
Host smart-71130902-64a7-493b-b239-3520698e7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489804655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1489804655
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3290449653
Short name T382
Test name
Test status
Simulation time 5629046545 ps
CPU time 4.06 seconds
Started Mar 12 12:37:34 PM PDT 24
Finished Mar 12 12:37:38 PM PDT 24
Peak memory 201600 kb
Host smart-c46b3ba6-c698-4bc8-9d99-bc3b17161811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290449653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3290449653
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3907103740
Short name T153
Test name
Test status
Simulation time 252853242297 ps
CPU time 370.94 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:43:46 PM PDT 24
Peak memory 212036 kb
Host smart-b0514d39-4a96-41fe-8300-e5be07a87704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907103740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3907103740
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3263376505
Short name T188
Test name
Test status
Simulation time 67216143126 ps
CPU time 160.82 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:40:07 PM PDT 24
Peak memory 218512 kb
Host smart-b9335f25-bde2-447b-a76f-6d333bdb93bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263376505 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3263376505
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4129464001
Short name T517
Test name
Test status
Simulation time 516553464 ps
CPU time 0.76 seconds
Started Mar 12 12:37:37 PM PDT 24
Finished Mar 12 12:37:38 PM PDT 24
Peak memory 201628 kb
Host smart-dd47ad14-afc6-4608-a735-1795fd208808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129464001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4129464001
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1870144113
Short name T278
Test name
Test status
Simulation time 176107242620 ps
CPU time 114.45 seconds
Started Mar 12 12:37:28 PM PDT 24
Finished Mar 12 12:39:23 PM PDT 24
Peak memory 201936 kb
Host smart-8e6adbea-90a4-49f2-a950-21d39e5f1998
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870144113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1870144113
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1518675215
Short name T496
Test name
Test status
Simulation time 166358997484 ps
CPU time 80.83 seconds
Started Mar 12 12:37:28 PM PDT 24
Finished Mar 12 12:38:49 PM PDT 24
Peak memory 201864 kb
Host smart-6febe26b-8c7f-4b67-b9ee-9ad9dd233c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518675215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1518675215
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1464065587
Short name T748
Test name
Test status
Simulation time 163146356743 ps
CPU time 103.2 seconds
Started Mar 12 12:37:30 PM PDT 24
Finished Mar 12 12:39:13 PM PDT 24
Peak memory 201916 kb
Host smart-a1ee4d0f-7f02-454d-b46a-4eb087f45f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464065587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1464065587
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2722467763
Short name T160
Test name
Test status
Simulation time 497607678298 ps
CPU time 592.81 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:47:19 PM PDT 24
Peak memory 201880 kb
Host smart-92a03370-72d0-4306-91cf-794c98a34f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722467763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2722467763
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.99649855
Short name T7
Test name
Test status
Simulation time 332057462321 ps
CPU time 484.2 seconds
Started Mar 12 12:37:28 PM PDT 24
Finished Mar 12 12:45:33 PM PDT 24
Peak memory 201888 kb
Host smart-97877bed-14fc-422d-a780-265fb291197a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=99649855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed
.99649855
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1792294182
Short name T38
Test name
Test status
Simulation time 550401791020 ps
CPU time 1242.54 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:58:17 PM PDT 24
Peak memory 201840 kb
Host smart-49290219-b039-425d-bfd3-85fa90076496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792294182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1792294182
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1661475083
Short name T678
Test name
Test status
Simulation time 597554606432 ps
CPU time 1240.78 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:58:08 PM PDT 24
Peak memory 201904 kb
Host smart-5da4afda-d7c4-41d2-bb95-4c200f2ddd54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661475083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1661475083
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.550898938
Short name T451
Test name
Test status
Simulation time 23399869815 ps
CPU time 55.24 seconds
Started Mar 12 12:37:29 PM PDT 24
Finished Mar 12 12:38:24 PM PDT 24
Peak memory 201696 kb
Host smart-9e69a35a-d528-4cf3-875a-dbf6770d154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550898938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.550898938
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.637066940
Short name T173
Test name
Test status
Simulation time 5116998001 ps
CPU time 7.62 seconds
Started Mar 12 12:37:27 PM PDT 24
Finished Mar 12 12:37:35 PM PDT 24
Peak memory 201540 kb
Host smart-3e45bca6-7b8a-4c31-b45f-417d84ea9d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637066940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.637066940
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.981266825
Short name T448
Test name
Test status
Simulation time 5721547752 ps
CPU time 3.81 seconds
Started Mar 12 12:37:26 PM PDT 24
Finished Mar 12 12:37:30 PM PDT 24
Peak memory 201712 kb
Host smart-f80748eb-8be5-4f57-ae60-630ddaaeacfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981266825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.981266825
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3000029906
Short name T585
Test name
Test status
Simulation time 470439573 ps
CPU time 1.13 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:37:37 PM PDT 24
Peak memory 201624 kb
Host smart-70732026-83db-41d6-bb0a-56ca1ddaa73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000029906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3000029906
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.99499416
Short name T86
Test name
Test status
Simulation time 160992190986 ps
CPU time 353.81 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:43:32 PM PDT 24
Peak memory 201732 kb
Host smart-9a3461a5-da40-4afc-a7b8-a4e03e3fc3d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99499416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gatin
g.99499416
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1297882241
Short name T355
Test name
Test status
Simulation time 322156724908 ps
CPU time 828.16 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:51:26 PM PDT 24
Peak memory 201780 kb
Host smart-2236a8d8-f622-4b9f-b6b7-f73397c5ccd9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297882241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1297882241
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3270095772
Short name T728
Test name
Test status
Simulation time 494975360672 ps
CPU time 1180.49 seconds
Started Mar 12 12:37:42 PM PDT 24
Finished Mar 12 12:57:23 PM PDT 24
Peak memory 201936 kb
Host smart-383c21de-0f7c-4c51-b514-187acb42e729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270095772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3270095772
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2060789779
Short name T773
Test name
Test status
Simulation time 324023453797 ps
CPU time 170.36 seconds
Started Mar 12 12:37:36 PM PDT 24
Finished Mar 12 12:40:27 PM PDT 24
Peak memory 201864 kb
Host smart-0017a93c-e72c-4fa9-8021-0653391d4326
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060789779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2060789779
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3839939501
Short name T470
Test name
Test status
Simulation time 592836597884 ps
CPU time 1262.56 seconds
Started Mar 12 12:37:39 PM PDT 24
Finished Mar 12 12:58:42 PM PDT 24
Peak memory 201848 kb
Host smart-a88fabb5-0f38-47cd-9ff5-083af6f5ed95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839939501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3839939501
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3789440538
Short name T547
Test name
Test status
Simulation time 42396573605 ps
CPU time 98.6 seconds
Started Mar 12 12:37:37 PM PDT 24
Finished Mar 12 12:39:16 PM PDT 24
Peak memory 201588 kb
Host smart-0cea2064-3721-4c76-b414-a0b467893265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789440538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3789440538
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1895110635
Short name T538
Test name
Test status
Simulation time 4630860010 ps
CPU time 11.95 seconds
Started Mar 12 12:37:41 PM PDT 24
Finished Mar 12 12:37:53 PM PDT 24
Peak memory 201696 kb
Host smart-45599cb8-88ef-4159-8292-d4713bae534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895110635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1895110635
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4244111422
Short name T673
Test name
Test status
Simulation time 5689065093 ps
CPU time 4.47 seconds
Started Mar 12 12:37:41 PM PDT 24
Finished Mar 12 12:37:46 PM PDT 24
Peak memory 201708 kb
Host smart-d1a310cd-e687-4f31-80d9-fc2652a7c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244111422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4244111422
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1056387928
Short name T454
Test name
Test status
Simulation time 481011885 ps
CPU time 1.73 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:37:58 PM PDT 24
Peak memory 201588 kb
Host smart-2df8e23d-dc02-443b-8a47-64f8f0e5ea70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056387928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1056387928
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2883947145
Short name T772
Test name
Test status
Simulation time 507471579453 ps
CPU time 413.64 seconds
Started Mar 12 12:37:35 PM PDT 24
Finished Mar 12 12:44:29 PM PDT 24
Peak memory 201932 kb
Host smart-a534321e-5e4f-4b8e-b304-61634dbaa15f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883947145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2883947145
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.543458440
Short name T296
Test name
Test status
Simulation time 511411188618 ps
CPU time 322.79 seconds
Started Mar 12 12:37:44 PM PDT 24
Finished Mar 12 12:43:07 PM PDT 24
Peak memory 201872 kb
Host smart-988e80a1-964e-4431-9a93-96112fbb4170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543458440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.543458440
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2775840910
Short name T780
Test name
Test status
Simulation time 478670397858 ps
CPU time 1100.34 seconds
Started Mar 12 12:37:37 PM PDT 24
Finished Mar 12 12:55:58 PM PDT 24
Peak memory 201944 kb
Host smart-3375e0ce-a807-4471-b9fc-f5c21e911333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775840910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2775840910
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2904202428
Short name T506
Test name
Test status
Simulation time 498640122746 ps
CPU time 283.48 seconds
Started Mar 12 12:37:42 PM PDT 24
Finished Mar 12 12:42:25 PM PDT 24
Peak memory 201924 kb
Host smart-4973b961-0919-4b0f-9c19-4dd03cbac269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904202428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2904202428
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2260040111
Short name T148
Test name
Test status
Simulation time 494612304732 ps
CPU time 277.82 seconds
Started Mar 12 12:37:36 PM PDT 24
Finished Mar 12 12:42:14 PM PDT 24
Peak memory 201752 kb
Host smart-c94d4268-d2ca-48cd-afca-3631720f6cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260040111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2260040111
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2075946406
Short name T560
Test name
Test status
Simulation time 159429460049 ps
CPU time 102.61 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:39:21 PM PDT 24
Peak memory 201900 kb
Host smart-ee54ced7-e642-4b47-8197-f5b36d9ffffd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075946406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2075946406
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2007853
Short name T281
Test name
Test status
Simulation time 358391383558 ps
CPU time 218.2 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:41:16 PM PDT 24
Peak memory 201872 kb
Host smart-e64cbf1c-edfa-49e5-8fc9-ed3edb342ac1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wa
keup.2007853
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3438493098
Short name T643
Test name
Test status
Simulation time 201496375195 ps
CPU time 243.21 seconds
Started Mar 12 12:37:42 PM PDT 24
Finished Mar 12 12:41:46 PM PDT 24
Peak memory 201744 kb
Host smart-cf25f7c9-4b2a-4be5-be41-25d30b6f0ba4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438493098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3438493098
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2620079114
Short name T498
Test name
Test status
Simulation time 93666324026 ps
CPU time 459.99 seconds
Started Mar 12 12:37:36 PM PDT 24
Finished Mar 12 12:45:16 PM PDT 24
Peak memory 202204 kb
Host smart-1031f2f3-7b2e-4d7d-9f6c-cf7460c35c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620079114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2620079114
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.133597566
Short name T169
Test name
Test status
Simulation time 31372151398 ps
CPU time 20.72 seconds
Started Mar 12 12:37:39 PM PDT 24
Finished Mar 12 12:38:00 PM PDT 24
Peak memory 201680 kb
Host smart-7ee01bd9-cd95-4ce2-9582-71e0925439b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133597566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.133597566
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.371200823
Short name T598
Test name
Test status
Simulation time 4849605795 ps
CPU time 4.15 seconds
Started Mar 12 12:37:42 PM PDT 24
Finished Mar 12 12:37:47 PM PDT 24
Peak memory 201684 kb
Host smart-dcc49725-4cbd-4b98-8a5e-cc5f9c0f8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371200823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.371200823
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2497042150
Short name T488
Test name
Test status
Simulation time 5931671950 ps
CPU time 14.28 seconds
Started Mar 12 12:37:38 PM PDT 24
Finished Mar 12 12:37:52 PM PDT 24
Peak memory 201620 kb
Host smart-200daee2-5b08-4725-9399-da9b428c60c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497042150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2497042150
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.365055861
Short name T301
Test name
Test status
Simulation time 447625243711 ps
CPU time 72.66 seconds
Started Mar 12 12:37:47 PM PDT 24
Finished Mar 12 12:39:00 PM PDT 24
Peak memory 201856 kb
Host smart-ca8a7a4f-e9eb-497e-a6c6-cb5f4392a043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365055861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
365055861
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.770645079
Short name T15
Test name
Test status
Simulation time 109574034120 ps
CPU time 118.26 seconds
Started Mar 12 12:37:47 PM PDT 24
Finished Mar 12 12:39:45 PM PDT 24
Peak memory 201932 kb
Host smart-b357edcf-e680-43d6-a1b7-f12e87cae314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770645079 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.770645079
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2566875303
Short name T25
Test name
Test status
Simulation time 462558238 ps
CPU time 0.85 seconds
Started Mar 12 12:37:54 PM PDT 24
Finished Mar 12 12:37:55 PM PDT 24
Peak memory 201724 kb
Host smart-0eb2224b-fc31-4090-9fd3-22c3c1a59465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566875303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2566875303
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3635735995
Short name T597
Test name
Test status
Simulation time 369047459061 ps
CPU time 433.31 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:45:10 PM PDT 24
Peak memory 201812 kb
Host smart-eaa83c55-2dab-45bf-892a-0e695bd26cd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635735995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3635735995
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.353743593
Short name T187
Test name
Test status
Simulation time 485891733523 ps
CPU time 586.33 seconds
Started Mar 12 12:37:48 PM PDT 24
Finished Mar 12 12:47:34 PM PDT 24
Peak memory 201952 kb
Host smart-56183a09-b9bc-4d9a-a7ae-d135a338bd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353743593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.353743593
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.556472225
Short name T777
Test name
Test status
Simulation time 335362856859 ps
CPU time 747.79 seconds
Started Mar 12 12:37:47 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 201936 kb
Host smart-43b09ec7-eca1-4b83-9c36-775118c6d543
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=556472225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrup
t_fixed.556472225
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3674549065
Short name T133
Test name
Test status
Simulation time 162378398566 ps
CPU time 367.58 seconds
Started Mar 12 12:37:46 PM PDT 24
Finished Mar 12 12:43:54 PM PDT 24
Peak memory 201760 kb
Host smart-c6b39c07-54d2-4bdc-ac4a-02d2d2db3a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674549065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3674549065
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1880791980
Short name T579
Test name
Test status
Simulation time 156409943587 ps
CPU time 401.57 seconds
Started Mar 12 12:37:57 PM PDT 24
Finished Mar 12 12:44:38 PM PDT 24
Peak memory 201724 kb
Host smart-2108ba04-d6c0-49d5-b652-5c9bcf65b7dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880791980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1880791980
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1691024028
Short name T580
Test name
Test status
Simulation time 386607655174 ps
CPU time 926.9 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:53:24 PM PDT 24
Peak memory 201748 kb
Host smart-4c9988f3-e700-4206-a82b-225b51099de4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691024028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1691024028
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2667955589
Short name T437
Test name
Test status
Simulation time 574999595295 ps
CPU time 1287.04 seconds
Started Mar 12 12:37:54 PM PDT 24
Finished Mar 12 12:59:21 PM PDT 24
Peak memory 201772 kb
Host smart-667cf9a9-c622-42f9-9889-a011c3db4f74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667955589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2667955589
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2228795214
Short name T767
Test name
Test status
Simulation time 86987485115 ps
CPU time 396.05 seconds
Started Mar 12 12:37:57 PM PDT 24
Finished Mar 12 12:44:33 PM PDT 24
Peak memory 201976 kb
Host smart-bb991eb0-3a90-461c-a472-cd3c89a1423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228795214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2228795214
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.931587314
Short name T376
Test name
Test status
Simulation time 31551768537 ps
CPU time 18.44 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:38:15 PM PDT 24
Peak memory 201564 kb
Host smart-3daebc56-bc60-4d3a-839e-d99824dc94c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931587314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.931587314
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.850083903
Short name T370
Test name
Test status
Simulation time 3960029503 ps
CPU time 9.12 seconds
Started Mar 12 12:37:58 PM PDT 24
Finished Mar 12 12:38:07 PM PDT 24
Peak memory 201564 kb
Host smart-8ddf2dab-e335-446e-a136-67986c96c992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850083903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.850083903
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3494906983
Short name T345
Test name
Test status
Simulation time 5986696476 ps
CPU time 7.95 seconds
Started Mar 12 12:37:54 PM PDT 24
Finished Mar 12 12:38:02 PM PDT 24
Peak memory 201708 kb
Host smart-4d9f031f-79d4-46bf-8bc6-d9c78fa804f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494906983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3494906983
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4158157042
Short name T744
Test name
Test status
Simulation time 383894635450 ps
CPU time 223.98 seconds
Started Mar 12 12:37:47 PM PDT 24
Finished Mar 12 12:41:31 PM PDT 24
Peak memory 201752 kb
Host smart-78584e85-c96e-4d38-b586-c5367e0e382e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158157042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4158157042
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1939483487
Short name T21
Test name
Test status
Simulation time 81565064683 ps
CPU time 145.57 seconds
Started Mar 12 12:37:52 PM PDT 24
Finished Mar 12 12:40:18 PM PDT 24
Peak memory 210412 kb
Host smart-9ed64d05-9fc0-4ebb-9f94-652883ec433f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939483487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1939483487
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3006514610
Short name T378
Test name
Test status
Simulation time 563553825 ps
CPU time 0.74 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:38:07 PM PDT 24
Peak memory 201640 kb
Host smart-47ee4b72-3c0b-440b-93e2-54c7b8cb6874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006514610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3006514610
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.931507480
Short name T583
Test name
Test status
Simulation time 357577793033 ps
CPU time 452.56 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:45:39 PM PDT 24
Peak memory 201792 kb
Host smart-2fdbbed0-5cea-4933-b078-0bd5100ad76e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931507480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.931507480
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.494879416
Short name T198
Test name
Test status
Simulation time 331138628025 ps
CPU time 64.69 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:39:12 PM PDT 24
Peak memory 201812 kb
Host smart-c06e76d9-5aec-4ced-9113-ace975883f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494879416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.494879416
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2552718089
Short name T768
Test name
Test status
Simulation time 161388147710 ps
CPU time 74.37 seconds
Started Mar 12 12:37:57 PM PDT 24
Finished Mar 12 12:39:12 PM PDT 24
Peak memory 201812 kb
Host smart-9d45a8db-fce0-4dcb-970a-d3c3dcba7ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552718089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2552718089
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.4283852656
Short name T697
Test name
Test status
Simulation time 165789388247 ps
CPU time 94.02 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:39:40 PM PDT 24
Peak memory 201784 kb
Host smart-1d91137a-6892-405f-b87b-5e9d01451626
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283852656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.4283852656
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2605376322
Short name T254
Test name
Test status
Simulation time 488408648477 ps
CPU time 1109.59 seconds
Started Mar 12 12:37:46 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 201944 kb
Host smart-c6f5771f-f20a-4f6d-87a7-76d63df1bbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605376322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2605376322
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4078075969
Short name T367
Test name
Test status
Simulation time 327718311451 ps
CPU time 752.84 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 201728 kb
Host smart-1b2589bd-0907-411c-849f-2148a639de73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078075969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4078075969
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2978302914
Short name T445
Test name
Test status
Simulation time 604501478581 ps
CPU time 684.08 seconds
Started Mar 12 12:37:57 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 201772 kb
Host smart-0f13401a-daa1-42e6-9b26-5dcc68ae4dfa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978302914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2978302914
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3446397173
Short name T312
Test name
Test status
Simulation time 74672842410 ps
CPU time 253.6 seconds
Started Mar 12 12:37:57 PM PDT 24
Finished Mar 12 12:42:11 PM PDT 24
Peak memory 202116 kb
Host smart-d39fcf02-d651-4df7-900e-7a79c4097ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446397173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3446397173
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.4125553012
Short name T409
Test name
Test status
Simulation time 28825373035 ps
CPU time 66.71 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:39:14 PM PDT 24
Peak memory 201552 kb
Host smart-520de740-a639-4bf9-9cdd-f3f134180c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125553012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.4125553012
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.184693835
Short name T757
Test name
Test status
Simulation time 3925432482 ps
CPU time 8.96 seconds
Started Mar 12 12:37:55 PM PDT 24
Finished Mar 12 12:38:04 PM PDT 24
Peak memory 201616 kb
Host smart-a73fdb47-7c9a-4434-8345-b6df85d15153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184693835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.184693835
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1941643313
Short name T752
Test name
Test status
Simulation time 5764011928 ps
CPU time 13.93 seconds
Started Mar 12 12:37:47 PM PDT 24
Finished Mar 12 12:38:01 PM PDT 24
Peak memory 201708 kb
Host smart-ea6aaf6f-7aac-4829-9af8-fa5413840661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941643313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1941643313
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3665522133
Short name T267
Test name
Test status
Simulation time 186540248795 ps
CPU time 238.44 seconds
Started Mar 12 12:37:55 PM PDT 24
Finished Mar 12 12:41:54 PM PDT 24
Peak memory 210608 kb
Host smart-cd2c82a1-3996-4499-a187-d5d5a212e36d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665522133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3665522133
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2914817321
Short name T340
Test name
Test status
Simulation time 403393739 ps
CPU time 0.79 seconds
Started Mar 12 12:38:17 PM PDT 24
Finished Mar 12 12:38:18 PM PDT 24
Peak memory 201620 kb
Host smart-eb5eb271-3bdb-4e27-96e2-4ea1038ee510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914817321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2914817321
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3288558769
Short name T234
Test name
Test status
Simulation time 531515846865 ps
CPU time 865.36 seconds
Started Mar 12 12:38:07 PM PDT 24
Finished Mar 12 12:52:33 PM PDT 24
Peak memory 201864 kb
Host smart-e915b5b9-69cc-4ad1-aede-18d890c15445
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288558769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3288558769
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3394553668
Short name T276
Test name
Test status
Simulation time 579566347592 ps
CPU time 1349.08 seconds
Started Mar 12 12:38:05 PM PDT 24
Finished Mar 12 01:00:34 PM PDT 24
Peak memory 201816 kb
Host smart-b7e9f7d2-0d00-4013-9941-bf85873f693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394553668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3394553668
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1485169139
Short name T290
Test name
Test status
Simulation time 165764473520 ps
CPU time 197.93 seconds
Started Mar 12 12:38:05 PM PDT 24
Finished Mar 12 12:41:23 PM PDT 24
Peak memory 201944 kb
Host smart-172c6bc5-c76a-48eb-8449-56f72d72d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485169139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1485169139
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2994930338
Short name T371
Test name
Test status
Simulation time 486753934776 ps
CPU time 1172.44 seconds
Started Mar 12 12:38:08 PM PDT 24
Finished Mar 12 12:57:42 PM PDT 24
Peak memory 201800 kb
Host smart-06de38d4-38af-4942-8cc9-49cf18ba257a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994930338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2994930338
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.4145990184
Short name T247
Test name
Test status
Simulation time 490181714723 ps
CPU time 96.17 seconds
Started Mar 12 12:38:05 PM PDT 24
Finished Mar 12 12:39:42 PM PDT 24
Peak memory 201736 kb
Host smart-fa74d833-3a03-4cbe-8692-3bfe49a69770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145990184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.4145990184
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4003191119
Short name T590
Test name
Test status
Simulation time 338454052264 ps
CPU time 46.86 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:38:43 PM PDT 24
Peak memory 201712 kb
Host smart-90ecf53d-59fd-4724-bd14-6a8463a837a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003191119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4003191119
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1901770500
Short name T192
Test name
Test status
Simulation time 186563426157 ps
CPU time 455.53 seconds
Started Mar 12 12:38:07 PM PDT 24
Finished Mar 12 12:45:43 PM PDT 24
Peak memory 201864 kb
Host smart-e8acff94-f25d-475f-8e3e-b0a38ac44747
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901770500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1901770500
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1352000156
Short name T366
Test name
Test status
Simulation time 193977692034 ps
CPU time 451.22 seconds
Started Mar 12 12:38:05 PM PDT 24
Finished Mar 12 12:45:37 PM PDT 24
Peak memory 201760 kb
Host smart-9c9c09ba-49a5-4a3b-8f1e-decffa1cc3ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352000156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1352000156
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.979705475
Short name T576
Test name
Test status
Simulation time 34693857878 ps
CPU time 78.94 seconds
Started Mar 12 12:38:06 PM PDT 24
Finished Mar 12 12:39:25 PM PDT 24
Peak memory 201736 kb
Host smart-ab2596de-0a34-42f6-953d-029fc0a91782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979705475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.979705475
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3860346862
Short name T763
Test name
Test status
Simulation time 4510669101 ps
CPU time 11.48 seconds
Started Mar 12 12:38:05 PM PDT 24
Finished Mar 12 12:38:17 PM PDT 24
Peak memory 201688 kb
Host smart-4cf28863-6cff-4e0c-9c7c-21a2d16ec708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860346862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3860346862
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3157659918
Short name T89
Test name
Test status
Simulation time 5791258852 ps
CPU time 3.69 seconds
Started Mar 12 12:37:56 PM PDT 24
Finished Mar 12 12:38:00 PM PDT 24
Peak memory 201560 kb
Host smart-ac27e86f-c1c7-4db6-968c-9062a3d73cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157659918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3157659918
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1829362518
Short name T574
Test name
Test status
Simulation time 165342019357 ps
CPU time 377.1 seconds
Started Mar 12 12:38:17 PM PDT 24
Finished Mar 12 12:44:35 PM PDT 24
Peak memory 201708 kb
Host smart-143f6d7b-b6e6-494a-ba0e-e74d12570ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829362518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1829362518
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3386620399
Short name T84
Test name
Test status
Simulation time 79362120442 ps
CPU time 199.07 seconds
Started Mar 12 12:38:15 PM PDT 24
Finished Mar 12 12:41:35 PM PDT 24
Peak memory 210520 kb
Host smart-ab79e053-2d1e-4867-9dfe-7987c4346b1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386620399 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3386620399
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1508404813
Short name T446
Test name
Test status
Simulation time 486924208 ps
CPU time 0.89 seconds
Started Mar 12 12:38:25 PM PDT 24
Finished Mar 12 12:38:26 PM PDT 24
Peak memory 201724 kb
Host smart-e9fc46ab-3b98-49c3-9b14-44359f6df14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508404813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1508404813
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3464723088
Short name T164
Test name
Test status
Simulation time 162754453427 ps
CPU time 347.61 seconds
Started Mar 12 12:38:16 PM PDT 24
Finished Mar 12 12:44:04 PM PDT 24
Peak memory 201692 kb
Host smart-a61b4e01-48ab-4d59-8f98-73de62c033ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464723088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3464723088
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.535896106
Short name T90
Test name
Test status
Simulation time 501561710487 ps
CPU time 1083.83 seconds
Started Mar 12 12:38:15 PM PDT 24
Finished Mar 12 12:56:19 PM PDT 24
Peak memory 201724 kb
Host smart-88e3d0e1-5135-4432-a1e6-258692ce9437
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=535896106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.535896106
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3119655405
Short name T432
Test name
Test status
Simulation time 485830155139 ps
CPU time 288.26 seconds
Started Mar 12 12:38:16 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 201852 kb
Host smart-25e17380-4755-44b2-bc54-f4affdb55963
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119655405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3119655405
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2543245694
Short name T618
Test name
Test status
Simulation time 198487547604 ps
CPU time 240.06 seconds
Started Mar 12 12:38:15 PM PDT 24
Finished Mar 12 12:42:16 PM PDT 24
Peak memory 201804 kb
Host smart-ef2edb47-72ee-4230-8844-c8942846b7ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543245694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2543245694
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2235412930
Short name T686
Test name
Test status
Simulation time 197812870625 ps
CPU time 451.89 seconds
Started Mar 12 12:38:15 PM PDT 24
Finished Mar 12 12:45:47 PM PDT 24
Peak memory 201948 kb
Host smart-48119831-332e-4dad-bf96-24cbeb1493d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235412930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2235412930
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.279034442
Short name T539
Test name
Test status
Simulation time 90995753418 ps
CPU time 460.13 seconds
Started Mar 12 12:38:16 PM PDT 24
Finished Mar 12 12:45:56 PM PDT 24
Peak memory 202064 kb
Host smart-4bc2ac57-811e-4f4c-8a45-cf5587b3d9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279034442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.279034442
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.804358044
Short name T135
Test name
Test status
Simulation time 32248851378 ps
CPU time 80.65 seconds
Started Mar 12 12:38:17 PM PDT 24
Finished Mar 12 12:39:38 PM PDT 24
Peak memory 201624 kb
Host smart-eabcc4a7-e8a4-4537-a599-e108e0f2efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804358044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.804358044
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3983703864
Short name T546
Test name
Test status
Simulation time 4905962889 ps
CPU time 12.83 seconds
Started Mar 12 12:38:17 PM PDT 24
Finished Mar 12 12:38:30 PM PDT 24
Peak memory 201584 kb
Host smart-fc66f99d-626f-4788-9ea8-3c4f744a9b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983703864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3983703864
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1044359739
Short name T712
Test name
Test status
Simulation time 5993043816 ps
CPU time 4.29 seconds
Started Mar 12 12:38:21 PM PDT 24
Finished Mar 12 12:38:27 PM PDT 24
Peak memory 201648 kb
Host smart-809b7ca7-41a3-49f1-9ab0-ec3d06be39b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044359739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1044359739
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1421675465
Short name T785
Test name
Test status
Simulation time 195939169714 ps
CPU time 14.26 seconds
Started Mar 12 12:38:24 PM PDT 24
Finished Mar 12 12:38:39 PM PDT 24
Peak memory 201868 kb
Host smart-a20c0f5c-5c0e-4485-9315-1df9ff95d3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421675465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1421675465
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2722146153
Short name T647
Test name
Test status
Simulation time 287370034 ps
CPU time 1.23 seconds
Started Mar 12 12:38:37 PM PDT 24
Finished Mar 12 12:38:41 PM PDT 24
Peak memory 201708 kb
Host smart-8867c67c-efc0-462b-a1b3-fbc5d28025ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722146153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2722146153
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1361023153
Short name T550
Test name
Test status
Simulation time 160429599387 ps
CPU time 39.3 seconds
Started Mar 12 12:38:28 PM PDT 24
Finished Mar 12 12:39:07 PM PDT 24
Peak memory 201916 kb
Host smart-04ff36be-ebca-4530-94cf-8acbbe4c37bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361023153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1361023153
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3016038923
Short name T236
Test name
Test status
Simulation time 165179287511 ps
CPU time 181.64 seconds
Started Mar 12 12:38:26 PM PDT 24
Finished Mar 12 12:41:28 PM PDT 24
Peak memory 201828 kb
Host smart-d469f812-66c0-4a77-9096-a5c2a7b0fbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016038923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3016038923
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2413319601
Short name T788
Test name
Test status
Simulation time 490530906727 ps
CPU time 764.1 seconds
Started Mar 12 12:38:28 PM PDT 24
Finished Mar 12 12:51:12 PM PDT 24
Peak memory 201916 kb
Host smart-ebeb1f82-3260-40e2-bb4b-da860e21d3a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413319601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2413319601
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1471856759
Short name T245
Test name
Test status
Simulation time 162077341319 ps
CPU time 198.25 seconds
Started Mar 12 12:38:27 PM PDT 24
Finished Mar 12 12:41:46 PM PDT 24
Peak memory 201912 kb
Host smart-87f45f5f-ac2c-45d7-8373-38c1d2e036f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471856759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1471856759
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.656498443
Short name T76
Test name
Test status
Simulation time 481371403832 ps
CPU time 832.48 seconds
Started Mar 12 12:38:25 PM PDT 24
Finished Mar 12 12:52:18 PM PDT 24
Peak memory 201776 kb
Host smart-058ab1c4-b81d-4d60-9583-c8d94cf91bab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=656498443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.656498443
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1692812280
Short name T144
Test name
Test status
Simulation time 381702897455 ps
CPU time 832.4 seconds
Started Mar 12 12:38:24 PM PDT 24
Finished Mar 12 12:52:16 PM PDT 24
Peak memory 201872 kb
Host smart-bca1030e-21d7-4052-bdb1-0a3713d8ac99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692812280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1692812280
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2944635764
Short name T358
Test name
Test status
Simulation time 394169298537 ps
CPU time 279.36 seconds
Started Mar 12 12:38:24 PM PDT 24
Finished Mar 12 12:43:04 PM PDT 24
Peak memory 201868 kb
Host smart-ef5a7f33-0c7b-4b2d-ae43-fcf91a64539a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944635764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2944635764
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3528159290
Short name T484
Test name
Test status
Simulation time 92509265357 ps
CPU time 532.41 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:47:28 PM PDT 24
Peak memory 202036 kb
Host smart-fed5a423-fb1b-412a-836c-4acb2c7cdce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528159290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3528159290
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2263704638
Short name T644
Test name
Test status
Simulation time 30004275089 ps
CPU time 63.46 seconds
Started Mar 12 12:38:34 PM PDT 24
Finished Mar 12 12:39:39 PM PDT 24
Peak memory 201572 kb
Host smart-a3b85e9d-44cd-43c5-a337-927293662a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263704638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2263704638
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3283749858
Short name T775
Test name
Test status
Simulation time 4558488692 ps
CPU time 3.18 seconds
Started Mar 12 12:38:34 PM PDT 24
Finished Mar 12 12:38:38 PM PDT 24
Peak memory 201584 kb
Host smart-301a307c-f3f4-4a73-8892-8bc1aee74cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283749858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3283749858
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2034984188
Short name T1
Test name
Test status
Simulation time 5921906613 ps
CPU time 4.21 seconds
Started Mar 12 12:38:24 PM PDT 24
Finished Mar 12 12:38:28 PM PDT 24
Peak memory 201608 kb
Host smart-b58c9020-82c0-4492-937a-ebe8c156cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034984188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2034984188
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2733837103
Short name T456
Test name
Test status
Simulation time 78382936334 ps
CPU time 138.66 seconds
Started Mar 12 12:38:36 PM PDT 24
Finished Mar 12 12:40:55 PM PDT 24
Peak memory 210456 kb
Host smart-9ccca8ca-1be2-47cd-b002-d00cb6e538dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733837103 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2733837103
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1968351386
Short name T600
Test name
Test status
Simulation time 507367573 ps
CPU time 1.14 seconds
Started Mar 12 12:36:25 PM PDT 24
Finished Mar 12 12:36:26 PM PDT 24
Peak memory 201600 kb
Host smart-03b40bd3-2278-4e27-a4dc-1f810dd34019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968351386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1968351386
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2769304599
Short name T180
Test name
Test status
Simulation time 509628512276 ps
CPU time 322.23 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:41:50 PM PDT 24
Peak memory 201896 kb
Host smart-2cc41efb-59ef-4b4a-9fa0-94482fe729ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769304599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2769304599
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1402930229
Short name T449
Test name
Test status
Simulation time 327163899465 ps
CPU time 185.64 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:39:36 PM PDT 24
Peak memory 201676 kb
Host smart-a927c655-40ac-4bf0-b5ce-2e4156e0fd3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402930229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1402930229
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2014056535
Short name T177
Test name
Test status
Simulation time 495070480676 ps
CPU time 121.76 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:38:28 PM PDT 24
Peak memory 201796 kb
Host smart-728100c9-742e-4183-9a48-7674c4cf1467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014056535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2014056535
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.983391537
Short name T533
Test name
Test status
Simulation time 333967036069 ps
CPU time 208.88 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:39:57 PM PDT 24
Peak memory 201776 kb
Host smart-31b90d05-8344-43d5-90c2-fcbef940440d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983391537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.983391537
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2877096998
Short name T701
Test name
Test status
Simulation time 537922603907 ps
CPU time 1132.41 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:55:19 PM PDT 24
Peak memory 201864 kb
Host smart-a175be1c-59a6-4b6e-afac-5d95364695f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877096998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2877096998
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2501845445
Short name T338
Test name
Test status
Simulation time 402983822507 ps
CPU time 265.59 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:40:54 PM PDT 24
Peak memory 201860 kb
Host smart-df506312-f50a-4d4f-b721-2df031d482f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501845445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2501845445
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2199070873
Short name T783
Test name
Test status
Simulation time 98616404740 ps
CPU time 586.8 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:46:16 PM PDT 24
Peak memory 202200 kb
Host smart-7724ee5e-3d35-48b0-92d4-3ea790ea3350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199070873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2199070873
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1718909699
Short name T362
Test name
Test status
Simulation time 46579296147 ps
CPU time 102.04 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:38:08 PM PDT 24
Peak memory 201728 kb
Host smart-9fa50d82-d879-407a-a40d-db81370a9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718909699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1718909699
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3780833810
Short name T375
Test name
Test status
Simulation time 5212140459 ps
CPU time 3.9 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:36:31 PM PDT 24
Peak memory 201544 kb
Host smart-deb2c2b0-fb46-4466-8c84-7655c46e8ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780833810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3780833810
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3255046244
Short name T71
Test name
Test status
Simulation time 8105902156 ps
CPU time 5.63 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:36:37 PM PDT 24
Peak memory 218140 kb
Host smart-cb3040df-5893-4cd2-bb17-2861e4f8cd4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255046244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3255046244
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2716473545
Short name T465
Test name
Test status
Simulation time 5910251814 ps
CPU time 1.67 seconds
Started Mar 12 12:36:25 PM PDT 24
Finished Mar 12 12:36:27 PM PDT 24
Peak memory 201608 kb
Host smart-245993bf-19ee-4d76-a777-43bb159de815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716473545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2716473545
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.4012671981
Short name T27
Test name
Test status
Simulation time 168276232214 ps
CPU time 95.08 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:38:02 PM PDT 24
Peak memory 201820 kb
Host smart-cb174b4b-a709-480b-a4dd-09a9f3ff421d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012671981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
4012671981
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2183989867
Short name T662
Test name
Test status
Simulation time 113424220240 ps
CPU time 199.87 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:39:49 PM PDT 24
Peak memory 210356 kb
Host smart-e1b3736a-2103-4643-9242-cc9148fdda8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183989867 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2183989867
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3024323935
Short name T462
Test name
Test status
Simulation time 479095745 ps
CPU time 1.73 seconds
Started Mar 12 12:38:45 PM PDT 24
Finished Mar 12 12:38:47 PM PDT 24
Peak memory 201692 kb
Host smart-8a328d11-6e6f-43ed-ae7c-1c9526c6df36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024323935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3024323935
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3804424275
Short name T582
Test name
Test status
Simulation time 492579462847 ps
CPU time 505.38 seconds
Started Mar 12 12:38:36 PM PDT 24
Finished Mar 12 12:47:03 PM PDT 24
Peak memory 201844 kb
Host smart-044036f5-4c2a-4d0f-8e93-aae9b2502d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804424275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3804424275
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.790601149
Short name T287
Test name
Test status
Simulation time 505515069613 ps
CPU time 95.78 seconds
Started Mar 12 12:38:45 PM PDT 24
Finished Mar 12 12:40:21 PM PDT 24
Peak memory 201868 kb
Host smart-2e530c9b-1826-4e65-9dd4-6e9c09a99f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790601149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.790601149
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.277947884
Short name T295
Test name
Test status
Simulation time 162178075733 ps
CPU time 95.42 seconds
Started Mar 12 12:38:36 PM PDT 24
Finished Mar 12 12:40:15 PM PDT 24
Peak memory 201824 kb
Host smart-87389435-80bb-4484-bb3f-3fd3e444829a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277947884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.277947884
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3045527354
Short name T553
Test name
Test status
Simulation time 169684643798 ps
CPU time 105.68 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:40:22 PM PDT 24
Peak memory 201804 kb
Host smart-dc848f61-16e1-49f3-a524-762f4f12e0f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045527354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3045527354
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2869788153
Short name T630
Test name
Test status
Simulation time 329781102420 ps
CPU time 179.97 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:41:36 PM PDT 24
Peak memory 201984 kb
Host smart-3862e012-5ef8-42da-ae63-1f9b4dd376a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869788153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2869788153
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2334982627
Short name T476
Test name
Test status
Simulation time 162765184263 ps
CPU time 365.58 seconds
Started Mar 12 12:38:36 PM PDT 24
Finished Mar 12 12:44:42 PM PDT 24
Peak memory 201932 kb
Host smart-20cbccf0-2c33-4691-bbea-e92e18e3bdcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334982627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2334982627
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1002439305
Short name T402
Test name
Test status
Simulation time 192445648959 ps
CPU time 113.68 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:40:30 PM PDT 24
Peak memory 201704 kb
Host smart-e6a07eca-839c-4cd7-bb8a-e2325b35fde1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002439305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1002439305
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1638781764
Short name T369
Test name
Test status
Simulation time 75824371857 ps
CPU time 321.95 seconds
Started Mar 12 12:38:49 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 202020 kb
Host smart-63241d15-e4c2-4885-89a2-fbb389d9642b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638781764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1638781764
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1413112428
Short name T736
Test name
Test status
Simulation time 36818182579 ps
CPU time 7.81 seconds
Started Mar 12 12:38:48 PM PDT 24
Finished Mar 12 12:38:56 PM PDT 24
Peak memory 201640 kb
Host smart-c1778b0f-32b4-473b-a3d0-704f0a1bffc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413112428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1413112428
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2920507716
Short name T684
Test name
Test status
Simulation time 4199639678 ps
CPU time 3.06 seconds
Started Mar 12 12:38:48 PM PDT 24
Finished Mar 12 12:38:51 PM PDT 24
Peak memory 201612 kb
Host smart-ddd37d51-60cf-4b76-9801-bc9239b32229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920507716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2920507716
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2331944422
Short name T415
Test name
Test status
Simulation time 5840832549 ps
CPU time 2.15 seconds
Started Mar 12 12:38:35 PM PDT 24
Finished Mar 12 12:38:37 PM PDT 24
Peak memory 201748 kb
Host smart-5aeb98ff-107c-4b0f-ac19-2e3e872ff5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331944422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2331944422
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.4123248429
Short name T635
Test name
Test status
Simulation time 112658610542 ps
CPU time 355.95 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:44:42 PM PDT 24
Peak memory 218356 kb
Host smart-586c65cb-d63b-4f25-8659-c922634df3f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123248429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.4123248429
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.552726339
Short name T742
Test name
Test status
Simulation time 69405384382 ps
CPU time 93.43 seconds
Started Mar 12 12:38:45 PM PDT 24
Finished Mar 12 12:40:19 PM PDT 24
Peak memory 202000 kb
Host smart-f0fdd8e0-0306-40ef-ade3-cec99680608e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552726339 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.552726339
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2173858161
Short name T769
Test name
Test status
Simulation time 482824936 ps
CPU time 1.14 seconds
Started Mar 12 12:38:48 PM PDT 24
Finished Mar 12 12:38:50 PM PDT 24
Peak memory 201636 kb
Host smart-5202e32c-0470-4174-bdd2-2401064a562f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173858161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2173858161
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.4177262042
Short name T265
Test name
Test status
Simulation time 543595150852 ps
CPU time 376.99 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:45:03 PM PDT 24
Peak memory 201796 kb
Host smart-89878fbb-0eb1-45ca-a5b2-d924f6905eda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177262042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.4177262042
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1622366328
Short name T216
Test name
Test status
Simulation time 206772927537 ps
CPU time 498.16 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:47:04 PM PDT 24
Peak memory 201852 kb
Host smart-ac80d52b-7bfe-459d-bbe9-af65b2029e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622366328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1622366328
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3135948171
Short name T206
Test name
Test status
Simulation time 495201451239 ps
CPU time 538.96 seconds
Started Mar 12 12:38:48 PM PDT 24
Finished Mar 12 12:47:47 PM PDT 24
Peak memory 201928 kb
Host smart-a3d10ff9-ca68-4bc8-a840-77f26479524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135948171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3135948171
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2846921752
Short name T653
Test name
Test status
Simulation time 488447561475 ps
CPU time 544.49 seconds
Started Mar 12 12:38:47 PM PDT 24
Finished Mar 12 12:47:51 PM PDT 24
Peak memory 201796 kb
Host smart-0396e1f7-7940-47e7-a7e1-9f6e95a2e1c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846921752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2846921752
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2462989072
Short name T274
Test name
Test status
Simulation time 491886304208 ps
CPU time 314.67 seconds
Started Mar 12 12:38:47 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 201812 kb
Host smart-08679cbc-5c90-4242-ae5e-8a1881486d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462989072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2462989072
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4042517653
Short name T490
Test name
Test status
Simulation time 485156509492 ps
CPU time 186.99 seconds
Started Mar 12 12:38:47 PM PDT 24
Finished Mar 12 12:41:54 PM PDT 24
Peak memory 201780 kb
Host smart-541e466b-d65f-4697-b75d-18364deeafb6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042517653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4042517653
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2058454270
Short name T181
Test name
Test status
Simulation time 169366732560 ps
CPU time 106.23 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:40:33 PM PDT 24
Peak memory 201936 kb
Host smart-8eb79b91-af6b-4f6f-8255-d5c21d2abf6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058454270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2058454270
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.257206180
Short name T765
Test name
Test status
Simulation time 401603866242 ps
CPU time 260.48 seconds
Started Mar 12 12:38:49 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 201716 kb
Host smart-3e1ddaa7-cf84-4c19-ba08-de4d293250cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257206180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.257206180
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.748578550
Short name T577
Test name
Test status
Simulation time 102800114694 ps
CPU time 421.64 seconds
Started Mar 12 12:38:47 PM PDT 24
Finished Mar 12 12:45:49 PM PDT 24
Peak memory 202152 kb
Host smart-17ce8b00-8050-43d5-9bc8-50632008c059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748578550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.748578550
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3019006037
Short name T321
Test name
Test status
Simulation time 39939691778 ps
CPU time 22.66 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:39:09 PM PDT 24
Peak memory 201532 kb
Host smart-362313df-09f5-457d-baa2-6fe64d60864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019006037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3019006037
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3979490970
Short name T458
Test name
Test status
Simulation time 4644535433 ps
CPU time 3.4 seconds
Started Mar 12 12:38:47 PM PDT 24
Finished Mar 12 12:38:51 PM PDT 24
Peak memory 201704 kb
Host smart-d08bdcf9-0370-4166-99bb-c5c322671d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979490970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3979490970
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3732452249
Short name T552
Test name
Test status
Simulation time 5821172338 ps
CPU time 4 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:38:50 PM PDT 24
Peak memory 201500 kb
Host smart-82229982-eec8-408e-8de9-f15936ade20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732452249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3732452249
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.232537165
Short name T636
Test name
Test status
Simulation time 367691649978 ps
CPU time 558.45 seconds
Started Mar 12 12:38:46 PM PDT 24
Finished Mar 12 12:48:05 PM PDT 24
Peak memory 202232 kb
Host smart-b63fae2e-8d06-422e-abf8-2de4450d7bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232537165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
232537165
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4253903935
Short name T326
Test name
Test status
Simulation time 365265065 ps
CPU time 0.79 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:38:58 PM PDT 24
Peak memory 201584 kb
Host smart-8b4eca7b-1bc5-4fdd-b06d-02c7b4a28137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253903935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4253903935
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3209783150
Short name T150
Test name
Test status
Simulation time 340706490536 ps
CPU time 201.22 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:42:17 PM PDT 24
Peak memory 201756 kb
Host smart-208d37b6-c77a-4602-9aed-ad2e1c9d90fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209783150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3209783150
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2978291776
Short name T379
Test name
Test status
Simulation time 164428875158 ps
CPU time 188.3 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:42:05 PM PDT 24
Peak memory 201848 kb
Host smart-a9a5e1c1-7dd5-441b-85bb-60e9acd888cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978291776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2978291776
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1865555825
Short name T298
Test name
Test status
Simulation time 167598001733 ps
CPU time 198.08 seconds
Started Mar 12 12:38:56 PM PDT 24
Finished Mar 12 12:42:14 PM PDT 24
Peak memory 201724 kb
Host smart-98b91308-d2dc-4e6a-a825-6f556c170d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865555825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1865555825
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1505943064
Short name T486
Test name
Test status
Simulation time 501278698045 ps
CPU time 1115.88 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:57:32 PM PDT 24
Peak memory 201844 kb
Host smart-0a981fb1-4c3b-48bc-b26a-8f74d6e01ab5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505943064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1505943064
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.808662021
Short name T182
Test name
Test status
Simulation time 349714560135 ps
CPU time 74.59 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:40:12 PM PDT 24
Peak memory 201888 kb
Host smart-6945d4c9-2097-4f7e-9b8b-8d44666a5d51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808662021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.808662021
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2589811347
Short name T681
Test name
Test status
Simulation time 630257312944 ps
CPU time 1286.87 seconds
Started Mar 12 12:38:56 PM PDT 24
Finished Mar 12 01:00:23 PM PDT 24
Peak memory 201776 kb
Host smart-e27be4b4-c4e3-49b2-842f-a5f2c2bdabf0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589811347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2589811347
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.516343543
Short name T561
Test name
Test status
Simulation time 116722626251 ps
CPU time 487.78 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:47:05 PM PDT 24
Peak memory 201912 kb
Host smart-abb5c161-4c68-4da0-8d30-7c601ce30f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516343543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.516343543
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1240373743
Short name T348
Test name
Test status
Simulation time 43590327360 ps
CPU time 92.39 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:40:30 PM PDT 24
Peak memory 201704 kb
Host smart-0e0cef2c-5b2f-4c7a-ab63-53db6f76ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240373743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1240373743
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.320502730
Short name T337
Test name
Test status
Simulation time 3704375084 ps
CPU time 4.76 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:39:03 PM PDT 24
Peak memory 201688 kb
Host smart-e6630488-4c70-44dd-b556-673d3e96fa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320502730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.320502730
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2977314818
Short name T731
Test name
Test status
Simulation time 5908014193 ps
CPU time 2.1 seconds
Started Mar 12 12:38:58 PM PDT 24
Finished Mar 12 12:39:01 PM PDT 24
Peak memory 201624 kb
Host smart-2e031c62-eb22-46d0-9880-47a6be79b735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977314818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2977314818
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2812753788
Short name T29
Test name
Test status
Simulation time 294565479906 ps
CPU time 447.29 seconds
Started Mar 12 12:38:57 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 202044 kb
Host smart-097c18a9-5bd2-4c6d-8c1e-1cb3b63e8d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812753788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2812753788
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1425546279
Short name T534
Test name
Test status
Simulation time 452892589 ps
CPU time 0.85 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:39:10 PM PDT 24
Peak memory 201708 kb
Host smart-33709c7e-e0c7-46a9-bd01-97fa2d016a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425546279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1425546279
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.598024231
Short name T608
Test name
Test status
Simulation time 164583541069 ps
CPU time 195.75 seconds
Started Mar 12 12:39:07 PM PDT 24
Finished Mar 12 12:42:23 PM PDT 24
Peak memory 201788 kb
Host smart-a7698066-2402-4709-b396-cd67bd5373df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598024231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.598024231
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3662945647
Short name T758
Test name
Test status
Simulation time 205558931142 ps
CPU time 253.42 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:43:23 PM PDT 24
Peak memory 201768 kb
Host smart-0c785dd6-c220-4456-bd17-257520e91c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662945647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3662945647
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.469619769
Short name T733
Test name
Test status
Simulation time 328438811708 ps
CPU time 198.23 seconds
Started Mar 12 12:39:10 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 201824 kb
Host smart-e9a540d2-6d4d-44db-a3df-30b79efc3f9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=469619769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.469619769
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2720893635
Short name T406
Test name
Test status
Simulation time 327243402706 ps
CPU time 204.41 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:42:21 PM PDT 24
Peak memory 201768 kb
Host smart-6f3b0d61-9ff7-488d-a24e-76f3cc114ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720893635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2720893635
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1436249017
Short name T611
Test name
Test status
Simulation time 494125873069 ps
CPU time 1210.77 seconds
Started Mar 12 12:39:09 PM PDT 24
Finished Mar 12 12:59:20 PM PDT 24
Peak memory 201904 kb
Host smart-abd66f29-b40d-4d0a-b8ca-eb932ec63e9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436249017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1436249017
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2202673886
Short name T628
Test name
Test status
Simulation time 177308976283 ps
CPU time 381.95 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:45:31 PM PDT 24
Peak memory 201864 kb
Host smart-65648bff-adea-4174-87f0-aa6383dce765
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202673886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2202673886
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.794336315
Short name T407
Test name
Test status
Simulation time 209273942933 ps
CPU time 95.49 seconds
Started Mar 12 12:39:07 PM PDT 24
Finished Mar 12 12:40:42 PM PDT 24
Peak memory 201800 kb
Host smart-74539077-e339-4d05-a2cc-f899e7c1f126
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794336315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.794336315
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1865616493
Short name T40
Test name
Test status
Simulation time 66834152456 ps
CPU time 419.77 seconds
Started Mar 12 12:39:10 PM PDT 24
Finished Mar 12 12:46:11 PM PDT 24
Peak memory 202084 kb
Host smart-da56d77b-8df9-482a-987a-1c741db855b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865616493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1865616493
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.304568445
Short name T399
Test name
Test status
Simulation time 39104652937 ps
CPU time 87.51 seconds
Started Mar 12 12:39:07 PM PDT 24
Finished Mar 12 12:40:35 PM PDT 24
Peak memory 201696 kb
Host smart-0ac5ad7b-8724-4c84-9711-580456dd5b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304568445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.304568445
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4050556627
Short name T753
Test name
Test status
Simulation time 3553342049 ps
CPU time 10.06 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:39:19 PM PDT 24
Peak memory 201700 kb
Host smart-1a12757c-5376-4e37-90e0-0292be212a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050556627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4050556627
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3423083275
Short name T483
Test name
Test status
Simulation time 5663627305 ps
CPU time 3.8 seconds
Started Mar 12 12:38:55 PM PDT 24
Finished Mar 12 12:39:00 PM PDT 24
Peak memory 201740 kb
Host smart-310261c8-1eb6-46cc-afdd-a5927d6d3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423083275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3423083275
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2137918402
Short name T521
Test name
Test status
Simulation time 29910230316 ps
CPU time 68.84 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:40:18 PM PDT 24
Peak memory 201668 kb
Host smart-a793ab8b-237a-4bed-9483-4982cbc2e8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137918402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2137918402
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.4023964854
Short name T504
Test name
Test status
Simulation time 18179148959 ps
CPU time 56.83 seconds
Started Mar 12 12:39:09 PM PDT 24
Finished Mar 12 12:40:06 PM PDT 24
Peak memory 210344 kb
Host smart-228ba3a8-a685-4d3d-9764-8cf312b35fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023964854 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.4023964854
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2796953360
Short name T61
Test name
Test status
Simulation time 315284007 ps
CPU time 0.8 seconds
Started Mar 12 12:39:15 PM PDT 24
Finished Mar 12 12:39:17 PM PDT 24
Peak memory 201628 kb
Host smart-95a684df-728f-4e0c-b078-80f80e24ea9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796953360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2796953360
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3743451594
Short name T208
Test name
Test status
Simulation time 330236010992 ps
CPU time 798.79 seconds
Started Mar 12 12:39:15 PM PDT 24
Finished Mar 12 12:52:34 PM PDT 24
Peak memory 201952 kb
Host smart-c7d4fe61-b2dc-4065-bac7-add8dd61fc64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743451594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3743451594
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3100391015
Short name T596
Test name
Test status
Simulation time 332142299657 ps
CPU time 131.32 seconds
Started Mar 12 12:39:15 PM PDT 24
Finished Mar 12 12:41:26 PM PDT 24
Peak memory 201712 kb
Host smart-308be225-07ff-40e5-bdd4-cc8f699bb29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100391015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3100391015
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1779658103
Short name T277
Test name
Test status
Simulation time 163368939049 ps
CPU time 361.83 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:45:11 PM PDT 24
Peak memory 201876 kb
Host smart-123158f7-7953-4b2b-a4e9-4a14a8568f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779658103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1779658103
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3373792485
Short name T721
Test name
Test status
Simulation time 167079338490 ps
CPU time 183.89 seconds
Started Mar 12 12:39:10 PM PDT 24
Finished Mar 12 12:42:15 PM PDT 24
Peak memory 201780 kb
Host smart-ddd47013-b031-4998-b0c6-9d5e6e31841a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373792485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3373792485
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2205071623
Short name T784
Test name
Test status
Simulation time 330560646364 ps
CPU time 205.78 seconds
Started Mar 12 12:39:07 PM PDT 24
Finished Mar 12 12:42:33 PM PDT 24
Peak memory 201940 kb
Host smart-db248e74-42c8-4041-8c41-8430a1e4b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205071623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2205071623
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.121124199
Short name T548
Test name
Test status
Simulation time 165239280547 ps
CPU time 407.31 seconds
Started Mar 12 12:39:08 PM PDT 24
Finished Mar 12 12:45:57 PM PDT 24
Peak memory 201872 kb
Host smart-7f7f5fd1-859d-410c-ae35-a1f43e4d623e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=121124199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.121124199
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1953481778
Short name T575
Test name
Test status
Simulation time 194983408026 ps
CPU time 230.84 seconds
Started Mar 12 12:39:10 PM PDT 24
Finished Mar 12 12:43:02 PM PDT 24
Peak memory 201752 kb
Host smart-f3ceadd2-711b-4caf-b3b3-9869c35f6dff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953481778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1953481778
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3050343773
Short name T557
Test name
Test status
Simulation time 197657828942 ps
CPU time 28.08 seconds
Started Mar 12 12:39:11 PM PDT 24
Finished Mar 12 12:39:39 PM PDT 24
Peak memory 201776 kb
Host smart-d2e52751-eb60-4986-b27d-4c4ba5558612
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050343773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3050343773
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.4147712419
Short name T341
Test name
Test status
Simulation time 82838517843 ps
CPU time 417.56 seconds
Started Mar 12 12:39:20 PM PDT 24
Finished Mar 12 12:46:18 PM PDT 24
Peak memory 202108 kb
Host smart-f6a649c3-8369-43d1-a33b-29373b35f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147712419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.4147712419
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.168356713
Short name T359
Test name
Test status
Simulation time 43999902577 ps
CPU time 25.49 seconds
Started Mar 12 12:39:15 PM PDT 24
Finished Mar 12 12:39:41 PM PDT 24
Peak memory 201584 kb
Host smart-8b5bd823-5278-4b55-9625-41131eba0eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168356713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.168356713
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.140152031
Short name T174
Test name
Test status
Simulation time 3252511315 ps
CPU time 2.75 seconds
Started Mar 12 12:39:17 PM PDT 24
Finished Mar 12 12:39:19 PM PDT 24
Peak memory 201676 kb
Host smart-72bfa5c2-055f-4005-b3cb-166aa2d659fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140152031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.140152031
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2249140859
Short name T711
Test name
Test status
Simulation time 5734837768 ps
CPU time 7.24 seconds
Started Mar 12 12:39:09 PM PDT 24
Finished Mar 12 12:39:16 PM PDT 24
Peak memory 201720 kb
Host smart-e55b7cad-064b-4e7a-b38a-474b833e3663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249140859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2249140859
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2840099337
Short name T699
Test name
Test status
Simulation time 120619279627 ps
CPU time 376 seconds
Started Mar 12 12:39:15 PM PDT 24
Finished Mar 12 12:45:32 PM PDT 24
Peak memory 202080 kb
Host smart-2466c332-bc26-4bcf-ae02-66dc8d8d5557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840099337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2840099337
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2300308273
Short name T391
Test name
Test status
Simulation time 376229416 ps
CPU time 1.42 seconds
Started Mar 12 12:39:27 PM PDT 24
Finished Mar 12 12:39:29 PM PDT 24
Peak memory 201712 kb
Host smart-46a1133a-de12-478b-b4c4-4d646a691507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300308273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2300308273
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.660506666
Short name T426
Test name
Test status
Simulation time 168796965318 ps
CPU time 128.41 seconds
Started Mar 12 12:39:27 PM PDT 24
Finished Mar 12 12:41:36 PM PDT 24
Peak memory 201728 kb
Host smart-f5331655-2e70-4e8b-9b65-c40d23b80550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660506666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.660506666
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2301187767
Short name T617
Test name
Test status
Simulation time 324636197561 ps
CPU time 391.77 seconds
Started Mar 12 12:39:16 PM PDT 24
Finished Mar 12 12:45:48 PM PDT 24
Peak memory 201876 kb
Host smart-dec6ad4a-345e-461d-ad32-5108390ca6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301187767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2301187767
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1899466035
Short name T477
Test name
Test status
Simulation time 160668128033 ps
CPU time 113.76 seconds
Started Mar 12 12:39:17 PM PDT 24
Finished Mar 12 12:41:11 PM PDT 24
Peak memory 201864 kb
Host smart-eb103919-3c40-47dd-9685-a670fd560fe3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899466035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1899466035
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.458264769
Short name T700
Test name
Test status
Simulation time 334987962243 ps
CPU time 191.43 seconds
Started Mar 12 12:39:19 PM PDT 24
Finished Mar 12 12:42:31 PM PDT 24
Peak memory 201848 kb
Host smart-ae266629-6e41-4c26-ab05-d311c09e8a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458264769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.458264769
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.416783517
Short name T564
Test name
Test status
Simulation time 329012077343 ps
CPU time 789.68 seconds
Started Mar 12 12:39:18 PM PDT 24
Finished Mar 12 12:52:27 PM PDT 24
Peak memory 201796 kb
Host smart-69b51675-212b-4e54-ac33-4ab5abc051c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=416783517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.416783517
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3795835535
Short name T184
Test name
Test status
Simulation time 351907480766 ps
CPU time 220.77 seconds
Started Mar 12 12:39:33 PM PDT 24
Finished Mar 12 12:43:16 PM PDT 24
Peak memory 201880 kb
Host smart-b4ea3e43-19f8-4724-992f-29c881dd9bc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795835535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3795835535
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2111972763
Short name T126
Test name
Test status
Simulation time 407291587114 ps
CPU time 225.32 seconds
Started Mar 12 12:39:27 PM PDT 24
Finished Mar 12 12:43:12 PM PDT 24
Peak memory 201900 kb
Host smart-d9c36bf2-31dd-4bec-b8eb-26cdf8626cca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111972763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2111972763
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1901824915
Short name T770
Test name
Test status
Simulation time 67290211905 ps
CPU time 270.09 seconds
Started Mar 12 12:39:27 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 202220 kb
Host smart-6320a5ca-a83f-45cc-9216-5e4dc9dfbbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901824915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1901824915
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1512481016
Short name T633
Test name
Test status
Simulation time 43847721947 ps
CPU time 15.66 seconds
Started Mar 12 12:39:28 PM PDT 24
Finished Mar 12 12:39:44 PM PDT 24
Peak memory 201704 kb
Host smart-34261a74-db91-4109-b379-70ae8ea292e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512481016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1512481016
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3421689625
Short name T350
Test name
Test status
Simulation time 3530993240 ps
CPU time 9.76 seconds
Started Mar 12 12:39:32 PM PDT 24
Finished Mar 12 12:39:45 PM PDT 24
Peak memory 201472 kb
Host smart-4f590bf1-babd-4352-a4bd-acc68feca205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421689625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3421689625
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2475272854
Short name T352
Test name
Test status
Simulation time 5935644044 ps
CPU time 4.08 seconds
Started Mar 12 12:39:17 PM PDT 24
Finished Mar 12 12:39:21 PM PDT 24
Peak memory 201596 kb
Host smart-83350f21-0f36-44c8-87d3-14b69505ce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475272854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2475272854
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.899607453
Short name T491
Test name
Test status
Simulation time 183716947828 ps
CPU time 103.34 seconds
Started Mar 12 12:39:29 PM PDT 24
Finished Mar 12 12:41:12 PM PDT 24
Peak memory 201888 kb
Host smart-e1919bdf-bad9-41ac-aab6-cb00b23ea685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899607453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
899607453
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3883242027
Short name T413
Test name
Test status
Simulation time 511317998 ps
CPU time 0.88 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:39:50 PM PDT 24
Peak memory 201732 kb
Host smart-40ad69d9-7d34-4bb4-a7a2-0120f50e18e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883242027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3883242027
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.141564224
Short name T540
Test name
Test status
Simulation time 166650351128 ps
CPU time 102.1 seconds
Started Mar 12 12:39:45 PM PDT 24
Finished Mar 12 12:41:27 PM PDT 24
Peak memory 201888 kb
Host smart-6ef8f9f1-5184-4aa2-b623-0eafb1536cdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141564224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.141564224
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1929431450
Short name T663
Test name
Test status
Simulation time 502890367313 ps
CPU time 600.77 seconds
Started Mar 12 12:39:44 PM PDT 24
Finished Mar 12 12:49:45 PM PDT 24
Peak memory 201868 kb
Host smart-500bce07-92e9-4411-b45a-198f2989ed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929431450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1929431450
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.357385727
Short name T201
Test name
Test status
Simulation time 491411929335 ps
CPU time 1089.02 seconds
Started Mar 12 12:39:41 PM PDT 24
Finished Mar 12 12:57:50 PM PDT 24
Peak memory 201720 kb
Host smart-e487b4f1-86f1-46b8-bc4c-917011e8fd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357385727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.357385727
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2514237993
Short name T568
Test name
Test status
Simulation time 484234355814 ps
CPU time 1121.05 seconds
Started Mar 12 12:39:44 PM PDT 24
Finished Mar 12 12:58:25 PM PDT 24
Peak memory 201924 kb
Host smart-dd964b5a-c1dd-42fe-80cc-21a54e5cb8a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514237993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2514237993
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3338971907
Short name T584
Test name
Test status
Simulation time 322656905782 ps
CPU time 192.48 seconds
Started Mar 12 12:39:28 PM PDT 24
Finished Mar 12 12:42:40 PM PDT 24
Peak memory 201880 kb
Host smart-1f6b3984-1cd1-45ed-a865-493d728e2ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338971907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3338971907
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1039531665
Short name T322
Test name
Test status
Simulation time 165865236152 ps
CPU time 259.55 seconds
Started Mar 12 12:39:38 PM PDT 24
Finished Mar 12 12:43:58 PM PDT 24
Peak memory 201864 kb
Host smart-249559fe-0d43-4beb-aebd-565495e75511
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039531665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1039531665
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4107106195
Short name T263
Test name
Test status
Simulation time 523166401216 ps
CPU time 327.24 seconds
Started Mar 12 12:39:41 PM PDT 24
Finished Mar 12 12:45:08 PM PDT 24
Peak memory 201888 kb
Host smart-2dad5631-4a61-4d2b-9e4b-dd4f0b23667a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107106195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4107106195
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.11077359
Short name T73
Test name
Test status
Simulation time 216995982450 ps
CPU time 134.49 seconds
Started Mar 12 12:39:40 PM PDT 24
Finished Mar 12 12:41:54 PM PDT 24
Peak memory 201780 kb
Host smart-732c94ab-90bf-4e98-bc9f-9c1d3c95f8fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11077359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
dc_ctrl_filters_wakeup_fixed.11077359
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3933001545
Short name T627
Test name
Test status
Simulation time 63802319085 ps
CPU time 239.03 seconds
Started Mar 12 12:39:41 PM PDT 24
Finished Mar 12 12:43:40 PM PDT 24
Peak memory 202036 kb
Host smart-71df1bce-31ce-43ae-a42a-27eb72b0fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933001545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3933001545
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2726056177
Short name T401
Test name
Test status
Simulation time 25660087176 ps
CPU time 13.14 seconds
Started Mar 12 12:39:42 PM PDT 24
Finished Mar 12 12:39:55 PM PDT 24
Peak memory 201692 kb
Host smart-4f12367f-b732-4ee2-8b81-b7461f3263a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726056177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2726056177
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2372145514
Short name T365
Test name
Test status
Simulation time 4077253917 ps
CPU time 10.54 seconds
Started Mar 12 12:39:41 PM PDT 24
Finished Mar 12 12:39:52 PM PDT 24
Peak memory 201668 kb
Host smart-abe293ee-87ae-4d48-be89-a8eff512b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372145514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2372145514
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.378002689
Short name T400
Test name
Test status
Simulation time 5737316006 ps
CPU time 13.74 seconds
Started Mar 12 12:39:26 PM PDT 24
Finished Mar 12 12:39:40 PM PDT 24
Peak memory 201516 kb
Host smart-8a74d1ba-5ef3-425d-95db-c45fb50afbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378002689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.378002689
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2862384240
Short name T730
Test name
Test status
Simulation time 294562265782 ps
CPU time 590.37 seconds
Started Mar 12 12:39:48 PM PDT 24
Finished Mar 12 12:49:39 PM PDT 24
Peak memory 201964 kb
Host smart-314e9056-db41-4cb7-8b72-73755a008411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862384240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2862384240
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3400185288
Short name T549
Test name
Test status
Simulation time 155644456801 ps
CPU time 172.52 seconds
Started Mar 12 12:39:40 PM PDT 24
Finished Mar 12 12:42:32 PM PDT 24
Peak memory 210864 kb
Host smart-b80a1a73-1866-4ae6-a8fd-515c1a92505f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400185288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3400185288
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4132967360
Short name T441
Test name
Test status
Simulation time 395025293 ps
CPU time 0.79 seconds
Started Mar 12 12:39:48 PM PDT 24
Finished Mar 12 12:39:49 PM PDT 24
Peak memory 201712 kb
Host smart-08f17552-cb77-4c0c-b4ec-ba3d05cb6d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132967360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4132967360
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1310482727
Short name T207
Test name
Test status
Simulation time 486812408140 ps
CPU time 258.13 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:44:09 PM PDT 24
Peak memory 201868 kb
Host smart-53ecc1ae-0c9a-422e-9588-9f668c156408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310482727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1310482727
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1770722549
Short name T395
Test name
Test status
Simulation time 162600495735 ps
CPU time 61.49 seconds
Started Mar 12 12:39:47 PM PDT 24
Finished Mar 12 12:40:49 PM PDT 24
Peak memory 201804 kb
Host smart-5f60b0f1-5c9a-4907-9916-a1fca449f93c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770722549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1770722549
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4118380289
Short name T12
Test name
Test status
Simulation time 327697756909 ps
CPU time 783.74 seconds
Started Mar 12 12:39:47 PM PDT 24
Finished Mar 12 12:52:51 PM PDT 24
Peak memory 201848 kb
Host smart-4fcf32f6-2afb-421e-bcf7-487973d5d32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118380289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4118380289
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.716528825
Short name T535
Test name
Test status
Simulation time 497478724789 ps
CPU time 1137.75 seconds
Started Mar 12 12:39:55 PM PDT 24
Finished Mar 12 12:58:53 PM PDT 24
Peak memory 201688 kb
Host smart-72477e3d-2273-430d-bb42-b69db6d39b97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=716528825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.716528825
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4131803652
Short name T171
Test name
Test status
Simulation time 343096765615 ps
CPU time 842.62 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:53:52 PM PDT 24
Peak memory 201860 kb
Host smart-9455efbe-7669-4f8e-8f29-26f539e92e05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131803652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4131803652
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2894440871
Short name T592
Test name
Test status
Simulation time 395004930992 ps
CPU time 442.6 seconds
Started Mar 12 12:39:47 PM PDT 24
Finished Mar 12 12:47:10 PM PDT 24
Peak memory 201852 kb
Host smart-7a6ed777-9ee9-48ed-b8de-062d0c4627ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894440871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2894440871
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3418742451
Short name T774
Test name
Test status
Simulation time 89395983949 ps
CPU time 327.1 seconds
Started Mar 12 12:39:55 PM PDT 24
Finished Mar 12 12:45:23 PM PDT 24
Peak memory 202032 kb
Host smart-8d37084f-66da-4072-8e7b-1d41dadbc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418742451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3418742451
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.978110700
Short name T665
Test name
Test status
Simulation time 43586995194 ps
CPU time 103.62 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:41:34 PM PDT 24
Peak memory 201600 kb
Host smart-82c8096c-bf49-40a9-b8b1-b80a509caf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978110700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.978110700
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.953754428
Short name T450
Test name
Test status
Simulation time 4357539052 ps
CPU time 2.94 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:39:52 PM PDT 24
Peak memory 201688 kb
Host smart-29afadf3-4005-4fe7-926b-9a5b0d009f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953754428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.953754428
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3354250702
Short name T142
Test name
Test status
Simulation time 5982202730 ps
CPU time 15.37 seconds
Started Mar 12 12:39:48 PM PDT 24
Finished Mar 12 12:40:03 PM PDT 24
Peak memory 201640 kb
Host smart-28121865-07d6-40f2-b76f-ff005c8954df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354250702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3354250702
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.327373011
Short name T500
Test name
Test status
Simulation time 280623593733 ps
CPU time 978.26 seconds
Started Mar 12 12:39:55 PM PDT 24
Finished Mar 12 12:56:14 PM PDT 24
Peak memory 212800 kb
Host smart-e50fe006-3d39-4aa9-a0df-920a5a02c72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327373011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
327373011
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.4078453448
Short name T30
Test name
Test status
Simulation time 103529840740 ps
CPU time 30.62 seconds
Started Mar 12 12:39:47 PM PDT 24
Finished Mar 12 12:40:18 PM PDT 24
Peak memory 202060 kb
Host smart-294f5b2b-7b0e-453e-a9a4-de7895d5111a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078453448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.4078453448
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2532487130
Short name T325
Test name
Test status
Simulation time 395880189 ps
CPU time 1.63 seconds
Started Mar 12 12:39:59 PM PDT 24
Finished Mar 12 12:40:01 PM PDT 24
Peak memory 201632 kb
Host smart-3490597a-0a9c-4985-b602-b61329b144b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532487130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2532487130
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3260005997
Short name T152
Test name
Test status
Simulation time 262070791938 ps
CPU time 90.73 seconds
Started Mar 12 12:40:00 PM PDT 24
Finished Mar 12 12:41:31 PM PDT 24
Peak memory 201768 kb
Host smart-141552ab-4a91-4657-bc3e-0dcfc988d85e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260005997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3260005997
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1392304069
Short name T255
Test name
Test status
Simulation time 162386011444 ps
CPU time 197.23 seconds
Started Mar 12 12:40:09 PM PDT 24
Finished Mar 12 12:43:27 PM PDT 24
Peak memory 201776 kb
Host smart-b4300789-c510-4ca3-9e95-55f224fa0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392304069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1392304069
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1116686191
Short name T607
Test name
Test status
Simulation time 329699881839 ps
CPU time 361.87 seconds
Started Mar 12 12:39:59 PM PDT 24
Finished Mar 12 12:46:01 PM PDT 24
Peak memory 201932 kb
Host smart-f8a43640-3cf4-4ccd-9548-47480b7c4d32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116686191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1116686191
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.38910117
Short name T364
Test name
Test status
Simulation time 495552811627 ps
CPU time 1230.44 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 01:00:20 PM PDT 24
Peak memory 201796 kb
Host smart-428bd911-88f9-4103-81ba-9c8048071421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38910117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.38910117
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.844765356
Short name T467
Test name
Test status
Simulation time 328137877057 ps
CPU time 198.72 seconds
Started Mar 12 12:39:49 PM PDT 24
Finished Mar 12 12:43:08 PM PDT 24
Peak memory 201872 kb
Host smart-e7c00072-9724-4d6f-a0b2-3ad61c9a8cfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=844765356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.844765356
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2116883838
Short name T645
Test name
Test status
Simulation time 176936146542 ps
CPU time 107.93 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:41:46 PM PDT 24
Peak memory 201872 kb
Host smart-2ac1a9d0-a284-4691-9dfc-76f621d915d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116883838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2116883838
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3933177440
Short name T558
Test name
Test status
Simulation time 387149523673 ps
CPU time 431.67 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:47:10 PM PDT 24
Peak memory 201844 kb
Host smart-4fd8e25d-33cd-41a3-9511-5a04fc0261b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933177440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3933177440
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.263143165
Short name T343
Test name
Test status
Simulation time 72018692526 ps
CPU time 244.29 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:44:02 PM PDT 24
Peak memory 202016 kb
Host smart-a0727482-01e1-4d9c-9afe-407f684c7cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263143165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.263143165
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.95763325
Short name T347
Test name
Test status
Simulation time 33389602008 ps
CPU time 28.04 seconds
Started Mar 12 12:39:57 PM PDT 24
Finished Mar 12 12:40:25 PM PDT 24
Peak memory 201584 kb
Host smart-4813f5ba-4112-49ae-8daf-7a0ad4b09e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95763325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.95763325
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2690034239
Short name T423
Test name
Test status
Simulation time 5135932807 ps
CPU time 3.08 seconds
Started Mar 12 12:40:08 PM PDT 24
Finished Mar 12 12:40:12 PM PDT 24
Peak memory 201596 kb
Host smart-e7944e0a-2c22-4239-8911-a70895e24110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690034239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2690034239
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1469825882
Short name T640
Test name
Test status
Simulation time 6109383284 ps
CPU time 2.45 seconds
Started Mar 12 12:39:47 PM PDT 24
Finished Mar 12 12:39:50 PM PDT 24
Peak memory 201708 kb
Host smart-5a60712c-9a1a-407c-a07d-a500a0e7fe65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469825882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1469825882
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.766727603
Short name T530
Test name
Test status
Simulation time 366283667984 ps
CPU time 180.77 seconds
Started Mar 12 12:40:09 PM PDT 24
Finished Mar 12 12:43:11 PM PDT 24
Peak memory 201828 kb
Host smart-4ef304af-a967-40ce-b03c-ddebb3c4ee19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766727603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
766727603
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3165038907
Short name T14
Test name
Test status
Simulation time 116696257120 ps
CPU time 320.36 seconds
Started Mar 12 12:40:09 PM PDT 24
Finished Mar 12 12:45:30 PM PDT 24
Peak memory 210352 kb
Host smart-355965c4-4d53-465b-8a9a-c88ec5e0cbc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165038907 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3165038907
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1690368712
Short name T342
Test name
Test status
Simulation time 499141885 ps
CPU time 1.77 seconds
Started Mar 12 12:40:09 PM PDT 24
Finished Mar 12 12:40:12 PM PDT 24
Peak memory 201720 kb
Host smart-eae2cd4a-44b3-49c2-8f54-158d9918240c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690368712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1690368712
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2823126215
Short name T507
Test name
Test status
Simulation time 162659347780 ps
CPU time 175.37 seconds
Started Mar 12 12:40:10 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 201856 kb
Host smart-43bab54b-3fdc-4c72-b81a-07a02bd2a6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823126215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2823126215
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3542392386
Short name T299
Test name
Test status
Simulation time 164894665023 ps
CPU time 361.77 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:46:00 PM PDT 24
Peak memory 201884 kb
Host smart-d5fca1e4-65e2-4f6f-80cf-17add56bfc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542392386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3542392386
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2957611647
Short name T381
Test name
Test status
Simulation time 330758993066 ps
CPU time 193.51 seconds
Started Mar 12 12:39:57 PM PDT 24
Finished Mar 12 12:43:11 PM PDT 24
Peak memory 201920 kb
Host smart-a27b95f7-c75b-4f1d-a5c3-6cc251aa7f2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957611647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2957611647
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2556668969
Short name T740
Test name
Test status
Simulation time 162636529263 ps
CPU time 98.78 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:41:37 PM PDT 24
Peak memory 201772 kb
Host smart-03be53e0-240a-41cc-9b06-c19f90ba72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556668969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2556668969
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2361451676
Short name T138
Test name
Test status
Simulation time 172006736772 ps
CPU time 45.33 seconds
Started Mar 12 12:40:10 PM PDT 24
Finished Mar 12 12:40:55 PM PDT 24
Peak memory 201776 kb
Host smart-da76b68f-6d52-42de-b2c7-fff6a0b20136
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361451676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2361451676
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1075516573
Short name T472
Test name
Test status
Simulation time 397687174843 ps
CPU time 243.94 seconds
Started Mar 12 12:40:08 PM PDT 24
Finished Mar 12 12:44:13 PM PDT 24
Peak memory 201944 kb
Host smart-2e8c9343-c23d-46d7-89be-84874d141fa1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075516573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1075516573
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4105776427
Short name T137
Test name
Test status
Simulation time 33192815914 ps
CPU time 77.14 seconds
Started Mar 12 12:40:10 PM PDT 24
Finished Mar 12 12:41:27 PM PDT 24
Peak memory 201500 kb
Host smart-81f85e5c-dbf6-4de7-b277-6b9e1f04eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105776427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4105776427
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1056400466
Short name T563
Test name
Test status
Simulation time 4931392510 ps
CPU time 6.51 seconds
Started Mar 12 12:40:09 PM PDT 24
Finished Mar 12 12:40:16 PM PDT 24
Peak memory 201732 kb
Host smart-cbc906d5-6166-48a2-836d-97fb8262b078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056400466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1056400466
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2781812828
Short name T411
Test name
Test status
Simulation time 5740464205 ps
CPU time 2.85 seconds
Started Mar 12 12:39:58 PM PDT 24
Finished Mar 12 12:40:01 PM PDT 24
Peak memory 201704 kb
Host smart-e30e025f-f522-486b-bc52-b3d8b3b58581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781812828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2781812828
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3674321413
Short name T229
Test name
Test status
Simulation time 189154361938 ps
CPU time 108.33 seconds
Started Mar 12 12:40:11 PM PDT 24
Finished Mar 12 12:41:59 PM PDT 24
Peak memory 201776 kb
Host smart-1762a944-20c5-4c37-b23b-91c62dc52f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674321413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3674321413
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3188186955
Short name T16
Test name
Test status
Simulation time 53480080359 ps
CPU time 117.97 seconds
Started Mar 12 12:40:08 PM PDT 24
Finished Mar 12 12:42:07 PM PDT 24
Peak memory 210196 kb
Host smart-a58f2acb-4461-47d1-b58b-fdaa30cf7f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188186955 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3188186955
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1876080435
Short name T421
Test name
Test status
Simulation time 304713605 ps
CPU time 1.41 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:36:33 PM PDT 24
Peak memory 201696 kb
Host smart-70b73934-daa6-43a7-a508-ebcd07e9b365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876080435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1876080435
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.937023710
Short name T275
Test name
Test status
Simulation time 399790485769 ps
CPU time 554.13 seconds
Started Mar 12 12:36:30 PM PDT 24
Finished Mar 12 12:45:44 PM PDT 24
Peak memory 201880 kb
Host smart-5f4159dd-b6d8-4fec-8e31-97f1141874a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937023710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.937023710
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2165184491
Short name T727
Test name
Test status
Simulation time 219709355040 ps
CPU time 491.29 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:44:41 PM PDT 24
Peak memory 201876 kb
Host smart-646dd3a1-c262-4de8-8f5e-1af27d683176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165184491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2165184491
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3008134627
Short name T457
Test name
Test status
Simulation time 165960154889 ps
CPU time 98.87 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:38:06 PM PDT 24
Peak memory 201704 kb
Host smart-a0939b4f-6ccd-4f53-a18e-050897762169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008134627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3008134627
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3855590406
Short name T478
Test name
Test status
Simulation time 327875967904 ps
CPU time 413.24 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:43:23 PM PDT 24
Peak memory 201716 kb
Host smart-c89e7b0d-f544-4edc-91fb-c36475af43fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855590406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3855590406
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2694215671
Short name T151
Test name
Test status
Simulation time 161039071822 ps
CPU time 206.99 seconds
Started Mar 12 12:36:30 PM PDT 24
Finished Mar 12 12:39:57 PM PDT 24
Peak memory 201676 kb
Host smart-085afa2c-810d-4346-bd85-5b1ab5b7e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694215671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2694215671
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1439843264
Short name T357
Test name
Test status
Simulation time 166381466948 ps
CPU time 188.62 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:39:37 PM PDT 24
Peak memory 201868 kb
Host smart-f748e413-751b-4363-9819-552e3696315c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439843264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1439843264
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.71524296
Short name T218
Test name
Test status
Simulation time 642219856669 ps
CPU time 1304.41 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:58:12 PM PDT 24
Peak memory 201720 kb
Host smart-ef415f55-e201-4f75-b691-14302b17247c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71524296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_wa
keup.71524296
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.549522373
Short name T732
Test name
Test status
Simulation time 612421310592 ps
CPU time 1341.42 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:58:48 PM PDT 24
Peak memory 201868 kb
Host smart-612e52ef-2dec-4d82-8ef8-07a0f3a19cb0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549522373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.549522373
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1624821172
Short name T316
Test name
Test status
Simulation time 124517501604 ps
CPU time 474.96 seconds
Started Mar 12 12:36:27 PM PDT 24
Finished Mar 12 12:44:22 PM PDT 24
Peak memory 202188 kb
Host smart-067c293b-cac2-4393-befa-08fbc72c5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624821172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1624821172
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2395269257
Short name T586
Test name
Test status
Simulation time 38751323765 ps
CPU time 41.78 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:37:11 PM PDT 24
Peak memory 201704 kb
Host smart-27e405f2-3731-4251-953b-6cc23dce7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395269257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2395269257
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.397086376
Short name T737
Test name
Test status
Simulation time 3775283002 ps
CPU time 8.07 seconds
Started Mar 12 12:36:26 PM PDT 24
Finished Mar 12 12:36:35 PM PDT 24
Peak memory 201684 kb
Host smart-3ee6dc63-9531-4253-a237-54bb76b8312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397086376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.397086376
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.484402896
Short name T54
Test name
Test status
Simulation time 3940231910 ps
CPU time 9.87 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:36:41 PM PDT 24
Peak memory 217024 kb
Host smart-2f2ae59a-0e69-416a-b34c-97945d329962
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484402896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.484402896
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.980962174
Short name T482
Test name
Test status
Simulation time 6028821876 ps
CPU time 7.33 seconds
Started Mar 12 12:36:30 PM PDT 24
Finished Mar 12 12:36:37 PM PDT 24
Peak memory 201720 kb
Host smart-5c58d498-8ce0-4768-950c-781324fc71e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980962174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.980962174
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3268706437
Short name T79
Test name
Test status
Simulation time 188109198022 ps
CPU time 471.44 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:44:20 PM PDT 24
Peak memory 201836 kb
Host smart-83487263-d764-491a-b8dc-246286284557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268706437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3268706437
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2167769777
Short name T709
Test name
Test status
Simulation time 85999534793 ps
CPU time 105.72 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:38:17 PM PDT 24
Peak memory 210196 kb
Host smart-45e9c12e-3229-4eff-bb11-a2798fe61dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167769777 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2167769777
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1323604439
Short name T682
Test name
Test status
Simulation time 463488243 ps
CPU time 0.82 seconds
Started Mar 12 12:40:16 PM PDT 24
Finished Mar 12 12:40:17 PM PDT 24
Peak memory 201548 kb
Host smart-962f2254-cc4e-40fc-b317-7d388ff03eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323604439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1323604439
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3555810508
Short name T648
Test name
Test status
Simulation time 421153253758 ps
CPU time 104.71 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:42:02 PM PDT 24
Peak memory 201876 kb
Host smart-3502ed8e-6ca0-4e55-a795-905bb8bc3473
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555810508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3555810508
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1635136577
Short name T185
Test name
Test status
Simulation time 358723409879 ps
CPU time 218.69 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:43:56 PM PDT 24
Peak memory 201792 kb
Host smart-1fc16448-1f29-4505-9221-5228242cf3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635136577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1635136577
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2995177653
Short name T149
Test name
Test status
Simulation time 490286730159 ps
CPU time 76.63 seconds
Started Mar 12 12:40:19 PM PDT 24
Finished Mar 12 12:41:36 PM PDT 24
Peak memory 201760 kb
Host smart-c63fd980-f550-427a-970a-19a4c69ec411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995177653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2995177653
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.229151725
Short name T505
Test name
Test status
Simulation time 160936028857 ps
CPU time 186.16 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:43:24 PM PDT 24
Peak memory 201836 kb
Host smart-e4b78d74-c318-4584-89e8-c4371273886e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=229151725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.229151725
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3771346884
Short name T422
Test name
Test status
Simulation time 161792879469 ps
CPU time 383.71 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:46:41 PM PDT 24
Peak memory 201884 kb
Host smart-b31d10df-17d3-4906-9c47-debb95483bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771346884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3771346884
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.130063785
Short name T81
Test name
Test status
Simulation time 169617522626 ps
CPU time 417.32 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:47:15 PM PDT 24
Peak memory 201844 kb
Host smart-fcfebf13-b055-44e1-9158-5fc87b894144
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=130063785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.130063785
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1392477077
Short name T230
Test name
Test status
Simulation time 533042000299 ps
CPU time 608.79 seconds
Started Mar 12 12:40:19 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 201784 kb
Host smart-be2a7f14-b9a2-45ca-883b-468b6b1de1d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392477077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1392477077
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.637358639
Short name T668
Test name
Test status
Simulation time 398088810599 ps
CPU time 422.92 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:47:20 PM PDT 24
Peak memory 201712 kb
Host smart-edc9feae-0aed-45b7-983a-5fff534b5d4a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637358639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.637358639
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3309620373
Short name T499
Test name
Test status
Simulation time 87901106129 ps
CPU time 281.98 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:45:00 PM PDT 24
Peak memory 202120 kb
Host smart-fcd5f076-f6e6-41ad-9c2d-4280048ee80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309620373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3309620373
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.358206346
Short name T632
Test name
Test status
Simulation time 40849532172 ps
CPU time 20.95 seconds
Started Mar 12 12:40:18 PM PDT 24
Finished Mar 12 12:40:39 PM PDT 24
Peak memory 201500 kb
Host smart-0a18c5cb-963d-4ab4-9cdd-5aa8a846a9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358206346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.358206346
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.2209114700
Short name T380
Test name
Test status
Simulation time 4155433762 ps
CPU time 10.85 seconds
Started Mar 12 12:40:18 PM PDT 24
Finished Mar 12 12:40:29 PM PDT 24
Peak memory 201612 kb
Host smart-d99c5ad6-b52d-46ed-871e-47f0ad9cb16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209114700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.2209114700
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.74225358
Short name T532
Test name
Test status
Simulation time 6090072476 ps
CPU time 15.71 seconds
Started Mar 12 12:40:17 PM PDT 24
Finished Mar 12 12:40:34 PM PDT 24
Peak memory 201612 kb
Host smart-dac3cf11-3864-4a58-a53f-4e5a4c7e11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74225358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.74225358
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1527747008
Short name T622
Test name
Test status
Simulation time 500024283 ps
CPU time 0.91 seconds
Started Mar 12 12:40:29 PM PDT 24
Finished Mar 12 12:40:30 PM PDT 24
Peak memory 201708 kb
Host smart-84aca96a-b5c2-4aa2-ad26-b6d7cf4b4c97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527747008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1527747008
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2012873695
Short name T240
Test name
Test status
Simulation time 160349326195 ps
CPU time 378.27 seconds
Started Mar 12 12:40:26 PM PDT 24
Finished Mar 12 12:46:44 PM PDT 24
Peak memory 201872 kb
Host smart-966f79b4-ee59-472b-aecd-230f93b3c751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012873695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2012873695
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.768184540
Short name T136
Test name
Test status
Simulation time 164459526769 ps
CPU time 66.63 seconds
Started Mar 12 12:40:27 PM PDT 24
Finished Mar 12 12:41:34 PM PDT 24
Peak memory 201772 kb
Host smart-b8f39690-d21a-446a-af4a-1d52f028dec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768184540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.768184540
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4175868737
Short name T518
Test name
Test status
Simulation time 325831297774 ps
CPU time 354.67 seconds
Started Mar 12 12:40:28 PM PDT 24
Finished Mar 12 12:46:23 PM PDT 24
Peak memory 201804 kb
Host smart-29fc9f13-3b26-4a93-82a0-6940919175f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175868737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4175868737
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3425659470
Short name T161
Test name
Test status
Simulation time 492698204400 ps
CPU time 191.4 seconds
Started Mar 12 12:40:18 PM PDT 24
Finished Mar 12 12:43:31 PM PDT 24
Peak memory 201868 kb
Host smart-4b7b9e3d-dfcc-4987-84d6-75473c330236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425659470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3425659470
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2748994233
Short name T410
Test name
Test status
Simulation time 334966141275 ps
CPU time 385.16 seconds
Started Mar 12 12:40:27 PM PDT 24
Finished Mar 12 12:46:52 PM PDT 24
Peak memory 201748 kb
Host smart-203dc552-c503-4f92-9bb5-f7ececf31ff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748994233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2748994233
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.436152479
Short name T26
Test name
Test status
Simulation time 361445534471 ps
CPU time 815.03 seconds
Started Mar 12 12:40:28 PM PDT 24
Finished Mar 12 12:54:03 PM PDT 24
Peak memory 201880 kb
Host smart-fcbe5074-4dab-49bb-8759-a525894041c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436152479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.436152479
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3961976004
Short name T349
Test name
Test status
Simulation time 615983261357 ps
CPU time 1302.19 seconds
Started Mar 12 12:40:27 PM PDT 24
Finished Mar 12 01:02:09 PM PDT 24
Peak memory 201880 kb
Host smart-2b2d3a58-06bd-4731-b8a2-ea8bafeae658
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961976004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3961976004
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.148045938
Short name T311
Test name
Test status
Simulation time 99161825826 ps
CPU time 318.68 seconds
Started Mar 12 12:40:28 PM PDT 24
Finished Mar 12 12:45:46 PM PDT 24
Peak memory 202172 kb
Host smart-f911ff9e-c2d9-4aea-82f1-0de592b10fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148045938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.148045938
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.652901131
Short name T473
Test name
Test status
Simulation time 26183190116 ps
CPU time 59.33 seconds
Started Mar 12 12:40:29 PM PDT 24
Finished Mar 12 12:41:29 PM PDT 24
Peak memory 201676 kb
Host smart-3ee0646b-5ca9-46b7-b57d-dc1e4bc6e38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652901131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.652901131
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.4292329088
Short name T725
Test name
Test status
Simulation time 2884048217 ps
CPU time 2.3 seconds
Started Mar 12 12:40:27 PM PDT 24
Finished Mar 12 12:40:29 PM PDT 24
Peak memory 201580 kb
Host smart-ec138f1a-e327-4abe-98ed-cdb00a4d48f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292329088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.4292329088
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4278703730
Short name T442
Test name
Test status
Simulation time 5875876612 ps
CPU time 3.11 seconds
Started Mar 12 12:40:19 PM PDT 24
Finished Mar 12 12:40:23 PM PDT 24
Peak memory 201612 kb
Host smart-6048c44b-55da-4e2d-88b4-f0f8e38c0c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278703730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4278703730
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.4238176967
Short name T764
Test name
Test status
Simulation time 117376580917 ps
CPU time 573.87 seconds
Started Mar 12 12:40:28 PM PDT 24
Finished Mar 12 12:50:02 PM PDT 24
Peak memory 202188 kb
Host smart-f39d9ae6-0556-41f1-9ff5-3f1ddca7eb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238176967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.4238176967
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2784168273
Short name T260
Test name
Test status
Simulation time 88059389142 ps
CPU time 119.61 seconds
Started Mar 12 12:40:28 PM PDT 24
Finished Mar 12 12:42:28 PM PDT 24
Peak memory 210360 kb
Host smart-edd1baf1-727f-46b2-adab-e3377a69b654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784168273 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2784168273
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1907522066
Short name T405
Test name
Test status
Simulation time 409656906 ps
CPU time 1.06 seconds
Started Mar 12 12:40:49 PM PDT 24
Finished Mar 12 12:40:50 PM PDT 24
Peak memory 201632 kb
Host smart-452d214b-f0d9-48ce-aa41-749cafe44d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907522066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1907522066
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.388488464
Short name T279
Test name
Test status
Simulation time 514929164778 ps
CPU time 435.22 seconds
Started Mar 12 12:40:40 PM PDT 24
Finished Mar 12 12:47:56 PM PDT 24
Peak memory 201752 kb
Host smart-39c3dab2-f712-43e2-8e10-3c9e63290daa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388488464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.388488464
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2838536270
Short name T489
Test name
Test status
Simulation time 166055853736 ps
CPU time 364.58 seconds
Started Mar 12 12:40:38 PM PDT 24
Finished Mar 12 12:46:43 PM PDT 24
Peak memory 201856 kb
Host smart-c7df8f8b-9e5b-4556-b0a9-345c3c643588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838536270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2838536270
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.920220645
Short name T261
Test name
Test status
Simulation time 495416378479 ps
CPU time 553.35 seconds
Started Mar 12 12:40:42 PM PDT 24
Finished Mar 12 12:49:55 PM PDT 24
Peak memory 201724 kb
Host smart-a6a70248-2017-419d-8532-eaeb1059a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920220645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.920220645
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1962287946
Short name T440
Test name
Test status
Simulation time 495802186302 ps
CPU time 1172.94 seconds
Started Mar 12 12:40:41 PM PDT 24
Finished Mar 12 01:00:14 PM PDT 24
Peak memory 201764 kb
Host smart-679fb549-6250-4e51-b871-a04d22b140e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962287946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1962287946
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4256308165
Short name T289
Test name
Test status
Simulation time 329423165978 ps
CPU time 185.24 seconds
Started Mar 12 12:40:40 PM PDT 24
Finished Mar 12 12:43:46 PM PDT 24
Peak memory 201776 kb
Host smart-12b96757-5604-4f83-8490-b582c5210023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256308165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4256308165
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1343124916
Short name T755
Test name
Test status
Simulation time 483515564056 ps
CPU time 212.47 seconds
Started Mar 12 12:40:38 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 201868 kb
Host smart-42dd53b4-4961-4417-b62d-1a27fa32fc65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343124916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1343124916
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2540841841
Short name T687
Test name
Test status
Simulation time 213650691845 ps
CPU time 110.92 seconds
Started Mar 12 12:40:38 PM PDT 24
Finished Mar 12 12:42:29 PM PDT 24
Peak memory 201968 kb
Host smart-75caa306-2d06-4793-a50c-40ec33684e34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540841841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2540841841
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3307918182
Short name T556
Test name
Test status
Simulation time 606041423161 ps
CPU time 1520.4 seconds
Started Mar 12 12:40:40 PM PDT 24
Finished Mar 12 01:06:01 PM PDT 24
Peak memory 201876 kb
Host smart-093b2414-7473-442d-b3a6-b85790363ace
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307918182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3307918182
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3243356054
Short name T544
Test name
Test status
Simulation time 120834690412 ps
CPU time 394.81 seconds
Started Mar 12 12:40:40 PM PDT 24
Finished Mar 12 12:47:15 PM PDT 24
Peak memory 202056 kb
Host smart-fd53e358-06c5-4b2b-bdfb-f729456e067a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243356054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3243356054
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.453932599
Short name T398
Test name
Test status
Simulation time 29792466098 ps
CPU time 70.02 seconds
Started Mar 12 12:40:40 PM PDT 24
Finished Mar 12 12:41:50 PM PDT 24
Peak memory 201496 kb
Host smart-1ca5c188-06ed-4f3d-b1ae-41a7d57a8477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453932599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.453932599
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3553699095
Short name T741
Test name
Test status
Simulation time 4411269914 ps
CPU time 3.16 seconds
Started Mar 12 12:40:41 PM PDT 24
Finished Mar 12 12:40:44 PM PDT 24
Peak memory 201676 kb
Host smart-c3104297-3b6d-4d34-bd9b-af66796c90ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553699095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3553699095
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.4279529545
Short name T460
Test name
Test status
Simulation time 6020934107 ps
CPU time 2.82 seconds
Started Mar 12 12:40:38 PM PDT 24
Finished Mar 12 12:40:42 PM PDT 24
Peak memory 201704 kb
Host smart-344eaa7f-f035-41c0-bbf4-a85800daead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279529545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.4279529545
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1871787569
Short name T571
Test name
Test status
Simulation time 245932688130 ps
CPU time 68.28 seconds
Started Mar 12 12:40:39 PM PDT 24
Finished Mar 12 12:41:48 PM PDT 24
Peak memory 210212 kb
Host smart-3aaaa311-66e6-40a4-9583-fb73cf41db02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871787569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1871787569
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2907967154
Short name T652
Test name
Test status
Simulation time 307125388 ps
CPU time 0.77 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:40:48 PM PDT 24
Peak memory 201608 kb
Host smart-86402316-6b23-4708-9bc3-b1d00b5aee75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907967154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2907967154
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.762317177
Short name T703
Test name
Test status
Simulation time 514704673647 ps
CPU time 834.8 seconds
Started Mar 12 12:40:52 PM PDT 24
Finished Mar 12 12:54:47 PM PDT 24
Peak memory 201800 kb
Host smart-e3a234aa-808f-4b8f-87d7-b590596b75ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762317177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.762317177
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3910658792
Short name T542
Test name
Test status
Simulation time 366441418457 ps
CPU time 422.55 seconds
Started Mar 12 12:40:52 PM PDT 24
Finished Mar 12 12:47:54 PM PDT 24
Peak memory 201796 kb
Host smart-e688b015-cd9e-4bb4-8791-eb2c4fb8afe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910658792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3910658792
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.395142702
Short name T203
Test name
Test status
Simulation time 168405232921 ps
CPU time 422.54 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:47:49 PM PDT 24
Peak memory 201748 kb
Host smart-0b22bc87-15db-4a5e-885f-0597e40c25ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395142702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.395142702
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.322002731
Short name T447
Test name
Test status
Simulation time 485676094555 ps
CPU time 527.17 seconds
Started Mar 12 12:40:49 PM PDT 24
Finished Mar 12 12:49:36 PM PDT 24
Peak memory 201872 kb
Host smart-e4b111eb-9c44-4bc9-ac6a-bfce28d0b536
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=322002731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.322002731
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3219732995
Short name T750
Test name
Test status
Simulation time 488231491757 ps
CPU time 270.15 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:45:17 PM PDT 24
Peak memory 201924 kb
Host smart-4ce5c29d-a89a-49af-8ecf-5ea01e2821da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219732995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3219732995
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2404158988
Short name T661
Test name
Test status
Simulation time 491479173891 ps
CPU time 390.79 seconds
Started Mar 12 12:40:48 PM PDT 24
Finished Mar 12 12:47:19 PM PDT 24
Peak memory 201868 kb
Host smart-bb17f660-31f6-4476-8b47-6f6c47c92fc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404158988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2404158988
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2310397816
Short name T262
Test name
Test status
Simulation time 364603561613 ps
CPU time 190.38 seconds
Started Mar 12 12:40:49 PM PDT 24
Finished Mar 12 12:43:59 PM PDT 24
Peak memory 201948 kb
Host smart-e87fedff-5c12-4f98-8020-c5c90d37f159
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310397816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2310397816
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1131350800
Short name T691
Test name
Test status
Simulation time 192511694231 ps
CPU time 424.7 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:47:51 PM PDT 24
Peak memory 201712 kb
Host smart-20b41d2e-d708-4e5a-ba39-62c296845ebc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131350800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1131350800
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.148764012
Short name T315
Test name
Test status
Simulation time 131331706597 ps
CPU time 461.81 seconds
Started Mar 12 12:40:49 PM PDT 24
Finished Mar 12 12:48:31 PM PDT 24
Peak memory 202052 kb
Host smart-0993e218-122b-45e5-a1f3-cd417dbba050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148764012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.148764012
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3263304827
Short name T616
Test name
Test status
Simulation time 29385928803 ps
CPU time 5.69 seconds
Started Mar 12 12:40:48 PM PDT 24
Finished Mar 12 12:40:54 PM PDT 24
Peak memory 201580 kb
Host smart-2372dd15-e7fb-47bf-98a0-8f13fea49120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263304827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3263304827
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1643711212
Short name T602
Test name
Test status
Simulation time 2988433281 ps
CPU time 8.18 seconds
Started Mar 12 12:40:54 PM PDT 24
Finished Mar 12 12:41:02 PM PDT 24
Peak memory 201604 kb
Host smart-4563bdd0-ed2f-495d-9dab-ae064f57d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643711212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1643711212
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2362217679
Short name T787
Test name
Test status
Simulation time 5842399915 ps
CPU time 1.58 seconds
Started Mar 12 12:40:50 PM PDT 24
Finished Mar 12 12:40:52 PM PDT 24
Peak memory 201644 kb
Host smart-14660a4f-31a0-40f1-9865-b18435f850b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362217679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2362217679
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1038241453
Short name T654
Test name
Test status
Simulation time 255197025258 ps
CPU time 726.87 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 210220 kb
Host smart-d7534455-4242-4114-bfad-6c3ba3bdfae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038241453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1038241453
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3873137807
Short name T221
Test name
Test status
Simulation time 193189894963 ps
CPU time 121.46 seconds
Started Mar 12 12:40:48 PM PDT 24
Finished Mar 12 12:42:49 PM PDT 24
Peak memory 210240 kb
Host smart-9f1ffa5c-2cd4-4336-a44c-5c619863a355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873137807 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3873137807
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.525877773
Short name T683
Test name
Test status
Simulation time 380124568 ps
CPU time 0.8 seconds
Started Mar 12 12:40:56 PM PDT 24
Finished Mar 12 12:40:57 PM PDT 24
Peak memory 201704 kb
Host smart-e0bc3536-9c81-41e4-b587-7f1a47ef076b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525877773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.525877773
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.961228473
Short name T604
Test name
Test status
Simulation time 191757900370 ps
CPU time 222.82 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:44:40 PM PDT 24
Peak memory 201744 kb
Host smart-96a47dd4-ad4a-4263-9f28-12e422b16656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961228473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.961228473
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2807564202
Short name T248
Test name
Test status
Simulation time 165070808121 ps
CPU time 96.78 seconds
Started Mar 12 12:40:46 PM PDT 24
Finished Mar 12 12:42:23 PM PDT 24
Peak memory 201780 kb
Host smart-f971c7f5-1dde-487a-9498-44e323d0c60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807564202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2807564202
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3228172866
Short name T156
Test name
Test status
Simulation time 158980966213 ps
CPU time 88.27 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:42:15 PM PDT 24
Peak memory 201720 kb
Host smart-b5695fd9-24a5-4548-a285-2988421810c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228172866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3228172866
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.521109729
Short name T685
Test name
Test status
Simulation time 494447836155 ps
CPU time 296.18 seconds
Started Mar 12 12:40:48 PM PDT 24
Finished Mar 12 12:45:44 PM PDT 24
Peak memory 201824 kb
Host smart-94cbf14c-2c1a-4a66-9d76-f446460df84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521109729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.521109729
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.288295201
Short name T480
Test name
Test status
Simulation time 169441718631 ps
CPU time 104.44 seconds
Started Mar 12 12:40:47 PM PDT 24
Finished Mar 12 12:42:31 PM PDT 24
Peak memory 201760 kb
Host smart-1fe78a91-9087-4798-a8b5-36e6cf9dde00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288295201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.288295201
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2016868877
Short name T251
Test name
Test status
Simulation time 616776293927 ps
CPU time 354.79 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:46:52 PM PDT 24
Peak memory 201856 kb
Host smart-487a3b77-91f8-429d-b89d-e2f339297aa4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016868877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2016868877
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.435432706
Short name T170
Test name
Test status
Simulation time 402920788486 ps
CPU time 462.1 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:48:39 PM PDT 24
Peak memory 201764 kb
Host smart-5f2c8afe-aaf3-432d-b9ae-8fc8350c08b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435432706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.435432706
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2818135240
Short name T306
Test name
Test status
Simulation time 107233792754 ps
CPU time 381.67 seconds
Started Mar 12 12:40:58 PM PDT 24
Finished Mar 12 12:47:20 PM PDT 24
Peak memory 202040 kb
Host smart-aba753be-e8a2-4f03-83ae-b0f78d79361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818135240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2818135240
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3431036131
Short name T525
Test name
Test status
Simulation time 37230073011 ps
CPU time 7.51 seconds
Started Mar 12 12:40:58 PM PDT 24
Finished Mar 12 12:41:06 PM PDT 24
Peak memory 201488 kb
Host smart-404883ef-847f-4b11-8650-10b3a147cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431036131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3431036131
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3417144594
Short name T565
Test name
Test status
Simulation time 4551672301 ps
CPU time 11.45 seconds
Started Mar 12 12:40:56 PM PDT 24
Finished Mar 12 12:41:07 PM PDT 24
Peak memory 201636 kb
Host smart-75fedbed-3e1b-4d3e-8a49-5beb9cce0a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417144594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3417144594
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3896150800
Short name T143
Test name
Test status
Simulation time 5830064611 ps
CPU time 12.56 seconds
Started Mar 12 12:40:48 PM PDT 24
Finished Mar 12 12:41:01 PM PDT 24
Peak memory 201700 kb
Host smart-50cb3af9-f8e5-4462-b4cc-7226c3cb7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896150800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3896150800
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3941190010
Short name T651
Test name
Test status
Simulation time 331412551270 ps
CPU time 853.33 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:55:11 PM PDT 24
Peak memory 212508 kb
Host smart-f01bf70c-88ca-477b-a3d7-7670b27b4725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941190010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3941190010
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2446073107
Short name T779
Test name
Test status
Simulation time 35372096188 ps
CPU time 129.68 seconds
Started Mar 12 12:40:56 PM PDT 24
Finished Mar 12 12:43:06 PM PDT 24
Peak memory 210356 kb
Host smart-2a9ec48f-9c6a-4ace-bc64-6625fe864ee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446073107 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2446073107
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.354518453
Short name T567
Test name
Test status
Simulation time 358954689 ps
CPU time 1.41 seconds
Started Mar 12 12:41:08 PM PDT 24
Finished Mar 12 12:41:10 PM PDT 24
Peak memory 201732 kb
Host smart-98898c89-5242-498e-8cc4-2c3483898de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354518453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.354518453
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3602508502
Short name T213
Test name
Test status
Simulation time 503645999328 ps
CPU time 760.1 seconds
Started Mar 12 12:41:10 PM PDT 24
Finished Mar 12 12:53:51 PM PDT 24
Peak memory 201916 kb
Host smart-43253d36-dc1e-4965-a0d3-67305d357e3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602508502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3602508502
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1999350978
Short name T781
Test name
Test status
Simulation time 500660717921 ps
CPU time 552.31 seconds
Started Mar 12 12:41:07 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 201872 kb
Host smart-f89ed889-bfea-4a75-8068-5a7202bff653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999350978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1999350978
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2828287751
Short name T702
Test name
Test status
Simulation time 484701813012 ps
CPU time 1215.53 seconds
Started Mar 12 12:41:08 PM PDT 24
Finished Mar 12 01:01:24 PM PDT 24
Peak memory 201748 kb
Host smart-955807e2-f058-4d99-b300-8c80184c770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828287751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2828287751
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.759835349
Short name T416
Test name
Test status
Simulation time 333139302282 ps
CPU time 103.59 seconds
Started Mar 12 12:41:09 PM PDT 24
Finished Mar 12 12:42:53 PM PDT 24
Peak memory 201840 kb
Host smart-456c128d-b755-4f5c-9e86-f676d2c8008d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=759835349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.759835349
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1218602926
Short name T696
Test name
Test status
Simulation time 327027526349 ps
CPU time 194.41 seconds
Started Mar 12 12:40:57 PM PDT 24
Finished Mar 12 12:44:12 PM PDT 24
Peak memory 201932 kb
Host smart-af6c6af7-53a1-42fa-b03c-5a8c0debc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218602926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1218602926
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.4247798013
Short name T356
Test name
Test status
Simulation time 158527925490 ps
CPU time 33.28 seconds
Started Mar 12 12:41:08 PM PDT 24
Finished Mar 12 12:41:42 PM PDT 24
Peak memory 201780 kb
Host smart-9bc4b4cf-8bc6-44a6-a2f7-03cb5f9239dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247798013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.4247798013
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2436417789
Short name T435
Test name
Test status
Simulation time 165877945548 ps
CPU time 103.11 seconds
Started Mar 12 12:42:53 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 201548 kb
Host smart-890c57f3-2580-47a4-8455-3c2dd9939f49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436417789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2436417789
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.935373509
Short name T589
Test name
Test status
Simulation time 409633052650 ps
CPU time 252.23 seconds
Started Mar 12 12:41:08 PM PDT 24
Finished Mar 12 12:45:20 PM PDT 24
Peak memory 201848 kb
Host smart-cabbe2ec-9990-45a2-9931-f21c7fb4aa73
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935373509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.935373509
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2596256542
Short name T39
Test name
Test status
Simulation time 114382004915 ps
CPU time 439.32 seconds
Started Mar 12 12:41:09 PM PDT 24
Finished Mar 12 12:48:29 PM PDT 24
Peak memory 202092 kb
Host smart-fd61f200-44c7-46e2-ba7b-09f31f5e0664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596256542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2596256542
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2608254629
Short name T468
Test name
Test status
Simulation time 26829956278 ps
CPU time 16.37 seconds
Started Mar 12 12:41:07 PM PDT 24
Finished Mar 12 12:41:23 PM PDT 24
Peak memory 201732 kb
Host smart-cd247cf4-b4c7-4000-be89-3c0b89bd2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608254629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2608254629
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2169337796
Short name T389
Test name
Test status
Simulation time 4500370721 ps
CPU time 1.91 seconds
Started Mar 12 12:41:07 PM PDT 24
Finished Mar 12 12:41:09 PM PDT 24
Peak memory 201616 kb
Host smart-f2454e0b-24d1-494e-bc85-56fa2711898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169337796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2169337796
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1313316385
Short name T336
Test name
Test status
Simulation time 5623361867 ps
CPU time 3.8 seconds
Started Mar 12 12:40:58 PM PDT 24
Finished Mar 12 12:41:02 PM PDT 24
Peak memory 201500 kb
Host smart-8462f9fc-d783-4f28-aa0b-b56a0ee01822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313316385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1313316385
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2408335277
Short name T87
Test name
Test status
Simulation time 501206583 ps
CPU time 0.97 seconds
Started Mar 12 12:41:32 PM PDT 24
Finished Mar 12 12:41:34 PM PDT 24
Peak memory 201608 kb
Host smart-dfda75cd-b0dd-4f36-a206-2cb964fae8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408335277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2408335277
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2002938483
Short name T80
Test name
Test status
Simulation time 343721548633 ps
CPU time 697.55 seconds
Started Mar 12 12:41:16 PM PDT 24
Finished Mar 12 12:52:54 PM PDT 24
Peak memory 201964 kb
Host smart-d6757f86-8a08-4ca2-a3ba-0e35f781ae2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002938483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2002938483
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3784509797
Short name T162
Test name
Test status
Simulation time 502704245094 ps
CPU time 1121.2 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:59:59 PM PDT 24
Peak memory 201876 kb
Host smart-05f72c1f-d0af-4003-9d79-9fea3d7ac541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784509797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3784509797
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2542475741
Short name T300
Test name
Test status
Simulation time 339522199367 ps
CPU time 213.21 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:44:50 PM PDT 24
Peak memory 201852 kb
Host smart-ba2b43ba-afc2-4374-8bca-aad70d6afc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542475741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2542475741
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3557933999
Short name T425
Test name
Test status
Simulation time 335108059869 ps
CPU time 754.91 seconds
Started Mar 12 12:41:16 PM PDT 24
Finished Mar 12 12:53:51 PM PDT 24
Peak memory 201916 kb
Host smart-2a78daf8-c9a8-418b-9317-47e2283af4b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557933999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3557933999
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2650539791
Short name T239
Test name
Test status
Simulation time 163919735367 ps
CPU time 173.53 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:44:11 PM PDT 24
Peak memory 201884 kb
Host smart-7bad84b2-a60d-4f84-b983-b2dce174216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650539791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2650539791
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3599756766
Short name T624
Test name
Test status
Simulation time 320925061476 ps
CPU time 528.3 seconds
Started Mar 12 12:41:15 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 201836 kb
Host smart-3e5e6c41-8c4b-4203-84e5-483371e5ef87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599756766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3599756766
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.887672399
Short name T791
Test name
Test status
Simulation time 345747326356 ps
CPU time 867.55 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:55:45 PM PDT 24
Peak memory 201764 kb
Host smart-fd75ceb1-6cf0-4574-bf5d-a9a3804658c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887672399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.887672399
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.484965506
Short name T438
Test name
Test status
Simulation time 200936806561 ps
CPU time 36.11 seconds
Started Mar 12 12:41:19 PM PDT 24
Finished Mar 12 12:41:55 PM PDT 24
Peak memory 201844 kb
Host smart-a969aff2-083d-4a30-82cb-ac76de0e3b59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484965506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.484965506
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1334118207
Short name T487
Test name
Test status
Simulation time 109922212248 ps
CPU time 592.04 seconds
Started Mar 12 12:41:16 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 202172 kb
Host smart-68e204e5-2400-4eb3-ba8c-75ca4ea62d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334118207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1334118207
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3543507117
Short name T388
Test name
Test status
Simulation time 25331678872 ps
CPU time 56.9 seconds
Started Mar 12 12:41:16 PM PDT 24
Finished Mar 12 12:42:13 PM PDT 24
Peak memory 201612 kb
Host smart-ba18eccd-fac4-4e8c-b491-1ac646e642b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543507117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3543507117
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2212448149
Short name T78
Test name
Test status
Simulation time 3791023342 ps
CPU time 1.27 seconds
Started Mar 12 12:41:18 PM PDT 24
Finished Mar 12 12:41:19 PM PDT 24
Peak memory 201700 kb
Host smart-94860e2f-a7ba-4516-83f9-385c423510f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212448149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2212448149
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.439226589
Short name T119
Test name
Test status
Simulation time 5772236067 ps
CPU time 6.62 seconds
Started Mar 12 12:41:08 PM PDT 24
Finished Mar 12 12:41:14 PM PDT 24
Peak memory 201604 kb
Host smart-5022c308-2edc-4507-a9fd-66b4213de2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439226589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.439226589
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2408892962
Short name T28
Test name
Test status
Simulation time 164253129995 ps
CPU time 195.18 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:44:32 PM PDT 24
Peak memory 201672 kb
Host smart-671d692e-7ff3-4bc6-85b3-ba13cbe0969f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408892962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2408892962
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.256546659
Short name T13
Test name
Test status
Simulation time 74823601087 ps
CPU time 54.89 seconds
Started Mar 12 12:41:17 PM PDT 24
Finished Mar 12 12:42:12 PM PDT 24
Peak memory 210356 kb
Host smart-b10e6423-bda5-4c1d-9535-e6fd4a98b246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256546659 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.256546659
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.576402385
Short name T660
Test name
Test status
Simulation time 423864685 ps
CPU time 1.29 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:41:38 PM PDT 24
Peak memory 201736 kb
Host smart-240b6d2f-5cb6-44aa-b8b0-7ad3b0f47e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576402385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.576402385
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1002408191
Short name T199
Test name
Test status
Simulation time 340979793075 ps
CPU time 798.5 seconds
Started Mar 12 12:41:29 PM PDT 24
Finished Mar 12 12:54:48 PM PDT 24
Peak memory 201876 kb
Host smart-65d5e260-0737-4a58-b8a3-5adb526ce085
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002408191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1002408191
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.746791470
Short name T235
Test name
Test status
Simulation time 328693011468 ps
CPU time 406.4 seconds
Started Mar 12 12:41:32 PM PDT 24
Finished Mar 12 12:48:19 PM PDT 24
Peak memory 201924 kb
Host smart-25ba806c-b01c-4e21-94b2-08fe1e2c2707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746791470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.746791470
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3133016184
Short name T749
Test name
Test status
Simulation time 164617432207 ps
CPU time 195.14 seconds
Started Mar 12 12:41:30 PM PDT 24
Finished Mar 12 12:44:46 PM PDT 24
Peak memory 201908 kb
Host smart-78f06f2f-4941-4667-8bf1-c96eb68ab508
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133016184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3133016184
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2807288992
Short name T155
Test name
Test status
Simulation time 498930389389 ps
CPU time 629.67 seconds
Started Mar 12 12:41:32 PM PDT 24
Finished Mar 12 12:52:02 PM PDT 24
Peak memory 201864 kb
Host smart-645372ad-d134-4bd1-9d84-e2186101b9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807288992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2807288992
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3953881228
Short name T459
Test name
Test status
Simulation time 327675617440 ps
CPU time 298.16 seconds
Started Mar 12 12:41:32 PM PDT 24
Finished Mar 12 12:46:31 PM PDT 24
Peak memory 201788 kb
Host smart-1566976b-bd41-4b29-a0a0-296ab82f5764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953881228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3953881228
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.502028387
Short name T734
Test name
Test status
Simulation time 377675545975 ps
CPU time 873.38 seconds
Started Mar 12 12:41:31 PM PDT 24
Finished Mar 12 12:56:05 PM PDT 24
Peak memory 201984 kb
Host smart-e6a68a5f-37c1-4f67-a24c-4c9d0e835206
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502028387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.502028387
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3746102679
Short name T464
Test name
Test status
Simulation time 399008304047 ps
CPU time 221.61 seconds
Started Mar 12 12:41:30 PM PDT 24
Finished Mar 12 12:45:12 PM PDT 24
Peak memory 201788 kb
Host smart-27ae8e10-5acf-49cc-8229-fe192cd015fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746102679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3746102679
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3895324263
Short name T360
Test name
Test status
Simulation time 128974398108 ps
CPU time 437.15 seconds
Started Mar 12 12:41:38 PM PDT 24
Finished Mar 12 12:48:55 PM PDT 24
Peak memory 202128 kb
Host smart-894cfab5-1d74-4bdd-bdc7-01eb3bad2291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895324263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3895324263
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.909562971
Short name T694
Test name
Test status
Simulation time 46879521221 ps
CPU time 29.07 seconds
Started Mar 12 12:41:31 PM PDT 24
Finished Mar 12 12:42:01 PM PDT 24
Peak memory 201628 kb
Host smart-7caeb0d4-8a42-4d99-8bcb-98c659ded31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909562971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.909562971
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1551929036
Short name T531
Test name
Test status
Simulation time 2936024252 ps
CPU time 7.41 seconds
Started Mar 12 12:41:29 PM PDT 24
Finished Mar 12 12:41:37 PM PDT 24
Peak memory 201584 kb
Host smart-b0e5a44b-ea6c-44d3-a655-bd2aa0bc24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551929036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1551929036
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1651493798
Short name T469
Test name
Test status
Simulation time 5698321675 ps
CPU time 14.23 seconds
Started Mar 12 12:41:30 PM PDT 24
Finished Mar 12 12:41:44 PM PDT 24
Peak memory 201716 kb
Host smart-2f6bbce9-b612-43ce-be6f-34295cd32c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651493798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1651493798
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3078257246
Short name T713
Test name
Test status
Simulation time 492666793837 ps
CPU time 1163.97 seconds
Started Mar 12 12:41:39 PM PDT 24
Finished Mar 12 01:01:04 PM PDT 24
Peak memory 201768 kb
Host smart-836c84bd-36b8-46dc-a7bd-61b1c9989eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078257246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3078257246
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.325106793
Short name T17
Test name
Test status
Simulation time 432287965588 ps
CPU time 436.53 seconds
Started Mar 12 12:41:38 PM PDT 24
Finished Mar 12 12:48:54 PM PDT 24
Peak memory 210464 kb
Host smart-9b569a75-a50f-4949-9b7d-351d78c7c6de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325106793 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.325106793
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2493438657
Short name T418
Test name
Test status
Simulation time 366645334 ps
CPU time 1.37 seconds
Started Mar 12 12:41:50 PM PDT 24
Finished Mar 12 12:41:51 PM PDT 24
Peak memory 201540 kb
Host smart-05cb0b12-9493-4be6-8a48-1eb3ebf334d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493438657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2493438657
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3411784052
Short name T659
Test name
Test status
Simulation time 184189487022 ps
CPU time 389.89 seconds
Started Mar 12 12:41:38 PM PDT 24
Finished Mar 12 12:48:09 PM PDT 24
Peak memory 201800 kb
Host smart-e1642322-fca9-4318-b9b1-c94205c260d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411784052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3411784052
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1483986453
Short name T634
Test name
Test status
Simulation time 346961895513 ps
CPU time 417.45 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:48:34 PM PDT 24
Peak memory 201748 kb
Host smart-b5a3d860-0e5c-4390-b18a-603b7c90bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483986453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1483986453
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.28675028
Short name T672
Test name
Test status
Simulation time 166705311857 ps
CPU time 101.21 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:43:18 PM PDT 24
Peak memory 201864 kb
Host smart-a01b66e7-24c5-40fc-a935-b72b6eda8581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28675028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.28675028
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4005254994
Short name T724
Test name
Test status
Simulation time 336080099483 ps
CPU time 745.37 seconds
Started Mar 12 12:41:40 PM PDT 24
Finished Mar 12 12:54:05 PM PDT 24
Peak memory 201804 kb
Host smart-de28fed3-5740-4f20-81aa-c04d5a9c2d8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005254994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4005254994
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.148778404
Short name T183
Test name
Test status
Simulation time 164592912225 ps
CPU time 361.75 seconds
Started Mar 12 12:41:40 PM PDT 24
Finished Mar 12 12:47:42 PM PDT 24
Peak memory 201800 kb
Host smart-8d1d3691-7352-438a-be20-d1cb18bbcd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148778404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.148778404
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2156113471
Short name T10
Test name
Test status
Simulation time 164991889419 ps
CPU time 184.56 seconds
Started Mar 12 12:41:39 PM PDT 24
Finished Mar 12 12:44:44 PM PDT 24
Peak memory 201756 kb
Host smart-4048a4dc-1241-441e-99fd-971afc6ca22f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156113471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2156113471
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.865674492
Short name T283
Test name
Test status
Simulation time 544847816782 ps
CPU time 362.46 seconds
Started Mar 12 12:41:40 PM PDT 24
Finished Mar 12 12:47:43 PM PDT 24
Peak memory 201752 kb
Host smart-db5dbd32-0ecb-46a4-b312-3d634094737e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865674492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.865674492
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1440719590
Short name T536
Test name
Test status
Simulation time 201138130060 ps
CPU time 113.45 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:43:30 PM PDT 24
Peak memory 201864 kb
Host smart-d434fb64-7a70-4981-8204-aaaabe0a46c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440719590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1440719590
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.203177622
Short name T609
Test name
Test status
Simulation time 88970285958 ps
CPU time 277.73 seconds
Started Mar 12 12:41:50 PM PDT 24
Finished Mar 12 12:46:28 PM PDT 24
Peak memory 202152 kb
Host smart-82e853ea-521a-4412-9b4a-877e6b1aa4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203177622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.203177622
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2704230977
Short name T385
Test name
Test status
Simulation time 43960655676 ps
CPU time 108.89 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:43:26 PM PDT 24
Peak memory 201488 kb
Host smart-7132c3d0-cf58-44fb-9758-ec9ed8983106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704230977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2704230977
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3989554568
Short name T419
Test name
Test status
Simulation time 4473775561 ps
CPU time 3.01 seconds
Started Mar 12 12:41:37 PM PDT 24
Finished Mar 12 12:41:40 PM PDT 24
Peak memory 201600 kb
Host smart-40b45091-7dea-494b-8b76-4905c8eee8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989554568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3989554568
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1284724569
Short name T383
Test name
Test status
Simulation time 6130947924 ps
CPU time 4.63 seconds
Started Mar 12 12:41:39 PM PDT 24
Finished Mar 12 12:41:44 PM PDT 24
Peak memory 201588 kb
Host smart-b15ce1ab-3eba-4c59-a874-4b68e14bffde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284724569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1284724569
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.268858052
Short name T346
Test name
Test status
Simulation time 309660972 ps
CPU time 0.91 seconds
Started Mar 12 12:41:58 PM PDT 24
Finished Mar 12 12:42:00 PM PDT 24
Peak memory 201728 kb
Host smart-15794924-f046-4052-ad85-b55f42fe4da6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268858052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.268858052
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.56135910
Short name T250
Test name
Test status
Simulation time 578188555760 ps
CPU time 180.19 seconds
Started Mar 12 12:41:58 PM PDT 24
Finished Mar 12 12:44:58 PM PDT 24
Peak memory 201916 kb
Host smart-204fc612-775b-4321-aa76-91799d82f048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56135910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gatin
g.56135910
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.4198844959
Short name T74
Test name
Test status
Simulation time 329655816864 ps
CPU time 733.81 seconds
Started Mar 12 12:41:57 PM PDT 24
Finished Mar 12 12:54:11 PM PDT 24
Peak memory 201884 kb
Host smart-4406b3ba-2f48-4efc-8517-beca2910bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198844959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.4198844959
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3104627393
Short name T501
Test name
Test status
Simulation time 162719880096 ps
CPU time 104.7 seconds
Started Mar 12 12:41:48 PM PDT 24
Finished Mar 12 12:43:33 PM PDT 24
Peak memory 201876 kb
Host smart-a71141d0-5fb9-4675-9c29-fdb62748c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104627393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3104627393
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2330737084
Short name T690
Test name
Test status
Simulation time 163426180258 ps
CPU time 403.57 seconds
Started Mar 12 12:41:49 PM PDT 24
Finished Mar 12 12:48:33 PM PDT 24
Peak memory 201876 kb
Host smart-55c9cee5-dea2-456d-b3b8-1f4fc3d89be6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330737084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2330737084
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1158386530
Short name T121
Test name
Test status
Simulation time 162266190588 ps
CPU time 85.73 seconds
Started Mar 12 12:41:50 PM PDT 24
Finished Mar 12 12:43:16 PM PDT 24
Peak memory 201816 kb
Host smart-bb5ebdb0-df2e-498a-8077-fc7cd223d40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158386530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1158386530
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1589001698
Short name T443
Test name
Test status
Simulation time 159178727672 ps
CPU time 389.78 seconds
Started Mar 12 12:41:49 PM PDT 24
Finished Mar 12 12:48:19 PM PDT 24
Peak memory 201656 kb
Host smart-1a768398-a3a4-4e4d-933a-1b1fc0ceb50c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589001698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1589001698
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1039809652
Short name T147
Test name
Test status
Simulation time 182515739960 ps
CPU time 152.98 seconds
Started Mar 12 12:41:50 PM PDT 24
Finished Mar 12 12:44:23 PM PDT 24
Peak memory 201792 kb
Host smart-5126f6fe-4643-427b-bde0-b32ea8cef87f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039809652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1039809652
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.901976088
Short name T746
Test name
Test status
Simulation time 194158606380 ps
CPU time 464.07 seconds
Started Mar 12 12:41:57 PM PDT 24
Finished Mar 12 12:49:42 PM PDT 24
Peak memory 201872 kb
Host smart-6bfe0ee3-dd99-45ad-9016-388385eec6ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901976088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.901976088
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3512392910
Short name T313
Test name
Test status
Simulation time 129259268706 ps
CPU time 692.02 seconds
Started Mar 12 12:43:12 PM PDT 24
Finished Mar 12 12:54:45 PM PDT 24
Peak memory 201720 kb
Host smart-39d99200-445c-4aff-9d6b-8231b2eac442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512392910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3512392910
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1172223486
Short name T394
Test name
Test status
Simulation time 35371593137 ps
CPU time 43.51 seconds
Started Mar 12 12:41:57 PM PDT 24
Finished Mar 12 12:42:41 PM PDT 24
Peak memory 201704 kb
Host smart-d36c22d3-2d0b-45de-8377-e0afe75f5e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172223486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1172223486
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1523235927
Short name T428
Test name
Test status
Simulation time 3252319464 ps
CPU time 4.34 seconds
Started Mar 12 12:41:58 PM PDT 24
Finished Mar 12 12:42:03 PM PDT 24
Peak memory 201684 kb
Host smart-01113c1b-3106-4bf4-ac4a-971be2cf0cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523235927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1523235927
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.903909224
Short name T461
Test name
Test status
Simulation time 5999020092 ps
CPU time 12.42 seconds
Started Mar 12 12:41:48 PM PDT 24
Finished Mar 12 12:42:01 PM PDT 24
Peak memory 201612 kb
Host smart-ddbead91-6a71-46f0-a1af-a8bfe497ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903909224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.903909224
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3860023582
Short name T264
Test name
Test status
Simulation time 288677466694 ps
CPU time 1002 seconds
Started Mar 12 12:41:58 PM PDT 24
Finished Mar 12 12:58:40 PM PDT 24
Peak memory 212444 kb
Host smart-ef7e7198-9d17-4993-a027-5d289fbbb766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860023582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3860023582
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3266129941
Short name T720
Test name
Test status
Simulation time 138415197281 ps
CPU time 155.7 seconds
Started Mar 12 12:41:58 PM PDT 24
Finished Mar 12 12:44:34 PM PDT 24
Peak memory 210512 kb
Host smart-9cb16e86-e6b2-487c-87a4-547be5fda93f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266129941 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3266129941
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1033794121
Short name T625
Test name
Test status
Simulation time 310225697 ps
CPU time 0.85 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:36:36 PM PDT 24
Peak memory 201720 kb
Host smart-0c268432-471c-4a09-bd37-dd3a316bf3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033794121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1033794121
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2218510034
Short name T214
Test name
Test status
Simulation time 197465180507 ps
CPU time 92.33 seconds
Started Mar 12 12:36:30 PM PDT 24
Finished Mar 12 12:38:02 PM PDT 24
Peak memory 201896 kb
Host smart-7a0b95a9-fb95-499a-939d-766266f3ecab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218510034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2218510034
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2064953662
Short name T131
Test name
Test status
Simulation time 493080456930 ps
CPU time 274.6 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:41:03 PM PDT 24
Peak memory 201892 kb
Host smart-000fa039-d699-4475-be6e-fd9bfa4bbff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064953662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2064953662
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.819032255
Short name T621
Test name
Test status
Simulation time 327095220816 ps
CPU time 194.98 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:39:44 PM PDT 24
Peak memory 201720 kb
Host smart-621c28a4-5cf0-4d6f-8363-43608a716ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819032255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.819032255
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2160213853
Short name T166
Test name
Test status
Simulation time 161979371854 ps
CPU time 136.83 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:38:46 PM PDT 24
Peak memory 201892 kb
Host smart-02b400b0-dfba-4054-aad9-8f9388417f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160213853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2160213853
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2870247188
Short name T285
Test name
Test status
Simulation time 166411361825 ps
CPU time 195.86 seconds
Started Mar 12 12:36:28 PM PDT 24
Finished Mar 12 12:39:45 PM PDT 24
Peak memory 201708 kb
Host smart-fe05093d-4a06-4f7a-b45e-19e082a34642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870247188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2870247188
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2357985493
Short name T745
Test name
Test status
Simulation time 154293535956 ps
CPU time 91.46 seconds
Started Mar 12 12:36:31 PM PDT 24
Finished Mar 12 12:38:03 PM PDT 24
Peak memory 201852 kb
Host smart-71000896-fe29-4136-9cf2-06d888728e3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357985493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2357985493
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4125575400
Short name T270
Test name
Test status
Simulation time 559220460130 ps
CPU time 344.79 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:42:14 PM PDT 24
Peak memory 201860 kb
Host smart-b0ad5930-232a-4fe4-ab00-b7e5c11a57f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125575400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4125575400
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2548979685
Short name T623
Test name
Test status
Simulation time 399502885278 ps
CPU time 240.49 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:40:30 PM PDT 24
Peak memory 201736 kb
Host smart-a623db9f-8462-4c44-b8ce-0f0e54f6542a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548979685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2548979685
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1370380998
Short name T707
Test name
Test status
Simulation time 123103671191 ps
CPU time 515.81 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:45:11 PM PDT 24
Peak memory 201992 kb
Host smart-233636bb-d093-4f1d-b66b-50f32ac6d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370380998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1370380998
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.4251925620
Short name T766
Test name
Test status
Simulation time 23698873453 ps
CPU time 16.64 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:36:51 PM PDT 24
Peak memory 201524 kb
Host smart-e03e3248-da0e-4ccc-b18d-cfdf0697989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251925620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4251925620
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2813916566
Short name T509
Test name
Test status
Simulation time 3958798499 ps
CPU time 9.84 seconds
Started Mar 12 12:36:29 PM PDT 24
Finished Mar 12 12:36:39 PM PDT 24
Peak memory 201716 kb
Host smart-5a316aa3-7e06-4e20-8f33-7c6b2cc73b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813916566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2813916566
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3754378180
Short name T427
Test name
Test status
Simulation time 5895000863 ps
CPU time 7.57 seconds
Started Mar 12 12:36:30 PM PDT 24
Finished Mar 12 12:36:38 PM PDT 24
Peak memory 201700 kb
Host smart-c84b0fa2-6b8a-4e14-b251-90ae5b639331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754378180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3754378180
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2369157581
Short name T417
Test name
Test status
Simulation time 323147945 ps
CPU time 1.42 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:36:40 PM PDT 24
Peak memory 201128 kb
Host smart-d7e605df-6fef-4d69-8e53-d5095b75ac66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369157581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2369157581
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1482424711
Short name T704
Test name
Test status
Simulation time 325192016492 ps
CPU time 79.42 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:37:56 PM PDT 24
Peak memory 201764 kb
Host smart-b3b8fadd-c7c3-4e0d-bfcf-c11a624bd6d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482424711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1482424711
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.353663989
Short name T280
Test name
Test status
Simulation time 507947819646 ps
CPU time 321.47 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:41:58 PM PDT 24
Peak memory 201876 kb
Host smart-864a1f37-ec00-416d-8162-672ccb0cfbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353663989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.353663989
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2500034758
Short name T566
Test name
Test status
Simulation time 498624005718 ps
CPU time 522.59 seconds
Started Mar 12 12:36:39 PM PDT 24
Finished Mar 12 12:45:22 PM PDT 24
Peak memory 201852 kb
Host smart-ac7be33f-de49-47ed-9675-a99edbafdf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500034758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2500034758
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1109703722
Short name T396
Test name
Test status
Simulation time 491236540615 ps
CPU time 478.28 seconds
Started Mar 12 12:36:34 PM PDT 24
Finished Mar 12 12:44:32 PM PDT 24
Peak memory 201832 kb
Host smart-be325941-f091-477f-8a18-f208cb7020d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109703722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1109703722
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1487032246
Short name T664
Test name
Test status
Simulation time 490083568111 ps
CPU time 1176.01 seconds
Started Mar 12 12:36:37 PM PDT 24
Finished Mar 12 12:56:13 PM PDT 24
Peak memory 201916 kb
Host smart-f888e79b-1374-4c9c-98b6-313e43c6d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487032246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1487032246
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.384780912
Short name T439
Test name
Test status
Simulation time 317169081090 ps
CPU time 174.63 seconds
Started Mar 12 12:36:37 PM PDT 24
Finished Mar 12 12:39:32 PM PDT 24
Peak memory 201772 kb
Host smart-3a9ed153-5ef6-4b6d-b4a3-6d6963bad7d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=384780912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.384780912
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.13793766
Short name T139
Test name
Test status
Simulation time 388594193939 ps
CPU time 240.89 seconds
Started Mar 12 12:36:37 PM PDT 24
Finished Mar 12 12:40:38 PM PDT 24
Peak memory 201868 kb
Host smart-6e02a3dc-afab-4a29-9a16-bd51920d4c8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wa
keup.13793766
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3327845521
Short name T420
Test name
Test status
Simulation time 198490552550 ps
CPU time 123.38 seconds
Started Mar 12 12:36:34 PM PDT 24
Finished Mar 12 12:38:38 PM PDT 24
Peak memory 201708 kb
Host smart-03e67dc0-bb66-49b1-a5a8-c5d7e4727f88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327845521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3327845521
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1734799667
Short name T638
Test name
Test status
Simulation time 85839073721 ps
CPU time 354.62 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:42:33 PM PDT 24
Peak memory 202020 kb
Host smart-18070fd3-1c13-4793-be76-378f7d465992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734799667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1734799667
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3929328999
Short name T331
Test name
Test status
Simulation time 46479146907 ps
CPU time 104.2 seconds
Started Mar 12 12:36:42 PM PDT 24
Finished Mar 12 12:38:28 PM PDT 24
Peak memory 201708 kb
Host smart-aff15581-8ded-411c-8593-7b33e6b9eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929328999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3929328999
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2105605331
Short name T444
Test name
Test status
Simulation time 3136225630 ps
CPU time 3.91 seconds
Started Mar 12 12:36:33 PM PDT 24
Finished Mar 12 12:36:38 PM PDT 24
Peak memory 201696 kb
Host smart-a8969cb0-f006-432e-91bf-d84593011b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105605331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2105605331
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1549193318
Short name T497
Test name
Test status
Simulation time 5880423725 ps
CPU time 13.51 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:36:52 PM PDT 24
Peak memory 201712 kb
Host smart-bf08a4c8-3d43-4b48-92ce-5e6186243a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549193318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1549193318
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4202634180
Short name T165
Test name
Test status
Simulation time 335839159489 ps
CPU time 777.07 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 201816 kb
Host smart-c0e0359c-737a-439c-981a-d19486665847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202634180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4202634180
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3021454461
Short name T562
Test name
Test status
Simulation time 497151855 ps
CPU time 1.18 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:45 PM PDT 24
Peak memory 201716 kb
Host smart-e5f0d5ac-6690-48a1-8989-fcfd9c23e884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021454461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3021454461
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3447821094
Short name T212
Test name
Test status
Simulation time 333251227000 ps
CPU time 168 seconds
Started Mar 12 12:36:42 PM PDT 24
Finished Mar 12 12:39:31 PM PDT 24
Peak memory 201888 kb
Host smart-dcfd950f-eff9-4bf3-be2e-fb16cf5835d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447821094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3447821094
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1148202370
Short name T167
Test name
Test status
Simulation time 319838902528 ps
CPU time 188.83 seconds
Started Mar 12 12:36:34 PM PDT 24
Finished Mar 12 12:39:44 PM PDT 24
Peak memory 201912 kb
Host smart-28b69149-bab5-4041-857a-a07d28a2de2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148202370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1148202370
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2174554988
Short name T593
Test name
Test status
Simulation time 500191321501 ps
CPU time 848.88 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 201848 kb
Host smart-6f3a9843-d0e9-4be5-b91b-5b44d2cdd9f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174554988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2174554988
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3073826503
Short name T145
Test name
Test status
Simulation time 494118402761 ps
CPU time 172.03 seconds
Started Mar 12 12:36:37 PM PDT 24
Finished Mar 12 12:39:29 PM PDT 24
Peak memory 201768 kb
Host smart-6cf69875-c7f4-4ef9-a64f-4a880404273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073826503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3073826503
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2843809483
Short name T374
Test name
Test status
Simulation time 484740627571 ps
CPU time 1036.02 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:54:00 PM PDT 24
Peak memory 201928 kb
Host smart-8e1b50aa-6850-459b-8b54-b30b97dd7668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843809483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2843809483
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2992470136
Short name T288
Test name
Test status
Simulation time 338386916189 ps
CPU time 102.41 seconds
Started Mar 12 12:36:34 PM PDT 24
Finished Mar 12 12:38:17 PM PDT 24
Peak memory 202128 kb
Host smart-5bc31413-0c76-461c-becb-fcdae1df2c20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992470136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2992470136
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.20623029
Short name T588
Test name
Test status
Simulation time 197628617906 ps
CPU time 106.77 seconds
Started Mar 12 12:36:39 PM PDT 24
Finished Mar 12 12:38:26 PM PDT 24
Peak memory 201748 kb
Host smart-81d903e4-9664-41a7-aa72-a44ac85b34bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20623029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad
c_ctrl_filters_wakeup_fixed.20623029
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.2708639669
Short name T637
Test name
Test status
Simulation time 93755607892 ps
CPU time 471.64 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:44:36 PM PDT 24
Peak memory 202084 kb
Host smart-811d5d4d-e470-4792-aa3a-b8633a570e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708639669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.2708639669
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3517911471
Short name T595
Test name
Test status
Simulation time 43253120649 ps
CPU time 26.35 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:37:05 PM PDT 24
Peak memory 201612 kb
Host smart-1a548f7d-e214-48ff-a6d9-ed269848274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517911471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3517911471
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2137240748
Short name T629
Test name
Test status
Simulation time 4341615325 ps
CPU time 9.83 seconds
Started Mar 12 12:36:39 PM PDT 24
Finished Mar 12 12:36:49 PM PDT 24
Peak memory 201672 kb
Host smart-81ab5573-4f47-4a60-88e3-b56f2e691e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137240748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2137240748
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1806944592
Short name T761
Test name
Test status
Simulation time 6058003521 ps
CPU time 5.07 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:36:40 PM PDT 24
Peak memory 201712 kb
Host smart-c502977a-1c12-4c9f-b91a-5006178d596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806944592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1806944592
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2755930743
Short name T273
Test name
Test status
Simulation time 656545737069 ps
CPU time 1548.56 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 01:02:27 PM PDT 24
Peak memory 201420 kb
Host smart-3f0633f8-68b4-449e-b27c-459dde625dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755930743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2755930743
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2416899747
Short name T269
Test name
Test status
Simulation time 96247350684 ps
CPU time 100.84 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:38:25 PM PDT 24
Peak memory 210308 kb
Host smart-2e41f524-ae29-4347-a8ca-65b8d5dfadec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416899747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2416899747
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3463771240
Short name T494
Test name
Test status
Simulation time 400802031 ps
CPU time 1.08 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:36:36 PM PDT 24
Peak memory 201592 kb
Host smart-2c0e1a59-4a5c-4485-b253-d09a4c2ca942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463771240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3463771240
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3834389247
Short name T680
Test name
Test status
Simulation time 329652375377 ps
CPU time 713.37 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:48:31 PM PDT 24
Peak memory 201868 kb
Host smart-228eda58-e8c0-4df9-8e11-5213031056da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834389247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3834389247
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2102584165
Short name T601
Test name
Test status
Simulation time 165619983712 ps
CPU time 94.14 seconds
Started Mar 12 12:36:42 PM PDT 24
Finished Mar 12 12:38:16 PM PDT 24
Peak memory 201760 kb
Host smart-ce24033d-e76f-4ff0-a739-278fb888ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102584165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2102584165
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3366611593
Short name T130
Test name
Test status
Simulation time 499724408510 ps
CPU time 311.26 seconds
Started Mar 12 12:36:32 PM PDT 24
Finished Mar 12 12:41:43 PM PDT 24
Peak memory 201904 kb
Host smart-bb3d6666-7b5e-416c-8a55-e028dbe7091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366611593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3366611593
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.88522986
Short name T128
Test name
Test status
Simulation time 165296419087 ps
CPU time 38.22 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:37:17 PM PDT 24
Peak memory 201912 kb
Host smart-fba19de9-fc93-47ed-a570-09e7a53fd466
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=88522986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt_
fixed.88522986
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.113361315
Short name T466
Test name
Test status
Simulation time 329341002059 ps
CPU time 106.64 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:38:30 PM PDT 24
Peak memory 201880 kb
Host smart-d45f5f7b-830b-49f1-bc8c-99c46a999818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113361315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.113361315
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3850911434
Short name T351
Test name
Test status
Simulation time 161319064233 ps
CPU time 89.2 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:38:07 PM PDT 24
Peak memory 201788 kb
Host smart-b967ad77-5ddd-439e-8cf3-c4a31d07f832
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850911434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3850911434
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.574736394
Short name T231
Test name
Test status
Simulation time 605244492844 ps
CPU time 652.15 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:47:27 PM PDT 24
Peak memory 201772 kb
Host smart-42e8eaad-6a80-415b-b61d-e8da21eef70a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574736394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.574736394
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2243074990
Short name T75
Test name
Test status
Simulation time 400801398086 ps
CPU time 948.09 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:52:24 PM PDT 24
Peak memory 201764 kb
Host smart-6840d720-603c-481e-a2b4-3b5290a0ee6e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243074990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2243074990
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.523267501
Short name T726
Test name
Test status
Simulation time 90194867207 ps
CPU time 452.4 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:44:09 PM PDT 24
Peak memory 201864 kb
Host smart-41dd025d-00a8-4428-acde-cb88c710412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523267501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.523267501
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.740170448
Short name T377
Test name
Test status
Simulation time 29835965627 ps
CPU time 11.95 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:36:48 PM PDT 24
Peak memory 201684 kb
Host smart-a3d5c312-b15c-4b51-a2f2-35d015ba1de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740170448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.740170448
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1852646808
Short name T620
Test name
Test status
Simulation time 4505440094 ps
CPU time 6 seconds
Started Mar 12 12:36:35 PM PDT 24
Finished Mar 12 12:36:41 PM PDT 24
Peak memory 201596 kb
Host smart-490d2a84-afca-456d-b56f-0cbe31486081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852646808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1852646808
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2049537625
Short name T606
Test name
Test status
Simulation time 5784310359 ps
CPU time 4.55 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:36:41 PM PDT 24
Peak memory 201672 kb
Host smart-3065c033-476b-4821-8e2f-73ada0849994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049537625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2049537625
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3279481017
Short name T433
Test name
Test status
Simulation time 119711941075 ps
CPU time 419.25 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:43:36 PM PDT 24
Peak memory 210548 kb
Host smart-e2e9c37f-ed2f-4135-a820-9a7ddf6eefb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279481017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3279481017
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3818012969
Short name T33
Test name
Test status
Simulation time 50428438736 ps
CPU time 49.97 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:37:34 PM PDT 24
Peak memory 202036 kb
Host smart-5a62bc36-76fe-49cf-ba2f-0aeea2d7cc75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818012969 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3818012969
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.290838934
Short name T479
Test name
Test status
Simulation time 319570241 ps
CPU time 0.78 seconds
Started Mar 12 12:36:44 PM PDT 24
Finished Mar 12 12:36:45 PM PDT 24
Peak memory 201600 kb
Host smart-004fc94d-d752-4a18-a352-65c28f7bd57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290838934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.290838934
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1782383730
Short name T455
Test name
Test status
Simulation time 168776922602 ps
CPU time 389.93 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:43:13 PM PDT 24
Peak memory 201756 kb
Host smart-1ab7da99-74e2-44ec-84ad-2199f9a3d395
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782383730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1782383730
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3575756183
Short name T414
Test name
Test status
Simulation time 169246709492 ps
CPU time 408.92 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:43:33 PM PDT 24
Peak memory 201756 kb
Host smart-728f557c-6706-4d0f-8c0d-5987c5397136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575756183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3575756183
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3881930682
Short name T475
Test name
Test status
Simulation time 330449478556 ps
CPU time 220.15 seconds
Started Mar 12 12:36:42 PM PDT 24
Finished Mar 12 12:40:23 PM PDT 24
Peak memory 201744 kb
Host smart-d749de49-8f77-44bf-8887-4f631612b6ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881930682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3881930682
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3423490182
Short name T515
Test name
Test status
Simulation time 162206965902 ps
CPU time 204.33 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:40:08 PM PDT 24
Peak memory 201884 kb
Host smart-7b4fa0cd-d5a8-4292-93ea-6d5c530a53b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423490182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3423490182
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3984413151
Short name T722
Test name
Test status
Simulation time 495102725054 ps
CPU time 1163.67 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:56:07 PM PDT 24
Peak memory 201868 kb
Host smart-7ef63287-d780-490d-8c8c-7250a57c7e77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984413151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3984413151
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3183807038
Short name T751
Test name
Test status
Simulation time 256413772837 ps
CPU time 606.27 seconds
Started Mar 12 12:36:36 PM PDT 24
Finished Mar 12 12:46:42 PM PDT 24
Peak memory 201856 kb
Host smart-d5c7beba-3793-4704-b138-587c5b5e5719
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183807038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3183807038
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3945939589
Short name T642
Test name
Test status
Simulation time 189790128332 ps
CPU time 450.41 seconds
Started Mar 12 12:36:37 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 201608 kb
Host smart-13c13048-cf3c-455c-8c83-c825c5aece1f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945939589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3945939589
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1583274160
Short name T404
Test name
Test status
Simulation time 120698369568 ps
CPU time 659.48 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:47:43 PM PDT 24
Peak memory 202124 kb
Host smart-2ae10c3f-42aa-4bc8-b0fa-74ad2668d4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583274160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1583274160
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1269013306
Short name T528
Test name
Test status
Simulation time 35498260829 ps
CPU time 20.88 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:37:05 PM PDT 24
Peak memory 201576 kb
Host smart-cb40243c-036c-4920-bf63-e0c775e54262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269013306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1269013306
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3778563646
Short name T333
Test name
Test status
Simulation time 4805635981 ps
CPU time 11.13 seconds
Started Mar 12 12:36:38 PM PDT 24
Finished Mar 12 12:36:49 PM PDT 24
Peak memory 201672 kb
Host smart-77da33d5-cb5e-47b4-94d6-532e213e3ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778563646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3778563646
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.843526562
Short name T335
Test name
Test status
Simulation time 5811561717 ps
CPU time 2.82 seconds
Started Mar 12 12:36:34 PM PDT 24
Finished Mar 12 12:36:37 PM PDT 24
Peak memory 201560 kb
Host smart-80f62e0f-53b2-4c3d-a6f8-f66b276678b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843526562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.843526562
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3929622230
Short name T677
Test name
Test status
Simulation time 339151647444 ps
CPU time 770.22 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 201760 kb
Host smart-441b12f5-975b-4c2a-bffd-8bc73a4c949c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929622230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3929622230
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.846689037
Short name T241
Test name
Test status
Simulation time 97428596256 ps
CPU time 223.65 seconds
Started Mar 12 12:36:43 PM PDT 24
Finished Mar 12 12:40:27 PM PDT 24
Peak memory 210488 kb
Host smart-d7a37e25-2047-4bc5-9622-c0cd9e25fa0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846689037 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.846689037
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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