Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7117	1			T8	55		T9	43		T10	20
testmodes[AdcCtrlTestmodeNormal]	5606	1			T1	1		T4	1		T5	1
testmodes[AdcCtrlTestmodeLowpower]	5748	1			T2	2		T3	12		T7	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3784	1			T8	20		T9	11		T10	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1854	1			T8	17		T9	14		T11	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1357	1			T8	18		T9	18		T15	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1856	1			T8	25		T9	15		T10	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2021	1			T6	2		T8	23		T9	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1416	1			T8	12		T9	20		T10	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1359	1			T8	10		T9	16		T15	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1408	1			T8	20		T9	22		T10	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2725	1			T2	1		T3	11		T7	1