Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22930

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3235

1

T4

25

T6

2

T10

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T3

12

T5

1

T6

1

auto[1]

5557

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T223	11		T224	26		-	-
values[0]	47	1			T158	13		T18	2		T225	11
values[1]	761	1			T5	1		T11	10		T38	15
values[2]	583	1			T6	1		T10	3		T146	7
values[3]	739	1			T26	21		T226	20		T53	22
values[4]	683	1			T47	23		T38	20		T39	3
values[5]	664	1			T6	1		T13	3		T48	2
values[6]	597	1			T4	25		T119	1		T27	9
values[7]	592	1			T10	10		T48	1		T39	1
values[8]	734	1			T1	1		T119	1		T34	11
values[9]	3136	1			T2	17		T6	1		T7	20
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1001	1			T5	1		T11	10		T38	15
values[1]	552	1			T6	1		T10	3		T26	21
values[2]	747	1			T226	20		T53	22		T147	1
values[3]	550	1			T6	1		T39	3		T29	9
values[4]	748	1			T4	25		T13	3		T47	23
values[5]	617	1			T10	10		T119	1		T27	9
values[6]	2790	1			T1	1		T2	17		T7	20
values[7]	613	1			T119	1		T227	1		T41	8
values[8]	790	1			T6	1		T11	3		T12	1
values[9]	159	1			T47	9		T226	12		T228	13
minimum	17598	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T5	1		T38	15		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	6		T146	1		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T10	1		T26	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T144	10		T229	14		T230	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T158	1		T62	3		T193	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T226	20		T53	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	1		T33	1		T226	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T6	1		T39	1		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	1		T38	20		T26	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T4	11		T13	2		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T119	1		T146	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T27	8		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1591	1			T1	1		T2	17		T7	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T34	1		T39	1		T15	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T227	1		T41	2		T17	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T119	1		T154	10		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	3		T12	1		T49	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T6	1		T38	5		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T47	7		T228	11		T155	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T226	12		T175	1		T223	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17461	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T16	8		T231	9		T42	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	4		T146	16		T41	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	2		T26	12		T146	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	10		T229	12		T37	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T158	3		T62	5		T193	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	10		T152	14		T36	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T29	8		T149	11		T61	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T39	2		T150	7		T232	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	12		T200	10		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	14		T13	1		T47	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	11		T148	5		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	9		T27	1		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	832	1			T25	11		T28	16		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T34	10		T15	1		T27	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T41	6		T17	3		T193	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T234	11		T235	5		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T49	9		T237	6		T158	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T17	1		T173	9		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T47	2		T228	2		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T238	7		T239	1		T177	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T223	11		T224	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T158	1		T18	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	1		T38	15		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	6		T146	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T10	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	10		T147	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T26	9		T158	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T226	20		T53	12		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T38	20		T29	1		T226	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T47	13		T39	1		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	1		T26	11		T30	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T13	2		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T119	1		T147	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	11		T27	8		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	1		T30	6		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T39	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T227	1		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T119	1		T34	1		T243	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1754	1			T2	17		T7	20		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	1		T38	5		T226	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T224	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T158	12		T18	1		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T16	8		T241	16		T164	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	4		T146	16		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	2		T146	6		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	10		T152	1		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T26	12		T158	3		T245	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T53	10		T152	14		T36	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	8		T61	9		T62	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T47	10		T39	2		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	12		T149	11		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	1		T169	11		T165	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T148	5		T153	7		T246	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	14		T27	1		T241	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T146	11		T144	8		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T10	9		T15	1		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T242	9		T44	1		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T34	10		T243	6		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T47	2		T49	9		T25	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T17	1		T173	9		T169	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	1		T38	1		T39	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	7		T146	17		T41	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T10	3		T26	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	11		T229	13		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T158	4		T62	6		T193	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T226	1		T53	11		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	9		T33	1		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	1		T39	3		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	1		T38	1		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	15		T13	3		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T119	1		T146	12		T148	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	10		T27	2		T149	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1163	1			T1	1		T2	2		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T34	11		T39	1		T15	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T227	1		T41	8		T17	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T119	1		T154	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T12	1		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T38	1		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T47	3		T228	3		T155	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T226	1		T175	1		T223	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17597	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T38	14		T16	8		T247	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	3		T18	5		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T26	8		T164	6		T248	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T144	9		T229	13		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T62	2		T193	19		T249	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T226	19		T53	11		T152	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T226	11		T61	4		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T150	9		T250	11		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	19		T26	10		T30	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	10		T47	12		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T150	7		T156	3		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T27	7		T153	2		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T2	15		T7	18		T30	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T15	1		T27	6		T243	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T17	4		T162	14		T193	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T154	9		T234	12		T252	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	2		T49	8		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T38	4		T17	1		T173	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T47	6		T228	10		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T226	11		T223	10		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T253	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T223	1		T224	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T158	13		T18	2		T225	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T38	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	7		T146	17		T41	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T10	3		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T144	11		T147	1		T152	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T26	13		T158	4		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T226	1		T53	11		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T38	1		T29	9		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	11		T39	3		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	1		T26	13		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T6	1		T13	3		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T119	1		T147	1		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	15		T27	2		T241	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	1		T30	1		T146	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	10		T39	1		T15	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T227	1		T242	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T119	1		T34	11		T243	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T2	2		T7	2		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T6	1		T38	1		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T223	10		T224	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T254	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T38	14		T16	8		T247	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	3		T18	5		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T42	6		T43	4		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T144	9		T244	10		T256	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	8		T156	2		T245	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T226	19		T53	11		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T38	19		T226	11		T61	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T47	12		T150	9		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T26	10		T30	7		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T169	11		T230	15		T251	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T150	7		T156	3		T233	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	10		T27	7		T153	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	5		T144	4		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	1		T27	6		T155	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T44	2		T156	20		T37	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T243	4		T234	12		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T2	15		T7	18		T11	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T38	4		T226	11		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22974

1

T2

17

T3

12

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3191

1

T1

1

T13

3

T48

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20690

1

T1

1

T3

12

T5

1

auto[1]

5475

1

T2

17

T4

25

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	427	1			T4	25		T47	9		T34	11
values[1]	751	1			T6	1		T10	10		T38	20
values[2]	541	1			T1	1		T5	1		T33	1
values[3]	584	1			T48	1		T119	1		T148	6
values[4]	2686	1			T2	17		T7	20		T48	1
values[5]	611	1			T12	1		T146	17		T42	30
values[6]	725	1			T10	3		T39	3		T30	6
values[7]	580	1			T6	1		T13	3		T49	18
values[8]	646	1			T39	1		T26	21		T144	13
values[9]	1022	1			T6	1		T11	13		T47	23
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T6	1		T10	10		T38	20
values[1]	524	1			T1	1		T5	1		T33	1
values[2]	479	1			T48	1		T119	1		T38	5
values[3]	2850	1			T2	17		T7	20		T12	1
values[4]	604	1			T10	3		T30	6		T226	12
values[5]	629	1			T6	1		T39	3		T29	9
values[6]	637	1			T13	3		T49	18		T231	10
values[7]	658	1			T11	5		T39	1		T26	21
values[8]	1018	1			T4	25		T6	1		T11	5
values[9]	208	1			T11	3		T39	1		T27	9
minimum	17773	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T6	1		T10	1		T17	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T38	20		T26	11		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T33	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T17	3		T249	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	1		T146	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T119	1		T38	5		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T2	17		T7	20		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T38	15		T30	8		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T237	12		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T30	6		T226	12		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T158	1		T193	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	1		T29	1		T226	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	9		T231	1		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	2		T61	5		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	3		T39	1		T144	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T26	9		T149	1		T228	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T4	11		T6	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	1		T34	1		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	3		T27	8		T53	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T39	1		T161	1		T199	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17535	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T258	1		T55	8		T251	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	9		T17	3		T173	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T26	12		T242	9		T245	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T153	3		T164	2		T188	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T17	1		T249	8		T259	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	6		T148	5		T150	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T36	8		T235	18		T260	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	869	1			T25	11		T27	4		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	27		T193	5		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	2		T237	6		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T41	6		T35	10		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T158	12		T193	2		T232	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	2		T29	8		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T49	9		T231	9		T62	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T61	9		T158	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	2		T144	8		T148	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T26	12		T149	9		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	14		T11	2		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T34	10		T15	1		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T27	1		T53	10		T239	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T230	11		T55	3		T261	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T258	2		T55	6		T251	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	11		T47	7		T53	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T34	1		T39	1		T144	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	1		T10	1		T17	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T38	20		T26	11		T226	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T33	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T242	1		T249	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	1		T148	1		T150	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T119	1		T17	3		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T2	17		T7	20		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	20		T30	8		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T42	10		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T146	1		T150	8		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	1		T237	12		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T39	1		T30	6		T226	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	1		T49	9		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	2		T29	1		T226	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	1		T144	5		T247	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	9		T149	1		T61	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	1		T11	9		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T48	1		T15	4		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T4	14		T47	2		T53	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	10		T144	10		T16	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	9		T17	3		T173	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	12		T245	4		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T153	1		T164	2		T188	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T242	9		T249	8		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T148	5		T150	3		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T17	1		T36	8		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	828	1			T25	11		T27	4		T28	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T146	11		T193	5		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T42	20		T169	10		T200	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T146	16		T145	4		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	2		T237	6		T41	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	2		T41	6		T145	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	9		T231	9		T62	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	1		T29	8		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T144	8		T148	7		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	12		T149	9		T61	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	4		T47	10		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	1		T149	6		T153	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3