Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22925

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3240

1

T4

25

T6

3

T10

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20579

1

T3

12

T5

1

T6

2

auto[1]

5586

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	177	1			T6	1		T11	3		T47	9
values[0]	53	1			T158	13		T18	2		T225	11
values[1]	771	1			T5	1		T11	10		T38	15
values[2]	575	1			T6	1		T10	3		T146	7
values[3]	757	1			T26	21		T226	20		T53	22
values[4]	525	1			T6	1		T39	3		T29	9
values[5]	792	1			T13	3		T47	23		T48	2
values[6]	607	1			T4	25		T119	1		T27	9
values[7]	603	1			T10	10		T48	1		T34	11
values[8]	770	1			T1	1		T119	1		T227	1
values[9]	2943	1			T2	17		T7	20		T12	1
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T5	1		T6	1		T11	10
values[1]	547	1			T10	3		T26	21		T146	7
values[2]	784	1			T226	20		T53	22		T147	1
values[3]	542	1			T6	1		T48	1		T39	3
values[4]	748	1			T4	25		T13	3		T47	23
values[5]	626	1			T10	10		T119	1		T27	20
values[6]	2733	1			T1	1		T2	17		T7	20
values[7]	657	1			T119	1		T227	1		T242	10
values[8]	843	1			T6	1		T11	3		T12	1
values[9]	101	1			T47	9		T321	1		T175	1
minimum	17736	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	1		T38	15		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T11	6		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	1		T26	9		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T163	1		T229	14		T230	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T158	1		T62	3		T193	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T226	20		T53	12		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	1		T29	1		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T6	1		T39	1		T150	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T38	20		T26	11		T30	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	11		T13	2		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T119	1		T146	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T27	15		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T1	1		T2	17		T7	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	1		T39	1		T243	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T227	1		T242	1		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T119	1		T154	10		T162	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	3		T12	1		T49	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T6	1		T38	5		T226	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T47	7		T321	1		T322	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T175	1		T223	11		T323	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17512	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T158	1		T18	1		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T146	16		T16	8		T231	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	4		T41	12		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	2		T26	12		T146	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T163	1		T229	12		T37	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	3		T62	5		T193	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T53	10		T193	5		T152	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T29	8		T149	11		T61	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T39	2		T150	7		T232	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T26	12		T200	10		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	14		T13	1		T47	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T146	11		T148	5		T145	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	9		T27	5		T149	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	794	1			T15	1		T25	11		T28	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T34	10		T243	6		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T242	9		T41	6		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T234	11		T236	7		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	9		T237	6		T158	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	1		T173	9		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T47	2		T322	15		T239	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T323	1		T238	7		T177	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T158	12		T18	1		T257	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	3		T47	7		T158	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T6	1		T55	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T158	1		T18	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	1		T38	15		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	6		T41	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	1		T146	1		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	1		T147	1		T244	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T26	9		T158	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T226	20		T53	12		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T29	1		T226	12		T61	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T6	1		T39	1		T150	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T48	1		T38	20		T26	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	2		T47	13		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T119	1		T146	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	11		T27	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	1		T15	4		T30	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T34	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T227	1		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T119	1		T243	5		T154	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T2	17		T7	20		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T38	5		T226	12		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T47	2		T158	9		T229	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T55	1		T177	6		T324	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T158	12		T18	1		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T146	16		T16	8		T231	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	4		T41	12		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	2		T146	6		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T244	10		T163	1		T289	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T26	12		T158	3		T245	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T53	10		T152	14		T36	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	8		T61	9		T62	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T39	2		T150	7		T193	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T26	12		T149	11		T163	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T47	10		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T146	11		T148	5		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	14		T27	1		T241	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	1		T144	8		T149	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	9		T34	10		T27	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T242	9		T17	3		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T243	6		T234	11		T236	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	796	1			T49	9		T25	11		T28	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T17	1		T173	9		T169	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	1		T38	1		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T11	7		T41	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	3		T26	13		T146	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	2		T229	13		T230	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T158	4		T62	6		T193	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T226	1		T53	11		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T48	1		T29	9		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T6	1		T39	3		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T38	1		T26	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	15		T13	3		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T119	1		T146	12		T148	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	10		T27	7		T149	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T1	1		T2	2		T7	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T34	11		T39	1		T243	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T227	1		T242	10		T41	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T119	1		T154	1		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	1		T12	1		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T38	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T47	3		T321	1		T322	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T175	1		T223	1		T323	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17621	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T158	13		T18	2		T257	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T38	14		T16	8		T42	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	3		T18	5		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T26	8		T144	9		T164	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T229	13		T230	5		T250	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T62	2		T193	15		T249	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T226	19		T53	11		T193	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T226	11		T61	4		T228	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T150	9		T250	11		T251	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T38	19		T26	10		T30	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	10		T47	12		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T150	7		T156	3		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	13		T153	2		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T2	15		T7	18		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T243	4		T155	10		T55	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T17	4		T193	10		T156	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T154	9		T162	14		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	2		T49	8		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T38	4		T226	11		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T47	6		T322	16		T239	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T223	10		T238	8		T309	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T247	17		T195	3		T325	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T326	12		T280	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T11	1		T47	3		T158	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T6	1		T55	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T158	13		T18	2		T225	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	1		T38	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	7		T41	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	3		T146	7		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	1		T147	1		T244	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T26	13		T158	4		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T226	1		T53	11		T240	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T29	9		T226	1		T61	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T6	1		T39	3		T150	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	1		T38	1		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	3		T47	11		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T119	1		T146	12		T148	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	15		T27	2		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	1		T15	4		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	10		T34	11		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T227	1		T242	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T119	1		T243	7		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T2	2		T7	2		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T38	1		T226	1		T17	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T11	2		T47	6		T229	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T55	1		T223	10		T309	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T326	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	14		T16	8		T247	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	3		T18	5		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	9		T42	6		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T244	10		T256	2		T289	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	8		T156	2		T245	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T226	19		T53	11		T152	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T226	11		T61	4		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T150	9		T193	4		T250	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	19		T26	10		T30	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	12		T169	11		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T150	7		T156	3		T199	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	10		T27	7		T153	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T15	1		T30	5		T144	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	6		T155	10		T55	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	4		T44	2		T156	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T243	4		T154	9		T234	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T2	15		T7	18		T49	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T38	4		T226	11		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18