Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23135

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3030

1

T6

1

T10

10

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20402

1

T1

1

T3

12

T6

1

auto[1]

5763

1

T2

17

T4

25

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T119	1		T38	5		T39	1
values[0]	2	1			T107	1		T327	1		-	-
values[1]	527	1			T5	1		T10	3		T12	1
values[2]	696	1			T6	1		T47	23		T29	9
values[3]	521	1			T47	9		T48	1		T119	1
values[4]	647	1			T226	12		T227	1		T149	22
values[5]	2665	1			T2	17		T4	25		T7	20
values[6]	709	1			T1	1		T6	1		T15	5
values[7]	785	1			T11	3		T26	21		T33	1
values[8]	662	1			T6	1		T11	5		T38	20
values[9]	1106	1			T10	10		T11	5		T13	3
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	705	1			T12	1		T47	23		T48	1
values[1]	665	1			T6	1		T47	9		T48	1
values[2]	517	1			T34	11		T39	1		T147	1
values[3]	2642	1			T2	17		T7	20		T50	2
values[4]	590	1			T4	25		T6	1		T38	15
values[5]	657	1			T1	1		T26	21		T146	7
values[6]	915	1			T11	8		T26	23		T33	1
values[7]	667	1			T6	1		T10	10		T48	1
values[8]	1035	1			T11	5		T13	3		T49	18
values[9]	110	1			T119	1		T38	5		T159	1
minimum	17662	1			T3	12		T5	1		T8	154

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T48	1		T30	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	13		T30	8		T61	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	1		T41	1		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T47	7		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	1		T147	1		T244	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T34	1		T193	11		T229	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1588	1			T2	17		T7	20		T50	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T227	1		T149	1		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	11		T15	4		T27	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	1		T38	15		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T1	1		T146	1		T226	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T26	9		T40	3		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	6		T26	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T226	12		T148	1		T193	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	1		T48	1		T38	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T53	12		T229	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	3		T27	8		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T13	2		T49	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T119	1		T38	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T163	12		T199	3		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17481	1			T3	12		T5	1		T8	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T156	4		T36	10		T250	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T242	9		T237	6		T41	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T47	10		T61	9		T158	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T41	12		T17	1		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	2		T29	8		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T244	10		T289	7		T255	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T34	10		T193	2		T229	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	828	1			T25	11		T28	16		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T149	11		T42	20		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	14		T15	1		T27	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	2		T16	8		T235	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	6		T144	10		T158	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T26	12		T228	2		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	2		T26	12		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	7		T193	11		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	7		T232	3		T152	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	9		T53	10		T229	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	2		T27	1		T146	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T13	1		T49	9		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T21	2		T328	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T163	10		T290	9		T329	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	2		T11	2		T13	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T36	8		T330	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T119	1		T38	5		T146	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T39	1		T199	3		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T327	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T107	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T10	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T61	5		T158	1		T156	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	1		T30	6		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	13		T29	1		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T39	1		T147	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	7		T48	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T226	12		T149	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T227	1		T149	1		T42	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	17		T4	11		T7	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T38	15		T39	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	1		T15	4		T226	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T43	1		T228	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	3		T33	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	9		T226	12		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	1		T11	3		T38	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T53	12		T148	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T11	3		T48	1		T27	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T10	1		T13	2		T49	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T146	16		T152	1		T153	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T252	16		T331	9		T290	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	2		T41	6		T158	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T61	9		T158	12		T36	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T242	9		T237	6		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T47	10		T29	8		T249	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	12		T169	11		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	2		T34	10		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	9		T148	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T149	11		T42	20		T193	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	834	1			T4	14		T25	11		T27	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T39	2		T16	8		T145	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T15	1		T231	9		T158	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T228	2		T193	11		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T146	6		T144	10		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	12		T165	7		T234	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	2		T26	12		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T53	10		T148	7		T164	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	2		T27	1		T149	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	9		T13	1		T49	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	1		T48	1		T30	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T47	11		T30	1		T61	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	1		T41	13		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	3		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	1		T147	1		T244	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T34	11		T193	3		T229	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T2	2		T7	2		T50	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T227	1		T149	12		T42	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	15		T15	4		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T38	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T146	7		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T26	13		T40	3		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	4		T26	13		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T226	1		T148	8		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	1		T48	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	10		T53	11		T229	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	4		T27	2		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T13	3		T49	10		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T119	1		T38	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T163	11		T199	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17610	1			T3	12		T5	1		T8	154
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T156	1		T36	9		T250	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	5		T237	11		T150	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	12		T30	7		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T17	1		T169	11		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	6		T17	4		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T244	10		T199	6		T289	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T193	10		T229	9		T55	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T2	15		T7	18		T31	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T42	6		T44	2		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T4	10		T15	1		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	14		T16	8		T156	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T226	19		T144	9		T247	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T26	8		T228	10		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	4		T26	10		T144	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T226	11		T193	15		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	19		T155	9		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T53	11		T229	13		T230	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T27	7		T173	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T49	8		T169	9		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T38	4		T21	3		T328	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T163	11		T199	2		T189	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T332	16		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T156	3		T36	9		T250	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T119	1		T38	1		T146	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T39	1		T199	1		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T327	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T107	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T10	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T61	10		T158	13		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	1		T30	1		T242	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	11		T29	9		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	1		T147	1		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	3		T48	1		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T226	1		T149	10		T148	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T227	1		T149	12		T42	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T2	2		T4	15		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T38	1		T39	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	1		T15	4		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	1		T43	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	1		T33	1		T146	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T26	13		T226	1		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	1		T11	3		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	11		T148	8		T164	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	4		T48	1		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T10	10		T13	3		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T38	4		T153	2		T305	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T199	2		T189	3		T252	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T150	5		T252	13		T201	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T61	4		T156	3		T36	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T30	5		T237	11		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	12		T30	7		T249	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T169	11		T244	10		T199	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T47	6		T17	4		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T226	11		T43	4		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	6		T193	10		T44	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T2	15		T4	10		T7	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	14		T16	8		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T15	1		T226	19		T247	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T228	10		T193	15		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	2		T144	9		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T26	8		T226	11		T234	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	2		T38	19		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T53	11		T229	13		T230	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	1		T27	7		T173	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T49	8		T169	9		T162	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18