Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22855

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3310

1

T4

25

T6

3

T10

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20558

1

T3

12

T5

1

T6

2

auto[1]

5607

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T334	14		T335	1		T217	13
values[0]	24	1			T285	13		T336	11		-	-
values[1]	805	1			T48	1		T38	15		T30	8
values[2]	795	1			T13	3		T34	11		T38	5
values[3]	615	1			T6	1		T39	1		T26	44
values[4]	546	1			T6	1		T10	10		T11	3
values[5]	2949	1			T2	17		T7	20		T11	10
values[6]	708	1			T231	10		T147	1		T42	30
values[7]	387	1			T1	1		T4	25		T5	1
values[8]	671	1			T29	9		T146	29		T148	6
values[9]	1045	1			T6	1		T10	3		T47	9
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1055	1			T13	3		T48	1		T34	11
values[1]	715	1			T6	1		T27	11		T226	20
values[2]	592	1			T6	1		T47	23		T39	2
values[3]	2731	1			T2	17		T7	20		T10	10
values[4]	709	1			T11	10		T15	5		T226	12
values[5]	712	1			T4	25		T119	1		T38	20
values[6]	445	1			T1	1		T5	1		T48	1
values[7]	612	1			T29	9		T33	1		T149	12
values[8]	812	1			T6	1		T10	3		T49	18
values[9]	184	1			T47	9		T145	9		T156	21
minimum	17598	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T38	5		T33	1		T61	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T13	2		T48	1		T34	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T27	7		T226	20		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	1		T53	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	1		T26	20		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T47	13		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1603	1			T2	17		T7	20		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	3		T48	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	3		T43	1		T228	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	3		T15	4		T226	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T119	1		T243	5		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	11		T38	20		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T1	1		T5	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T146	1		T159	1		T145	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T161	1		T199	7		T164	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T29	1		T33	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T39	1		T30	6		T62	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T10	1		T49	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T47	7		T156	21		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T145	5		T175	1		T168	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17458	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T156	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T61	9		T41	6		T241	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	1		T34	10		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	4		T41	12		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T53	10		T43	4		T241	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T26	24		T27	1		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T47	10		T148	7		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T10	9		T25	11		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T146	6		T242	9		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	2		T228	2		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	2		T15	1		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T243	6		T155	7		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	14		T144	10		T42	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	11		T144	8		T231	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T146	16		T145	1		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T164	11		T167	3		T235	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T29	8		T149	11		T237	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	2		T62	5		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	2		T49	9		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T47	2		T271	13		T312	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T145	4		T104	5		T337	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T335	1		T217	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T334	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T336	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T285	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T61	5		T41	2		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	1		T38	15		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T38	5		T27	7		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T34	1		T226	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T26	20		T227	1		T169	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T39	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	1		T39	1		T27	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	1		T11	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T2	17		T7	20		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	3		T38	20		T15	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T231	1		T228	11		T243	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T147	1		T42	10		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T1	1		T5	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	11		T33	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	1		T148	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	1		T146	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T47	7		T39	1		T30	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T6	1		T10	1		T49	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T217	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T334	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T336	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T61	9		T41	6		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T193	7		T262	12		T263	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	4		T41	12		T241	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	1		T34	10		T149	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T26	24		T169	10		T165	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	7		T43	4		T241	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	9		T27	1		T158	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T47	10		T242	9		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	868	1			T11	2		T25	11		T28	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	2		T15	1		T146	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	9		T228	2		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T42	20		T228	7		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T144	8		T17	3		T286	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T4	14		T144	10		T237	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T146	11		T148	5		T167	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	8		T146	16		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T47	2		T39	2		T62	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	2		T49	9		T149	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T38	1		T33	1		T61	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	3		T48	1		T34	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T27	5		T226	1		T41	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	1		T53	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T39	1		T26	26		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T47	11		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T2	2		T7	2		T10	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T48	1		T146	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	4		T43	1		T228	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	3		T15	4		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T119	1		T243	7		T155	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	15		T38	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T5	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T146	17		T159	1		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T161	1		T199	1		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	9		T33	1		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T39	3		T30	1		T62	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T6	1		T10	3		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T47	3		T156	1		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T145	7		T175	1		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17594	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T156	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T38	4		T61	4		T162	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T38	14		T30	7		T247	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T27	6		T226	19		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T53	11		T43	4		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T26	18		T27	7		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	12		T226	11		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T2	15		T7	18		T31	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	2		T245	6		T255	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T228	10		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T15	1		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T243	4		T155	9		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	10		T38	19		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T144	4		T17	4		T189	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T199	2		T164	6		T338	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T199	6		T164	12		T194	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T237	11		T17	1		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T30	5		T62	2		T193	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T49	8		T155	10		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T47	6		T156	20		T271	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T145	2		T168	5		T319	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T156	3		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T335	1		T217	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T334	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T336	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T61	10		T41	8		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	1		T38	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T38	1		T27	5		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	3		T34	11		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T26	26		T227	1		T169	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T39	1		T148	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	10		T39	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T6	1		T11	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T2	2		T7	2		T11	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	3		T38	1		T15	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T231	10		T228	3		T243	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	1		T42	24		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T1	1		T5	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	15		T33	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T146	12		T148	6		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T29	9		T146	17		T158	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T47	3		T39	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	1		T10	3		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T217	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T334	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T336	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T61	4		T256	2		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T38	14		T30	7		T193	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T38	4		T27	6		T226	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T226	11		T247	17		T53	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T26	18		T169	9		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T43	4		T44	2		T245	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T27	7		T173	15		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	2		T47	12		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T2	15		T7	18		T11	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	2		T38	19		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T228	10		T243	4		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T42	6		T228	7		T18	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T144	4		T17	4		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	10		T144	9		T237	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T199	6		T189	3		T266	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	11		T152	11		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T47	6		T30	5		T62	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	8		T17	1		T155	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18