Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22865

1

T2

17

T3

12

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3300

1

T1

1

T5

1

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20478

1

T3

12

T4

25

T6

2

auto[1]

5687

1

T1

1

T2

17

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	663	1			T6	1		T8	2		T9	1
values[0]	36	1			T267	8		T268	6		T269	22
values[1]	571	1			T6	1		T47	23		T38	15
values[2]	2817	1			T2	17		T6	1		T7	20
values[3]	518	1			T11	5		T17	11		T62	8
values[4]	792	1			T4	25		T10	3		T48	2
values[5]	523	1			T5	1		T11	5		T29	9
values[6]	684	1			T47	9		T119	1		T39	4
values[7]	755	1			T10	10		T12	1		T48	1
values[8]	469	1			T13	3		T247	18		T40	3
values[9]	1193	1			T1	1		T49	18		T119	1
minimum	17144	1			T3	12		T8	152		T9	149

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	579	1			T6	2		T47	23		T38	15
values[1]	2847	1			T2	17		T7	20		T11	8
values[2]	512	1			T38	20		T226	12		T62	8
values[3]	673	1			T4	25		T10	3		T48	1
values[4]	706	1			T5	1		T11	5		T48	1
values[5]	672	1			T47	9		T119	1		T39	4
values[6]	721	1			T10	10		T12	1		T48	1
values[7]	535	1			T13	3		T146	12		T17	4
values[8]	1024	1			T1	1		T49	18		T119	1
values[9]	132	1			T6	1		T41	8		T145	3
minimum	17764	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T33	1		T226	20		T144	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	2		T47	13		T38	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1637	1			T2	17		T7	20		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	6		T146	1		T16	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	20		T44	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T226	12		T62	3		T150	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	11		T48	1		T26	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T26	11		T27	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	1		T29	1		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T11	3		T42	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T39	1		T226	12		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	7		T119	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	1		T48	1		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T247	18		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	2		T150	6		T164	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T146	1		T17	3		T248	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T34	1		T38	5		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T1	1		T49	9		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T66	7		T339	10		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T6	1		T41	2		T145	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17500	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T163	1		T340	1		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T144	8		T158	9		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	10		T193	2		T245	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	834	1			T25	11		T28	16		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	2		T146	16		T16	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T165	5		T167	3		T171	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T62	5		T35	10		T235	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	14		T26	12		T146	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	2		T26	12		T27	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	8		T148	7		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	2		T42	20		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T39	2		T149	6		T155	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	2		T15	1		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	9		T243	6		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T43	4		T36	8		T19	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	1		T150	3		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T146	11		T17	1		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T34	10		T144	10		T149	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T49	9		T27	1		T61	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T66	5		T339	5		T239	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T41	6		T145	1		T178	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T163	1		T277	10		T341	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	544	1			T8	2		T9	1		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T6	1		T165	1		T250	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T268	1		T269	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T33	1		T226	20		T144	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T47	13		T38	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T2	17		T7	20		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T6	1		T11	3		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	8		T169	12		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	3		T62	3		T150	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	11		T48	2		T38	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	1		T26	11		T27	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T29	1		T146	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	1		T11	3		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	1		T30	6		T226	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T47	7		T119	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	1		T48	1		T243	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	1		T15	4		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	2		T40	3		T150	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T247	18		T17	3		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T34	1		T38	5		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T1	1		T49	9		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T3	12		T8	152		T9	149
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T53	10		T18	4		T236	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T165	7		T21	3		T283	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T267	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T268	5		T269	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	8		T296	10		T278	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	10		T163	1		T200	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	847	1			T25	11		T28	16		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T146	16		T16	8		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	3		T169	11		T152	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T11	2		T62	5		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	14		T26	12		T232	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	2		T26	12		T27	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T29	8		T146	6		T149	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	2		T242	9		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	2		T148	7		T228	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	2		T231	9		T42	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	9		T243	6		T153	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T149	9		T43	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	1		T150	3		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T17	1		T235	5		T37	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T34	10		T144	10		T149	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T49	9		T27	1		T146	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	1		T226	1		T144	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	2		T47	11		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T2	2		T7	2		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	5		T146	17		T16	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T38	1		T44	1		T165	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T226	1		T62	6		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	15		T48	1		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T10	3		T26	13		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	1		T29	9		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	1		T11	3		T42	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T39	3		T226	1		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	3		T119	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	10		T48	1		T40	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T247	1		T43	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	3		T150	4		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T146	12		T17	3		T248	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T34	11		T38	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	1		T49	10		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T66	10		T339	6		T239	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T6	1		T41	8		T145	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17649	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T163	2		T340	1		T277	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T226	19		T144	4		T244	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	12		T38	14		T30	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T2	15		T7	18		T31	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	3		T16	8		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	19		T171	17		T201	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T226	11		T62	2		T150	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T4	10		T26	8		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T26	10		T27	6		T255	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	5		T228	10		T245	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	2		T42	6		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T226	11		T155	9		T156	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	6		T15	1		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T243	4		T162	14		T193	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T247	17		T43	4		T36	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T150	5		T164	6		T230	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	1		T248	13		T262	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T38	4		T144	9		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T49	8		T27	7		T61	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T66	2		T339	9		T267	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T230	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T342	19		T239	1		T315	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T196	14		T309	12		T273	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	530	1			T8	2		T9	1		T13	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T6	1		T165	8		T250	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T267	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T268	6		T269	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T33	1		T226	1		T144	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	1		T47	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T2	2		T7	2		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	1		T11	1		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	7		T169	12		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	4		T62	6		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	15		T48	2		T38	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T10	3		T26	13		T27	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T29	9		T146	7		T149	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	1		T11	3		T242	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	3		T30	1		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	3		T119	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	10		T48	1		T243	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	1		T15	4		T149	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	3		T40	3		T150	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T247	1		T17	3		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	367	1			T34	11		T38	1		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T1	1		T49	10		T119	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17144	1			T3	12		T8	152		T9	149
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T53	11		T18	5		T66	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T250	7		T21	3		T283	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T269	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T226	19		T144	4		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	12		T38	14		T199	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T2	15		T7	18		T31	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	2		T30	7		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	4		T169	11		T244	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	1		T62	2		T150	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	10		T38	19		T26	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	10		T27	6		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T245	17		T270	11		T252	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	2		T154	9		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T30	5		T226	11		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	6		T42	6		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T243	4		T162	14		T156	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	1		T43	4		T36	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T150	5		T193	15		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T247	17		T17	1		T248	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T38	4		T144	9		T193	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T49	8		T27	7		T61	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18