Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22954

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3211

1

T6

1

T10

10

T11

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20631

1

T3

12

T4

25

T6

1

auto[1]

5534

1

T1

1

T2

17

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	216	1			T4	25		T249	13		T18	2
values[0]	43	1			T39	1		T61	14		T179	28
values[1]	707	1			T48	1		T39	3		T26	21
values[2]	663	1			T6	1		T11	5		T47	9
values[3]	637	1			T27	9		T16	21		T237	18
values[4]	649	1			T48	1		T34	11		T27	11
values[5]	530	1			T10	10		T11	3		T38	20
values[6]	669	1			T5	1		T6	1		T10	3
values[7]	925	1			T12	1		T49	18		T119	1
values[8]	2548	1			T2	17		T7	20		T13	3
values[9]	986	1			T1	1		T6	1		T11	5
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T48	1		T39	4		T15	5
values[1]	660	1			T6	1		T11	5		T47	9
values[2]	569	1			T48	1		T27	9		T16	21
values[3]	716	1			T34	11		T27	11		T144	20
values[4]	495	1			T5	1		T10	13		T11	3
values[5]	814	1			T6	1		T33	1		T243	11
values[6]	2767	1			T2	17		T7	20		T49	18
values[7]	647	1			T12	1		T13	3		T146	12
values[8]	848	1			T1	1		T6	1		T11	5
values[9]	122	1			T4	25		T18	2		T200	11
minimum	17858	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T39	1		T33	1		T226	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	1		T39	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	1		T11	3		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	7		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T27	8		T16	13		T43	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T48	1		T17	3		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	7		T247	18		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T34	1		T144	10		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T10	1		T11	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	1		T39	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T33	1		T243	5		T155	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T152	1		T245	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T2	17		T7	20		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T49	9		T119	1		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	1		T173	16		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	2		T146	1		T144	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	1		T6	1		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	3		T149	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T4	11		T200	1		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T18	1		T305	10		T298	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17522	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T146	1		T61	5		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	2		T241	1		T150	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	1		T148	5		T44	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	2		T29	8		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T47	2		T26	12		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T27	1		T16	8		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	1		T42	20		T62	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	4		T237	6		T18	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	10		T144	10		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	2		T41	6		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T10	9		T146	16		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T243	6		T155	11		T145	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T152	1		T245	17		T229	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	802	1			T25	11		T28	16		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	9		T53	10		T158	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T173	9		T152	1		T296	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	1		T146	11		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	10		T155	7		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	2		T149	15		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T4	14		T200	10		T307	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T18	1		T305	11		T298	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T146	6		T61	9		T188	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T4	11		T249	5		T307	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T18	1		T189	4		T331	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T179	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T39	1		T61	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T39	1		T26	9		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	1		T146	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	1		T11	3		T29	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	7		T48	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T27	8		T16	13		T237	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T17	3		T42	10		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	7		T247	18		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T48	1		T34	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	3		T38	20		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T10	1		T39	1		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T10	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T146	1		T245	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T30	6		T226	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T49	9		T119	1		T30	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T2	17		T7	20		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	2		T146	1		T17	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T6	1		T47	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T11	3		T144	5		T149	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T4	14		T249	8		T307	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T18	1		T331	9		T305	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T179	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T61	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	2		T26	12		T241	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T146	6		T148	5		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	2		T29	8		T169	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T47	2		T15	1		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T27	1		T16	8		T237	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	1		T42	20		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	4		T153	7		T258	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T34	10		T41	12		T62	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T41	6		T18	4		T245	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T10	9		T144	10		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	2		T243	6		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T146	16		T245	17		T229	27
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T148	7		T152	14		T153	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	9		T53	10		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	780	1			T25	11		T28	16		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	1		T146	11		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	10		T155	7		T200	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T11	2		T144	8		T149	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T39	3		T33	1		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	1		T39	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T11	4		T29	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	3		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	2		T16	13		T43	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	1		T17	3		T42	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T27	5		T247	1		T237	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T34	11		T144	11		T41	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T5	1		T10	3		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T10	10		T39	1		T146	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T33	1		T243	7		T155	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	1		T152	2		T245	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T2	2		T7	2		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	10		T119	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T173	10		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	3		T146	12		T144	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T6	1		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	3		T149	17		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T4	15		T200	11		T307	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T18	2		T305	12		T298	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17701	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T146	7		T61	10		T188	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T226	11		T162	14		T150	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T15	1		T44	2		T156	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	1		T169	9		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T47	6		T26	10		T226	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	7		T16	8		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T17	1		T42	6		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T27	6		T247	17		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	9		T228	7		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	2		T38	23		T162	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T199	12		T201	17		T333	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T243	4		T155	10		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T245	17		T229	9		T255	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T2	15		T7	18		T30	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T49	8		T30	7		T53	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T173	15		T270	11		T297	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T144	4		T17	4		T36	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	12		T38	14		T154	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	2		T169	11		T193	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T4	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T305	9		T298	6		T275	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T26	8		T241	9		T153	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T61	4		T311	11		T343	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T4	15		T249	9		T307	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T18	2		T189	1		T331	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T179	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T39	1		T61	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T39	3		T26	13		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	1		T146	7		T148	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	1		T11	4		T29	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	3		T48	1		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T27	2		T16	13		T237	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T17	3		T42	24		T164	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T27	5		T247	1		T153	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T48	1		T34	11		T41	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	1		T38	1		T41	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	10		T39	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	1		T10	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T146	17		T245	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	1		T30	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T49	10		T119	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T2	2		T7	2		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	3		T146	12		T17	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	1		T6	1		T47	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T11	3		T144	9		T149	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T4	10		T249	4		T338	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T189	3		T331	10		T305	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T179	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T61	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T26	8		T226	11		T241	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	2		T156	20		T257	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	1		T169	9		T162	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	6		T15	1		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T27	7		T16	8		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T17	1		T42	6		T302	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T27	6		T247	17		T270	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T62	2		T176	1		T265	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	2		T38	19		T162	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	9		T228	7		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	4		T243	4		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T245	17		T229	22		T255	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	5		T226	11		T156	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T49	8		T30	7		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T2	15		T7	18		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T17	4		T171	9		T37	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	12		T38	14		T154	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	2		T144	4		T169	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18