Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20614

1

T3

12

T4

25

T6

2

auto[ADC_CTRL_FILTER_COND_OUT]

5551

1

T1

1

T2

17

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20547

1

T3

12

T4

25

T6

2

auto[1]

5618

1

T1

1

T2

17

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T39	1		T162	10		T244	3
values[0]	94	1			T118	13		T318	19		T254	21
values[1]	769	1			T29	9		T146	7		T144	13
values[2]	655	1			T10	3		T13	3		T48	1
values[3]	659	1			T11	5		T47	23		T48	1
values[4]	681	1			T4	25		T6	1		T27	11
values[5]	652	1			T12	1		T119	1		T33	1
values[6]	621	1			T119	1		T39	1		T247	18
values[7]	657	1			T47	9		T48	1		T38	20
values[8]	481	1			T6	1		T11	3		T49	18
values[9]	3040	1			T1	1		T2	17		T5	1
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	805	1			T48	1		T38	15		T39	3
values[1]	2662	1			T2	17		T7	20		T10	3
values[2]	652	1			T6	1		T47	23		T48	1
values[3]	697	1			T4	25		T27	11		T226	12
values[4]	682	1			T12	1		T119	1		T39	1
values[5]	641	1			T119	1		T38	20		T247	18
values[6]	580	1			T47	9		T48	1		T26	21
values[7]	566	1			T6	1		T11	8		T49	18
values[8]	859	1			T1	1		T5	1		T6	1
values[9]	176	1			T39	1		T244	21		T262	26
minimum	17845	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T38	15		T39	1		T193	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	1		T15	4		T29	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	3		T144	10		T61	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1544	1			T2	17		T7	20		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T146	1		T226	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T47	13		T48	1		T62	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	11		T41	2		T249	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	7		T226	12		T173	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T119	1		T39	1		T16	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	1		T33	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T119	1		T38	20		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T247	18		T147	1		T42	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T47	7		T26	9		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	1		T159	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	1		T11	3		T49	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	3		T149	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T30	6		T33	1		T226	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	1		T5	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T262	14		T317	9		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T39	1		T244	11		T318	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17544	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T161	1		T66	7		T341	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	2		T193	5		T152	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	1		T29	8		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T144	10		T61	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	813	1			T10	2		T13	1		T25	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T146	16		T158	9		T145	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	10		T62	5		T150	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	14		T41	6		T249	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T27	4		T173	9		T241	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	8		T148	12		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T146	11		T169	10		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	1		T307	4		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T42	20		T228	7		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T47	2		T26	12		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T145	1		T301	14		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	2		T49	9		T41	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T149	20		T158	3		T163	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T149	6		T231	9		T243	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	9		T34	10		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T262	12		T317	15		T344	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T244	10		T318	8		T309	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T66	5		T341	6		T292	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T162	10		T200	1		T302	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T39	1		T244	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T318	11		T254	10		T345	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T118	1		T346	3		T319	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T146	1		T144	5		T53	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T29	1		T17	8		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T38	15		T39	1		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	1		T13	2		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	3		T146	1		T226	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	13		T48	1		T150	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	11		T6	1		T41	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T27	7		T226	12		T62	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	1		T16	13		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T33	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T119	1		T39	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T247	18		T42	10		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	7		T38	20		T26	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	1		T147	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T49	9		T30	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	3		T149	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	3		T30	6		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1735	1			T1	1		T2	17		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T200	10		T262	12		T176	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T318	8		T316	13		T309	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T318	8		T254	11		T345	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T118	12		T346	2		T319	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T146	6		T144	8		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	8		T17	3		T152	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T39	2		T144	10		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T10	2		T13	1		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	2		T146	16		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T47	10		T150	3		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	14		T41	6		T249	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	4		T62	5		T173	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	8		T148	5		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T146	11		T241	1		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T148	7		T17	1		T307	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T42	20		T228	7		T169	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	2		T26	12		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T155	11		T145	1		T301	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T49	9		T41	12		T255	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	11		T158	3		T261	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	2		T149	6		T231	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	922	1			T10	9		T34	10		T25	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	1		T39	3		T193	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	1		T15	4		T29	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	4		T144	11		T61	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1139	1			T2	2		T7	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	1		T146	17		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	11		T48	1		T62	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	15		T41	8		T249	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T27	5		T226	1		T173	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T119	1		T39	1		T16	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T33	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T119	1		T38	1		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T247	1		T147	1		T42	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T47	3		T26	13		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	1		T159	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T11	3		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	1		T149	22		T158	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	1		T33	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	1		T5	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T262	13		T317	16		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	1		T244	11		T318	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T161	1		T66	10		T341	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T38	14		T193	4		T289	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	1		T17	4		T150	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T144	9		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1218	1			T2	15		T7	18		T26	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T226	19		T145	2		T18	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T47	12		T62	2		T150	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	10		T249	4		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	6		T226	11		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	8		T256	2		T245	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T169	9		T193	15		T36	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	19		T17	1		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T247	17		T42	6		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T47	6		T26	8		T30	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T301	10		T233	14		T252	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	2		T49	8		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	2		T199	12		T245	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	5		T226	11		T243	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T38	4		T155	9		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T262	13		T317	8		T347	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T244	10		T318	11		T309	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T144	4		T53	11		T237	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T66	2		T292	8		T320	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T162	1		T200	11		T302	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T39	1		T244	1		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T318	9		T254	12		T345	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T118	13		T346	3		T319	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T146	7		T144	9		T53	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	9		T17	7		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T38	1		T39	3		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	3		T13	3		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	4		T146	17		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T47	11		T48	1		T150	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	15		T6	1		T41	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	5		T226	1		T62	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T119	1		T16	13		T40	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T33	1		T146	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	1		T39	1		T148	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T247	1		T42	24		T228	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	3		T38	1		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	1		T147	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T49	10		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	1		T149	12		T158	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	3		T30	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T1	1		T2	2		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T162	9		T302	2		T262	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T244	2		T318	11		T325	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T318	10		T254	9		T345	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T346	2		T319	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T144	4		T53	11		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T17	4		T152	11		T281	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	14		T144	9		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	1		T26	10		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	1		T226	19		T145	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	12		T150	5		T164	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	10		T249	4		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	6		T226	11		T62	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	8		T245	6		T230	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T193	15		T36	9		T229	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T17	1		T154	9		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T247	17		T42	6		T228	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	6		T38	19		T26	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T155	10		T301	10		T233	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	8		T30	7		T156	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T11	2		T199	12		T261	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	2		T30	5		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1385	1			T2	15		T7	18		T38	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18