Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	1		T10	10		T17	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T38	1		T26	13		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	1		T33	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	1		T17	3		T249	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	1		T146	7		T148	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T119	1		T38	1		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1199	1			T2	2		T7	2		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T38	1		T30	1		T146	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	3		T237	7		T41	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	1		T226	1		T41	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T158	13		T193	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T39	3		T29	9		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T49	10		T231	10		T62	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	3		T61	10		T158	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	3		T39	1		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	13		T149	10		T228	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T4	15		T6	1		T11	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	1		T34	11		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T11	1		T27	2		T53	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T39	1		T161	1		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17652	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T258	3		T55	10		T251	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T17	4		T173	15		T162	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T38	19		T26	10		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T153	2		T164	6		T201	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	1		T249	4		T262	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T150	5		T55	1		T201	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T38	4		T36	9		T199	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T2	15		T7	18		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T38	14		T30	7		T193	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T237	11		T37	10		T263	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	5		T226	11		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T193	10		T264	3		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T226	19		T162	14		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	8		T62	2		T245	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T61	4		T18	5		T252	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T144	4		T247	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	8		T228	10		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	10		T11	1		T47	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T144	9		T16	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T11	2		T27	7		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T199	2		T230	15		T55	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T169	11		T155	9		T248	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T55	4		T251	6		T265	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	15		T47	3		T53	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T34	11		T39	1		T144	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	1		T10	10		T17	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	1		T26	13		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T33	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T242	10		T249	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	1		T148	6		T150	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T119	1		T17	3		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T2	2		T7	2		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	2		T30	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T42	24		T169	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T146	17		T150	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	3		T237	7		T41	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	3		T30	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T49	10		T231	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	3		T29	9		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T39	1		T144	9		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	13		T149	10		T61	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	1		T11	8		T47	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T48	1		T15	4		T33	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	10		T47	6		T53	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T144	9		T16	8		T43	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T17	4		T173	15		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	19		T26	10		T226	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T164	6		T201	30		T266	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T249	4		T229	13		T233	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T150	5		T153	2		T55	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T17	1		T36	9		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T2	15		T7	18		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	18		T30	7		T193	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T42	6		T169	9		T37	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T150	7		T145	2		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T237	11		T193	10		T171	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T30	5		T226	11		T162	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T49	8		T62	2		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T226	19		T156	3		T18	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T144	4		T247	17		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T26	8		T61	4		T228	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	5		T47	12		T27	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T15	1		T154	9		T156	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18