Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22769

1

T2

17

T3

12

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

3396

1

T1

1

T4

25

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20750

1

T3

12

T6

2

T8

152

auto[1]

5415

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	522	1			T8	2		T9	1		T13	2
values[0]	56	1			T267	8		T268	6		T269	22
values[1]	577	1			T6	1		T47	23		T38	15
values[2]	2797	1			T2	17		T6	1		T7	20
values[3]	521	1			T11	5		T147	1		T17	11
values[4]	698	1			T4	25		T10	3		T48	2
values[5]	541	1			T5	1		T11	5		T26	21
values[6]	771	1			T47	9		T119	1		T39	4
values[7]	705	1			T10	10		T12	1		T48	1
values[8]	515	1			T13	3		T247	18		T40	3
values[9]	1318	1			T1	1		T6	1		T49	18
minimum	17144	1			T3	12		T8	152		T9	149

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	799	1			T6	1		T47	23		T38	15
values[1]	2773	1			T2	17		T6	1		T7	20
values[2]	561	1			T38	20		T226	12		T17	11
values[3]	655	1			T4	25		T10	3		T48	2
values[4]	692	1			T5	1		T11	5		T39	3
values[5]	739	1			T47	9		T119	1		T39	1
values[6]	628	1			T10	10		T12	1		T48	1
values[7]	588	1			T1	1		T13	3		T17	4
values[8]	954	1			T49	18		T119	1		T34	11
values[9]	184	1			T6	1		T41	8		T150	17
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T33	1		T158	1		T193	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T47	13		T38	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T2	17		T7	20		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	1		T11	6		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	20		T17	8		T150	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T226	12		T62	3		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T48	1		T26	9		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T4	11		T10	1		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	3		T29	1		T30	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T39	1		T42	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T47	7		T39	1		T226	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T119	1		T15	4		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T10	1		T12	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T247	18		T40	3		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	2		T150	6		T164	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T17	3		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T34	1		T38	5		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T49	9		T119	1		T27	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T150	10		T230	7		T270	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T6	1		T41	2		T230	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	9		T193	2		T249	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	10		T144	8		T163	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	788	1			T25	11		T28	16		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	2		T146	16		T16	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T17	3		T200	13		T165	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T62	5		T35	10		T235	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T26	12		T146	6		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	14		T10	2		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	2		T29	8		T149	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	2		T42	20		T228	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T47	2		T149	9		T155	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	1		T231	9		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	9		T43	4		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	8		T153	7		T271	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T150	3		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T17	1		T163	1		T230	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T34	10		T144	10		T53	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T49	9		T27	1		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T150	7		T270	14		T263	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T41	6		T178	12		T272	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T8	2		T9	1		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	1		T269	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T268	1		T273	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T33	1		T244	3		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	1		T47	13		T38	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T2	17		T7	20		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T11	3		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T147	1		T17	8		T169	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T11	3		T62	3		T44	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T48	1		T38	20		T29	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	11		T10	1		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	3		T26	9		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T242	1		T154	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T47	7		T39	1		T30	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T119	1		T39	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T10	1		T12	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	4		T161	1		T156	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	2		T43	8		T150	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T247	18		T40	3		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T34	1		T38	5		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T1	1		T6	1		T49	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17009	1			T3	12		T8	152		T9	149
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T263	5		T275	7		T276	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T267	7		T269	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T268	5		T273	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T200	10		T277	10		T278	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T47	10		T144	8		T163	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	814	1			T25	11		T28	16		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T146	16		T16	8		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T17	3		T169	11		T152	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	2		T62	5		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T29	8		T18	1		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	14		T10	2		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	2		T26	12		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T242	9		T229	15		T55	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	2		T243	6		T155	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T39	2		T231	9		T42	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	9		T149	9		T153	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	1		T153	7		T252	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	1		T43	4		T150	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T17	1		T36	8		T235	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T34	10		T144	10		T53	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T49	9		T27	1		T146	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T33	1		T158	10		T193	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T6	1		T47	11		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1112	1			T2	2		T7	2		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T11	5		T146	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	1		T17	7		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T226	1		T62	6		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	1		T26	13		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T4	15		T10	3		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	3		T29	9		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T39	3		T42	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	3		T39	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T119	1		T15	4		T231	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	10		T12	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T247	1		T40	3		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	3		T150	4		T164	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T17	3		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T34	11		T38	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T49	10		T119	1		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T150	8		T230	1		T270	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T6	1		T41	8		T230	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T193	10		T249	4		T244	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	12		T38	14		T30	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	15		T7	18		T31	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	3		T16	8		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T38	19		T17	4		T150	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T226	11		T62	2		T35	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T26	8		T156	2		T256	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	10		T26	10		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	2		T30	5		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T42	6		T228	10		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	6		T226	11		T162	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	1		T169	9		T156	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T43	4		T243	4		T193	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T247	17		T36	9		T271	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T150	5		T164	6		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T17	1		T230	15		T248	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	4		T144	9		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T49	8		T27	7		T237	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T150	9		T230	6		T270	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T230	5		T279	17		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	494	1			T8	2		T9	1		T13	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T267	8		T269	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T268	6		T273	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	1		T244	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T47	11		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T2	2		T7	2		T50	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	1		T11	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T147	1		T17	7		T169	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	4		T62	6		T44	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	1		T38	1		T29	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	15		T10	3		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	3		T26	13		T146	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T242	10		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	3		T39	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T119	1		T39	3		T231	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T10	10		T12	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	4		T161	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	3		T43	8		T150	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T247	1		T40	3		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T34	11		T38	1		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	446	1			T1	1		T6	1		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17144	1			T3	12		T8	152		T9	149
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T263	6		T275	9		T280	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T269	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T273	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T244	2		T223	10		T278	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	12		T38	14		T226	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	15		T7	18		T31	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	2		T30	7		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	4		T169	11		T171	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T11	1		T62	2		T44	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T38	19		T150	7		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	10		T26	10		T27	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	2		T26	8		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T154	9		T229	9		T55	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T47	6		T30	5		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T42	6		T228	10		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T162	14		T153	2		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T15	1		T156	20		T281	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	4		T150	5		T193	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T247	17		T17	1		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T38	4		T144	9		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T49	8		T27	7		T237	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18