Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23002

1

T2

17

T3

12

T4

25

auto[ADC_CTRL_FILTER_COND_OUT]

3163

1

T1

1

T13

3

T48

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20690

1

T1

1

T3

12

T5

1

auto[1]

5475

1

T2

17

T4

25

T6

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	92	1			T4	25		T11	3		T260	12
values[0]	80	1			T10	10		T155	17		T172	8
values[1]	673	1			T6	1		T26	23		T226	12
values[2]	553	1			T1	1		T5	1		T38	20
values[3]	569	1			T48	1		T119	1		T148	6
values[4]	2710	1			T2	17		T7	20		T48	1
values[5]	599	1			T12	1		T38	15		T146	29
values[6]	724	1			T10	3		T39	3		T30	6
values[7]	580	1			T6	1		T13	3		T49	18
values[8]	638	1			T39	1		T26	21		T144	13
values[9]	1355	1			T6	1		T11	10		T47	32
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	952	1			T5	1		T6	1		T10	10
values[1]	507	1			T1	1		T33	1		T147	1
values[2]	505	1			T48	1		T119	1		T38	5
values[3]	2790	1			T2	17		T7	20		T48	1
values[4]	619	1			T10	3		T12	1		T30	6
values[5]	648	1			T6	1		T39	3		T29	9
values[6]	637	1			T13	3		T49	18		T231	10
values[7]	649	1			T11	5		T39	1		T26	21
values[8]	1021	1			T4	25		T6	1		T11	5
values[9]	218	1			T11	3		T39	1		T149	12
minimum	17619	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T5	1		T6	1		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T38	20		T26	11		T226	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T33	1		T147	1		T162	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	1		T17	3		T249	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T48	1		T146	1		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T119	1		T38	5		T36	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	17		T7	20		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	15		T30	8		T146	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T12	1		T237	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T30	6		T226	12		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	1		T158	1		T193	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	1		T29	1		T226	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	9		T231	1		T62	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	2		T61	5		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	3		T39	1		T144	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	9		T149	2		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T4	11		T6	1		T11	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	1		T34	1		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T11	3		T149	1		T199	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T39	1		T161	1		T199	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17472	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	9		T17	3		T173	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	12		T242	9		T245	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T153	3		T55	1		T188	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T17	1		T249	8		T259	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T146	6		T148	5		T150	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T36	8		T262	12		T235	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	873	1			T25	11		T27	4		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T146	27		T193	5		T145	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	2		T237	6		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	6		T35	10		T152	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T158	12		T193	2		T232	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	2		T29	8		T145	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	9		T231	9		T62	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	1		T61	9		T158	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	2		T144	8		T148	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	12		T149	15		T228	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T4	14		T11	2		T47	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T34	10		T15	1		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T149	11		T167	4		T239	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T282	15		T55	3		T261	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T4	11		T11	3		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T194	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T10	1		T155	10		T172	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	1		T17	8		T169	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T26	11		T226	12		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	1		T33	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	1		T38	20		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	1		T148	1		T150	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T119	1		T17	3		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T2	17		T7	20		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T38	5		T30	8		T193	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T169	10		T200	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T38	15		T146	2		T162	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	1		T237	12		T41	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	1		T30	6		T226	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	1		T49	9		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T29	1		T226	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	1		T144	5		T247	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T26	9		T149	1		T61	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	383	1			T6	1		T11	6		T47	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T48	1		T34	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T4	14		T260	11		T92	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T10	9		T155	7		T283	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	3		T169	11		T241	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	12		T245	4		T164	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T173	9		T153	1		T164	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T242	9		T249	8		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T148	5		T150	3		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T17	1		T36	8		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	852	1			T25	11		T27	4		T28	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T193	5		T163	10		T200	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T169	10		T200	10		T165	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T146	27		T145	4		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	2		T237	6		T41	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	2		T41	6		T145	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T49	9		T231	9		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	1		T29	8		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	8		T44	1		T164	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	12		T149	9		T61	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T11	4		T47	12		T27	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T34	10		T15	1		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	1		T6	1		T10	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T38	1		T26	13		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T33	1		T147	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	1		T17	3		T249	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	1		T146	7		T148	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	1		T38	1		T36	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T2	2		T7	2		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	1		T30	1		T146	29
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	3		T12	1		T237	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	1		T226	1		T41	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	1		T158	13		T193	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	3		T29	9		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T49	10		T231	10		T62	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	3		T61	10		T158	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	3		T39	1		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T26	13		T149	17		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T4	15		T6	1		T11	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T48	1		T34	11		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T11	1		T149	12		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T39	1		T161	1		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17606	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T17	4		T173	15		T169	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T38	19		T26	10		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T162	9		T153	2		T55	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T17	1		T249	4		T197	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T150	5		T201	16		T284	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	4		T36	9		T199	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T2	15		T7	18		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T38	14		T30	7		T193	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T237	11		T37	10		T263	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	5		T226	11		T150	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T193	10		T264	3		T171	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T226	19		T162	14		T156	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T49	8		T62	2		T245	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T61	4		T252	13		T257	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	2		T144	4		T247	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	8		T228	10		T241	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	10		T11	1		T47	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T15	1		T144	9		T16	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	2		T199	6		T285	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T199	2		T282	11		T55	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T252	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T4	15		T11	1		T260	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T194	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T10	10		T155	8		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	1		T17	7		T169	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	13		T226	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	1		T33	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T38	1		T242	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	1		T148	6		T150	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T119	1		T17	3		T36	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T2	2		T7	2		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T38	1		T30	1		T193	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	1		T169	11		T200	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T38	1		T146	29		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T10	3		T237	7		T41	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	3		T30	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T49	10		T231	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	3		T29	9		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T39	1		T144	9		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	13		T149	10		T61	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	360	1			T6	1		T11	7		T47	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T48	1		T34	11		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T4	10		T11	2		T92	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T194	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T155	9		T172	7		T283	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	4		T169	11		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	10		T226	11		T245	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T173	15		T164	6		T201	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	19		T249	4		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T150	5		T153	2		T55	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T17	1		T36	9		T199	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T2	15		T7	18		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T38	4		T30	7		T193	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T169	9		T37	10		T194	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T38	14		T162	14		T150	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T237	11		T62	2		T193	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T30	5		T226	11		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T49	8		T245	17		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T226	19		T228	10		T156	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T144	4		T247	17		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T26	8		T61	4		T241	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	3		T47	18		T27	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T15	1		T144	9		T16	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18