Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23126

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3039

1

T6

1

T10

10

T13

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20400

1

T1

1

T3

12

T6

1

auto[1]

5765

1

T2

17

T4

25

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T252	26		T286	1		-	-
values[0]	63	1			T36	18		T271	25		T287	3
values[1]	467	1			T5	1		T10	3		T12	1
values[2]	696	1			T6	1		T47	32		T29	9
values[3]	499	1			T48	1		T119	1		T34	11
values[4]	609	1			T226	12		T227	1		T149	10
values[5]	2718	1			T2	17		T4	25		T7	20
values[6]	643	1			T6	1		T15	5		T226	20
values[7]	886	1			T1	1		T11	3		T26	21
values[8]	600	1			T6	1		T11	5		T38	20
values[9]	1365	1			T10	10		T11	5		T13	3
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	726	1			T5	1		T10	3		T12	1
values[1]	695	1			T6	1		T47	32		T48	1
values[2]	531	1			T34	11		T39	1		T193	13
values[3]	2651	1			T2	17		T7	20		T50	2
values[4]	548	1			T4	25		T6	1		T38	15
values[5]	688	1			T1	1		T26	21		T146	7
values[6]	956	1			T11	8		T38	20		T26	23
values[7]	640	1			T6	1		T10	10		T48	1
values[8]	903	1			T11	5		T13	3		T49	18
values[9]	225	1			T119	1		T38	5		T159	1
minimum	17602	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T10	1		T12	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	8		T61	5		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	1		T41	1		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T47	20		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	1		T244	11		T199	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T34	1		T193	11		T229	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T2	17		T7	20		T50	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T227	1		T149	1		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	11		T15	4		T27	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	1		T38	15		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	1		T146	1		T226	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T26	9		T43	1		T228	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T11	6		T38	20		T26	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T226	12		T40	3		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	1		T48	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T53	12		T229	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	3		T27	8		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T13	2		T49	9		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T119	1		T38	5		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T163	12		T199	3		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17460	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	2		T242	9		T237	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T61	9		T158	12		T36	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	12		T17	1		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	12		T29	8		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T244	10		T289	7		T255	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T34	10		T193	2		T229	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	826	1			T25	11		T28	16		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T149	11		T42	20		T44	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	14		T15	1		T27	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	2		T16	8		T235	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	6		T144	10		T245	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T26	12		T228	2		T35	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	2		T26	12		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T148	7		T193	11		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T232	3		T152	14		T270	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	9		T53	10		T229	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T27	1		T146	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T49	9		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T233	13		T258	2		T21	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T163	10		T290	9		T177	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T286	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T252	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T271	12		T287	2		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T36	10		T107	1		T292	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T10	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T61	5		T158	1		T156	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	1		T30	6		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T47	20		T29	1		T30	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	1		T147	1		T41	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	1		T119	1		T34	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T226	12		T149	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T227	1		T42	10		T193	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T2	17		T4	11		T7	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	15		T39	1		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T15	4		T226	20		T247	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T43	1		T228	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T11	3		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T26	9		T226	12		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	1		T11	3		T38	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T53	12		T148	1		T164	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T11	3		T48	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T10	1		T13	2		T49	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T252	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T271	13		T287	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T36	8		T292	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	2		T41	6		T158	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T61	9		T158	12		T163	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T242	9		T237	6		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	12		T29	8		T249	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T41	12		T169	11		T289	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T34	10		T17	3		T241	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T149	9		T148	5		T43	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T42	20		T193	2		T44	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	858	1			T4	14		T25	11		T27	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T39	2		T16	8		T149	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T158	9		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T228	2		T35	10		T115	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T146	6		T144	10		T232	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T26	12		T193	11		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	2		T26	12		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T53	10		T148	7		T164	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	2		T27	1		T146	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T10	9		T13	1		T49	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T10	3		T12	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	1		T61	10		T158	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T41	13		T17	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	14		T48	1		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T39	1		T244	11		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T34	11		T193	3		T229	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1153	1			T2	2		T7	2		T50	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T227	1		T149	12		T42	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	15		T15	4		T27	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T38	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	1		T146	7		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T26	13		T43	1		T228	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T11	4		T38	1		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T226	1		T40	3		T148	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	1		T48	1		T232	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	10		T53	11		T229	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	4		T27	2		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	3		T49	10		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T119	1		T38	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T163	11		T199	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17602	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T30	5		T237	11		T150	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T30	7		T61	4		T156	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T17	1		T169	11		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	18		T17	4		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T244	10		T199	6		T289	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T193	10		T229	9		T55	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	15		T7	18		T31	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T42	6		T44	2		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T4	10		T15	1		T27	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T38	14		T16	8		T266	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T226	19		T144	9		T247	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T26	8		T228	10		T35	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	4		T38	19		T26	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T226	11		T193	15		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T152	11		T270	18		T168	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	11		T229	13		T230	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T27	7		T173	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T49	8		T169	9		T162	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T38	4		T233	14		T21	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T163	11		T199	2		T189	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T286	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T252	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T271	14		T287	3		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T36	9		T107	1		T292	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T61	10		T158	13		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T30	1		T242	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	14		T29	9		T30	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T39	1		T147	1		T41	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	1		T119	1		T34	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T226	1		T149	10		T148	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T227	1		T42	24		T193	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T2	2		T4	15		T7	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T38	1		T39	3		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	4		T226	1		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T6	1		T43	1		T228	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T11	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T26	13		T226	1		T40	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T11	3		T38	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T53	11		T148	8		T164	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T11	4		T48	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T10	10		T13	3		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T252	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T271	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T36	9		T292	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	5		T252	13		T201	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T61	4		T156	3		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T30	5		T237	11		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	18		T30	7		T249	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T169	11		T199	6		T289	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T17	4		T162	9		T241	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T226	11		T43	4		T62	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T42	6		T193	10		T44	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T2	15		T4	10		T7	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T38	14		T16	8		T293	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	1		T226	19		T247	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T228	10		T35	11		T156	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	2		T144	9		T248	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T26	8		T226	11		T193	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	2		T38	19		T26	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T53	11		T229	13		T230	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T11	1		T38	4		T27	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T49	8		T169	9		T162	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18