Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22747

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3418

1

T6

3

T10

13

T11

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20622

1

T3

12

T5

1

T6

2

auto[1]

5543

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T170	1		T285	19		-	-
values[0]	37	1			T119	1		T150	17		T189	4
values[1]	487	1			T4	25		T49	18		T34	11
values[2]	2668	1			T1	1		T2	17		T6	1
values[3]	678	1			T47	23		T39	3		T26	21
values[4]	643	1			T30	6		T146	12		T242	10
values[5]	672	1			T6	1		T11	5		T12	1
values[6]	736	1			T5	1		T119	1		T38	20
values[7]	372	1			T48	1		T38	15		T29	9
values[8]	716	1			T10	10		T11	5		T13	3
values[9]	1544	1			T6	1		T10	3		T11	3
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	700	1			T4	25		T49	18		T119	1
values[1]	2608	1			T1	1		T2	17		T6	1
values[2]	775	1			T47	23		T39	3		T26	21
values[3]	563	1			T6	1		T11	5		T146	29
values[4]	715	1			T12	1		T119	1		T39	1
values[5]	577	1			T5	1		T38	35		T29	9
values[6]	439	1			T10	10		T48	1		T16	21
values[7]	784	1			T11	8		T13	3		T47	9
values[8]	1155	1			T10	3		T48	2		T38	5
values[9]	230	1			T6	1		T26	23		T149	7
minimum	17619	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	11		T119	1		T34	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T49	9		T30	8		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	1		T2	17		T7	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T6	1		T247	18		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T39	1		T26	9		T155	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	13		T146	1		T226	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	1		T53	12		T242	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	1		T11	3		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T27	8		T30	6		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T119	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	1		T29	1		T294	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	35		T149	1		T61	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T16	13		T231	1		T41	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T48	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	3		T13	2		T47	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T11	3		T15	4		T17	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T48	1		T39	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T10	1		T48	1		T38	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T26	11		T149	1		T237	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T6	1		T274	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17471	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	14		T34	10		T27	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T49	9		T241	1		T193	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	797	1			T25	11		T28	16		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T163	1		T229	12		T282	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T39	2		T26	12		T155	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	10		T146	6		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T146	11		T53	10		T242	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	2		T146	16		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T27	1		T42	20		T150	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T241	16		T296	10		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	8		T245	4		T200	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T149	11		T61	9		T169	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	8		T231	9		T41	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T10	9		T17	1		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	2		T13	1		T47	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T15	1		T17	3		T152	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T158	12		T62	5		T193	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	2		T144	8		T149	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T26	12		T149	6		T237	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T297	9		T298	6		T299	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T170	1		T285	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T119	1		T150	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T189	4		T300	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	11		T34	1		T27	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T49	9		T162	10		T241	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T1	1		T2	17		T7	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T30	8		T247	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T39	1		T26	9		T155	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	13		T146	1		T226	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	6		T146	1		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T41	1		T158	1		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	8		T53	12		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	1		T11	3		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	1		T163	12		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T119	1		T38	20		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T29	1		T16	13		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T48	1		T38	15		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	3		T13	2		T47	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	1		T17	8		T154	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	398	1			T39	1		T26	11		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	477	1			T6	1		T10	1		T11	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T150	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T300	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	14		T34	10		T27	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T49	9		T241	1		T193	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	848	1			T25	11		T28	16		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T18	1		T163	1		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	2		T26	12		T155	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T47	10		T146	6		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T146	11		T242	9		T193	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T41	12		T158	3		T232	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	1		T53	10		T42	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	2		T146	16		T61	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T163	10		T245	4		T235	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	11		T169	10		T241	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T29	8		T16	8		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T17	1		T249	8		T301	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	2		T13	1		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	9		T17	3		T152	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T26	12		T149	6		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T10	2		T15	1		T144	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	15		T119	1		T34	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T49	10		T30	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1129	1			T1	1		T2	2		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	1		T247	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T39	3		T26	13		T155	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	11		T146	7		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	12		T53	11		T242	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T11	4		T146	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	2		T30	1		T42	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T119	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T29	9		T294	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	2		T149	12		T61	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T16	13		T231	10		T41	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	10		T48	1		T17	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	3		T13	3		T47	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	1		T15	4		T17	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T48	1		T39	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T10	3		T48	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T26	13		T149	7		T237	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T6	1		T274	1		T288	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17605	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T4	10		T27	6		T226	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	8		T30	7		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T2	15		T7	18		T31	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T247	17		T229	13		T302	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	8		T155	10		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	12		T226	11		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T53	11		T193	15		T145	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	1		T152	11		T248	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T27	7		T30	5		T42	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T241	9		T303	10		T278	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T245	6		T261	1		T251	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	33		T61	4		T169	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T16	8		T156	2		T163	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T17	1		T249	4		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	2		T47	6		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	2		T15	1		T17	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T62	2		T193	4		T156	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T38	4		T226	19		T144	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T26	10		T237	11		T155	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T297	7		T298	6		T285	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T304	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T170	1		T285	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T119	1		T150	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T189	1		T300	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	15		T34	11		T27	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T49	10		T162	1		T241	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T1	1		T2	2		T7	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	1		T30	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	3		T26	13		T155	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	11		T146	7		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T146	12		T242	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T41	13		T158	4		T232	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	2		T53	11		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T11	4		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T163	11		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T119	1		T38	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	9		T16	13		T41	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T48	1		T38	1		T17	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	3		T13	3		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	10		T17	7		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T39	1		T26	13		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T6	1		T10	3		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T285	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T150	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T189	3		T300	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T4	10		T27	6		T226	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T49	8		T162	9		T193	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T2	15		T7	18		T31	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	7		T247	17		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T26	8		T155	10		T194	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	12		T226	11		T169	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	5		T193	15		T145	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	11		T289	7		T248	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T27	7		T53	11		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	1		T61	4		T305	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T163	11		T245	6		T261	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	19		T169	9		T241	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T16	8		T228	7		T156	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T38	14		T17	1		T249	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	2		T47	6		T55	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T17	4		T154	9		T264	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T26	10		T237	11		T43	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	399	1			T11	2		T38	4		T15	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18