Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22882

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3283

1

T6

1

T10

10

T11

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20703

1

T3

12

T4

25

T6

1

auto[1]

5462

1

T1

1

T2

17

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T306	2		-	-		-	-
values[0]	71	1			T39	1		T61	14		T299	12
values[1]	678	1			T48	1		T119	1		T26	21
values[2]	647	1			T11	5		T48	1		T39	3
values[3]	638	1			T6	1		T47	9		T27	9
values[4]	657	1			T48	1		T38	20		T27	11
values[5]	558	1			T10	10		T11	3		T34	11
values[6]	655	1			T5	1		T6	1		T10	3
values[7]	886	1			T12	1		T49	18		T119	1
values[8]	2603	1			T2	17		T7	20		T13	3
values[9]	1178	1			T1	1		T4	25		T6	1
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	903	1			T48	1		T39	4		T15	5
values[1]	651	1			T6	1		T11	5		T47	9
values[2]	595	1			T48	1		T27	9		T237	18
values[3]	690	1			T34	11		T27	11		T144	20
values[4]	490	1			T10	13		T11	3		T38	20
values[5]	833	1			T5	1		T6	1		T38	5
values[6]	2738	1			T2	17		T7	20		T49	18
values[7]	654	1			T12	1		T13	3		T30	6
values[8]	854	1			T1	1		T6	1		T11	5
values[9]	142	1			T4	25		T18	2		T296	11
minimum	17615	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T39	1		T26	9		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	1		T39	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T29	1		T16	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	3		T47	7		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	8		T237	12		T43	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	1		T17	3		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T27	7		T247	18		T18	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	1		T144	10		T41	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T38	20		T41	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	1		T11	3		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	1		T38	5		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	1		T152	1		T245	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T2	17		T7	20		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T49	9		T119	1		T30	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T30	6		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	2		T146	1		T144	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	1		T6	1		T47	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	3		T149	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T4	11		T307	1		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T18	1		T296	1		T305	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T309	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T39	2		T26	12		T241	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	1		T146	6		T61	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	8		T16	8		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	2		T47	2		T26	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T27	1		T237	6		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T17	1		T42	20		T62	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T27	4		T18	4		T153	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	10		T144	10		T41	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T10	2		T41	6		T245	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T10	9		T146	16		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T243	6		T155	11		T145	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T152	1		T245	17		T229	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	800	1			T25	11		T28	16		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T49	9		T53	10		T158	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T152	1		T296	10		T270	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T146	11		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	10		T155	7		T249	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	2		T149	15		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T4	14		T307	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T18	1		T296	10		T305	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T309	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T299	1		T310	1		T179	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T39	1		T61	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T26	9		T226	12		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	1		T119	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T39	1		T33	1		T162	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	3		T48	1		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	1		T27	8		T29	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T47	7		T17	3		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	20		T27	7		T247	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	1		T41	1		T62	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T41	2		T162	10		T18	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T11	3		T34	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T10	1		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T146	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T12	1		T30	6		T226	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T49	9		T119	1		T30	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T2	17		T7	20		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	2		T146	1		T17	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T1	1		T4	11		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T11	3		T144	5		T149	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T299	11		T310	15		T179	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T61	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	12		T169	10		T241	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T146	6		T148	5		T235	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T39	2		T241	1		T171	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	2		T15	1		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T27	1		T29	8		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T47	2		T17	1		T42	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T27	4		T43	4		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T41	12		T62	5		T163	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	6		T18	4		T245	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T10	9		T34	10		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T10	2		T243	6		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T146	16		T158	9		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T148	7		T152	14		T153	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	9		T53	10		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	776	1			T25	11		T28	16		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T146	11		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	14		T47	10		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T11	2		T144	8		T149	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T39	3		T26	13		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	1		T39	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	1		T29	9		T16	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	4		T47	3		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	2		T237	7		T43	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	1		T17	3		T42	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T27	5		T247	1		T18	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T34	11		T144	11		T41	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	3		T38	1		T41	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T10	10		T11	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T5	1		T38	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T152	2		T245	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T2	2		T7	2		T50	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T49	10		T119	1		T30	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T30	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	3		T146	12		T144	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T6	1		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	3		T149	17		T158	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T4	15		T307	5		T308	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T18	2		T296	11		T305	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T309	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T26	8		T226	11		T162	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	1		T61	4		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	8		T169	9		T153	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	1		T47	6		T26	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T27	7		T237	11		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T17	1		T42	6		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T27	6		T247	17		T18	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	9		T228	7		T150	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	19		T162	9		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T11	2		T199	12		T201	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T38	4		T243	4		T155	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T245	17		T229	9		T255	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T2	15		T7	18		T31	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T49	8		T30	7		T53	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T30	5		T270	11		T297	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	4		T17	4		T173	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T47	12		T38	14		T154	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	2		T169	11		T193	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T4	10		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T305	9		T298	6		T278	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T309	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T306	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T299	12		T310	16		T179	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T39	1		T61	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T26	13		T226	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	1		T119	1		T146	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	3		T33	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	4		T48	1		T15	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	1		T27	2		T29	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T47	3		T17	3		T42	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T38	1		T27	5		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	1		T41	13		T62	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T41	8		T162	1		T18	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	10		T11	1		T34	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T10	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	1		T146	17		T158	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T30	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T49	10		T119	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T2	2		T7	2		T50	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	3		T146	12		T17	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T1	1		T4	15		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T11	3		T144	9		T149	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T179	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T61	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T26	8		T226	11		T169	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T156	20		T257	9		T311	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T162	14		T230	6		T171	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T15	1		T26	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T27	7		T16	8		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T47	6		T17	1		T42	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T38	19		T27	6		T247	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T62	2		T176	1		T265	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T162	9		T18	5		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	2		T144	9		T228	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T38	4		T243	4		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T199	12		T245	17		T229	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T30	5		T226	11		T156	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T49	8		T30	7		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T2	15		T7	18		T31	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T17	4		T173	15		T171	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	10		T47	12		T38	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	2		T144	4		T169	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18