Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22569

1

T1

1

T2

17

T3

12

auto[ADC_CTRL_FILTER_COND_OUT]

3596

1

T4

25

T5

1

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20530

1

T3

12

T5

1

T6

2

auto[1]

5635

1

T1

1

T2

17

T4

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	214	1			T62	8		T145	9		T19	12
values[0]	13	1			T285	13		-	-		-	-
values[1]	820	1			T48	1		T38	15		T30	8
values[2]	818	1			T13	3		T34	11		T38	5
values[3]	590	1			T6	1		T39	2		T26	44
values[4]	520	1			T6	1		T10	10		T11	3
values[5]	2967	1			T2	17		T7	20		T11	10
values[6]	673	1			T38	20		T147	1		T42	30
values[7]	385	1			T1	1		T4	25		T48	1
values[8]	728	1			T5	1		T29	9		T33	1
values[9]	845	1			T6	1		T10	3		T47	9
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	725	1			T34	11		T38	20		T30	8
values[1]	727	1			T13	3		T27	11		T226	20
values[2]	538	1			T6	2		T47	23		T39	2
values[3]	2740	1			T2	17		T7	20		T10	10
values[4]	769	1			T11	10		T15	5		T226	12
values[5]	689	1			T4	25		T119	1		T38	20
values[6]	392	1			T1	1		T5	1		T48	1
values[7]	653	1			T29	9		T33	1		T146	12
values[8]	885	1			T6	1		T10	3		T47	9
values[9]	99	1			T145	9		T156	21		T271	26
minimum	17948	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	1		T38	5		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T38	15		T30	8		T247	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T27	7		T226	20		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	2		T53	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T39	1		T26	20		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	2		T47	13		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T2	17		T7	20		T10	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	3		T48	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T11	3		T149	1		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	3		T15	4		T226	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T119	1		T38	20		T228	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	11		T144	10		T243	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	1		T144	5		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	1		T48	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T29	1		T146	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T33	1		T149	1		T237	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T47	7		T39	1		T30	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T10	1		T49	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T156	21		T271	13		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T145	5		T292	15		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17553	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	1		T262	14		T93	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T34	10		T61	9		T41	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T149	6		T241	16		T193	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	4		T41	12		T150	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	1		T53	10		T43	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T26	24		T27	1		T158	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T47	10		T148	7		T44	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	832	1			T10	9		T25	11		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	6		T242	9		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	2		T149	9		T228	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	2		T15	1		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T228	7		T153	7		T286	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	14		T144	10		T243	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T144	8		T231	9		T17	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T146	16		T145	1		T164	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T29	8		T146	11		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T149	11		T237	6		T17	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	2		T39	2		T62	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	2		T49	9		T155	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T271	13		T104	5		T312	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T145	4		T292	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T13	1		T34	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T262	12		T93	11		T297	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T62	3		T19	9		T104	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T145	5		T168	6		T298	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T285	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T61	5		T41	2		T156	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T48	1		T38	15		T30	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T34	1		T38	5		T27	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	2		T247	18		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T39	1		T26	20		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T39	1		T226	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	1		T27	8		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T11	3		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T2	17		T7	20		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	3		T15	4		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T38	20		T228	8		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T147	1		T42	10		T243	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T1	1		T119	1		T144	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	11		T48	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T29	1		T146	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	1		T33	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T47	7		T39	1		T30	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	1		T10	1		T49	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T62	5		T19	3		T104	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T145	4		T298	7		T292	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T61	9		T41	6		T153	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T193	7		T262	12		T263	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T34	10		T27	4		T41	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	1		T149	6		T53	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T26	24		T169	10		T152	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	7		T43	4		T241	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	9		T27	1		T158	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T47	10		T242	9		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T11	2		T25	11		T28	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	2		T15	1		T146	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T228	7		T153	7		T230	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T42	20		T243	6		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T144	8		T231	9		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T4	14		T144	10		T145	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T29	8		T146	11		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T146	16		T149	11		T237	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	2		T39	2		T193	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	2		T49	9		T17	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	11		T38	1		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T38	1		T30	1		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	5		T226	1		T41	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	3		T53	11		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	1		T26	26		T27	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	2		T47	11		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T2	2		T7	2		T10	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	1		T48	1		T146	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	4		T149	10		T43	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	3		T15	4		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T119	1		T38	1		T228	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	15		T144	11		T243	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	1		T144	9		T231	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T48	1		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	9		T146	12		T148	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T33	1		T149	12		T237	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T47	3		T39	3		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T6	1		T10	3		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T156	1		T271	14		T104	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T145	7		T292	12		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T3	12		T8	154		T9	150
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	1		T262	13		T93	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T38	4		T61	4		T162	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T38	14		T30	7		T247	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T27	6		T226	19		T150	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T53	11		T43	4		T150	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	18		T27	7		T169	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	12		T226	11		T44	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T2	15		T7	18		T31	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	2		T245	6		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T228	10		T154	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	2		T15	1		T226	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T38	19		T228	7		T230	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	10		T144	9		T243	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T144	4		T17	4		T266	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T199	2		T164	6		T313	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T199	6		T189	3		T194	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T237	11		T17	1		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	6		T30	5		T62	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	8		T155	10		T36	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T156	20		T271	12		T312	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T145	2		T292	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T156	3		T256	2		T234	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T262	13		T168	13		T297	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T62	6		T19	10		T104	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T145	7		T168	1		T298	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T285	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T61	10		T41	8		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T48	1		T38	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T34	11		T38	1		T27	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	3		T247	1		T149	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T39	1		T26	26		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T39	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T10	10		T27	2		T158	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T11	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T2	2		T7	2		T11	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	3		T15	4		T146	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	1		T228	8		T153	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T147	1		T42	24		T243	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T1	1		T119	1		T144	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	15		T48	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	9		T146	12		T148	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T5	1		T33	1		T146	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T47	3		T39	3		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	1		T10	3		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T62	2		T19	2		T314	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T145	2		T168	5		T298	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T285	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T61	4		T156	3		T256	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T38	14		T30	7		T193	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T38	4		T27	6		T226	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T247	17		T53	11		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T26	18		T169	9		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T226	11		T43	4		T44	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T27	7		T173	15		T163	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	2		T47	12		T245	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T2	15		T7	18		T11	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	2		T15	1		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	19		T228	7		T230	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T42	6		T243	4		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T144	4		T17	4		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	10		T144	9		T162	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T199	6		T189	3		T266	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T237	11		T35	11		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	6		T30	5		T193	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	8		T17	1		T155	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18