Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26165

1

T1

1

T2

17

T3

12

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20600

1

T3

12

T4

25

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

5565

1

T1

1

T2

17

T5

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20460

1

T3

12

T4

25

T6

2

auto[1]

5705

1

T1

1

T2

17

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22545

1

T1

1

T2

17

T3

12

auto[1]

3620

1

T4

14

T10

11

T11

6

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T231	10		T315	31		-	-
values[0]	121	1			T237	18		T161	1		T118	13
values[1]	740	1			T29	9		T146	7		T144	13
values[2]	667	1			T10	3		T13	3		T48	1
values[3]	664	1			T11	5		T48	1		T146	17
values[4]	616	1			T4	25		T6	1		T12	1
values[5]	707	1			T119	1		T33	1		T146	12
values[6]	566	1			T39	1		T40	3		T148	8
values[7]	699	1			T47	9		T48	1		T119	1
values[8]	469	1			T6	1		T49	18		T149	22
values[9]	3283	1			T1	1		T2	17		T5	1
minimum	17592	1			T3	12		T8	154		T9	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1005	1			T48	1		T38	15		T39	3
values[1]	2665	1			T2	17		T7	20		T10	3
values[2]	668	1			T6	1		T47	23		T48	1
values[3]	692	1			T4	25		T27	11		T146	17
values[4]	722	1			T12	1		T119	1		T39	1
values[5]	574	1			T119	1		T38	20		T247	18
values[6]	596	1			T47	9		T48	1		T26	21
values[7]	547	1			T6	1		T11	8		T49	18
values[8]	841	1			T1	1		T5	1		T6	1
values[9]	216	1			T39	1		T30	6		T33	1
minimum	17639	1			T3	12		T8	154		T9	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

4074

1

T2

15

T4

10

T7

18

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T38	15		T39	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	1		T15	4		T26	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	3		T144	10		T61	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1537	1			T2	17		T7	20		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T226	20		T158	1		T18	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	1		T47	13		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	11		T146	1		T41	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T27	7		T226	12		T173	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T119	1		T39	1		T16	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T33	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T119	1		T38	20		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T247	18		T147	1		T42	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T47	7		T26	9		T30	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	1		T159	1		T145	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T11	3		T49	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	3		T149	2		T41	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T226	12		T149	1		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T1	1		T5	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T30	6		T33	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T39	1		T244	11		T246	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17482	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T39	2		T146	6		T53	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T15	1		T26	12		T29	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T144	10		T61	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	802	1			T10	2		T13	1		T25	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T158	9		T18	4		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	10		T62	5		T241	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T4	14		T146	16		T41	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	4		T173	9		T232	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T16	8		T148	12		T158	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T146	11		T228	7		T169	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T17	1		T234	11		T171	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T42	20		T169	11		T193	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	2		T26	12		T43	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	1		T301	14		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	2		T49	9		T228	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T149	20		T41	12		T158	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T149	6		T231	9		T243	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	9		T34	10		T242	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T262	12		T316	14		T317	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T244	10		T246	3		T315	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	2		T13	1		T34	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T231	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T315	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T237	12		T318	11		T254	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T161	1		T118	1		T319	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T146	1		T144	5		T53	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T29	1		T17	8		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T38	15		T39	1		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T13	2		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	3		T146	1		T226	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	1		T150	6		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	11		T41	2		T249	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T12	1		T47	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T119	1		T16	13		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T33	1		T146	1		T226	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T39	1		T40	3		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T42	10		T228	8		T169	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	7		T119	1		T38	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	1		T147	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	1		T49	9		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	2		T158	1		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T11	3		T30	6		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1786	1			T1	1		T2	17		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17457	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T231	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T315	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T237	6		T318	8		T254	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T118	12		T319	20		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T146	6		T144	8		T53	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	8		T17	3		T152	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T39	2		T144	10		T152	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	2		T13	1		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	2		T146	16		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	3		T18	1		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T4	14		T41	6		T249	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	10		T27	4		T62	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	8		T148	5		T158	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T146	11		T173	9		T241	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T148	7		T17	1		T307	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T42	20		T228	7		T169	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	2		T26	12		T43	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T155	11		T145	1		T301	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T49	9		T255	17		T261	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T149	20		T158	3		T233	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	2		T149	6		T228	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	978	1			T10	9		T34	10		T25	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T13	1		T34	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T38	1		T39	3		T146	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T48	1		T15	4		T26	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	4		T144	11		T61	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1126	1			T2	2		T7	2		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T226	1		T158	10		T18	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	1		T47	11		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	15		T146	17		T41	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	5		T226	1		T173	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T119	1		T39	1		T16	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T33	1		T146	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T119	1		T38	1		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T247	1		T147	1		T42	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	3		T26	13		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T48	1		T159	1		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T11	3		T49	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T149	22		T41	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T226	1		T149	7		T231	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T5	1		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T30	1		T33	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T39	1		T244	11		T246	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17617	1			T3	12		T8	154		T9	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T38	14		T53	11		T237	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	1		T26	10		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	1		T144	9		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1213	1			T2	15		T7	18		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T226	19		T18	5		T153	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	12		T62	2		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	10		T249	4		T153	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T27	6		T226	11		T173	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	8		T256	2		T245	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T228	7		T169	9		T193	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T38	19		T17	1		T154	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T247	17		T42	6		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T47	6		T26	8		T30	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T301	10		T233	14		T189	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	2		T49	8		T228	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	2		T199	12		T245	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T226	11		T243	4		T162	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T38	4		T155	9		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T30	5		T262	13		T316	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T244	10		T315	15		T224	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T144	4		T92	8		T320	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T231	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T315	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T237	7		T318	9		T254	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T161	1		T118	13		T319	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T146	7		T144	9		T53	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T29	9		T17	7		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T38	1		T39	3		T144	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	3		T13	3		T48	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	4		T146	17		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	1		T150	4		T18	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	15		T41	8		T249	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	1		T12	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T119	1		T16	13		T148	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	1		T146	12		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	1		T40	3		T148	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T42	24		T228	8		T169	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	3		T119	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	1		T147	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	1		T49	10		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	22		T158	4		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	3		T30	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1336	1			T1	1		T2	2		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17592	1			T3	12		T8	154		T9	150
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T315	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T237	11		T318	10		T254	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T319	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T144	4		T53	11		T61	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T17	4		T152	11		T281	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	14		T144	9		T156	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	1		T26	10		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T226	19		T145	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	5		T164	12		T293	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	10		T249	4		T153	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T47	12		T27	6		T62	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	8		T230	6		T255	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T226	11		T247	17		T173	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	1		T154	9		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T42	6		T228	7		T169	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	6		T38	19		T26	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T155	10		T301	10		T252	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T49	8		T255	13		T261	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T199	12		T233	14		T189	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	2		T30	5		T226	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1428	1			T2	15		T7	18		T11	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22091

1

T1

1

T2

2

T3

12

auto[1]

auto[0]

4074

1

T2

15

T4

10

T7

18