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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 911
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T82 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3942565368 Mar 14 12:21:34 PM PDT 24 Mar 14 12:21:36 PM PDT 24 634920202 ps
T799 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1159866820 Mar 14 12:24:14 PM PDT 24 Mar 14 12:24:16 PM PDT 24 386855900 ps
T120 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1942216716 Mar 14 12:20:12 PM PDT 24 Mar 14 12:20:18 PM PDT 24 1151598503 ps
T77 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1135496987 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 514038220 ps
T121 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.112348496 Mar 14 12:21:47 PM PDT 24 Mar 14 12:21:48 PM PDT 24 437530380 ps
T99 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1295970848 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:27 PM PDT 24 380822641 ps
T64 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.440951321 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:24 PM PDT 24 4544714559 ps
T65 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1169923601 Mar 14 12:20:54 PM PDT 24 Mar 14 12:21:06 PM PDT 24 4635788651 ps
T69 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1566184913 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:29 PM PDT 24 4270898290 ps
T81 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2529474554 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:33 PM PDT 24 4473644876 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.626748575 Mar 14 12:20:33 PM PDT 24 Mar 14 12:20:37 PM PDT 24 1937794528 ps
T142 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1586400314 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:13 PM PDT 24 366671651 ps
T60 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2629617711 Mar 14 12:24:59 PM PDT 24 Mar 14 12:25:00 PM PDT 24 352366440 ps
T86 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3836587878 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:13 PM PDT 24 649097658 ps
T59 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.423079975 Mar 14 12:24:27 PM PDT 24 Mar 14 12:24:33 PM PDT 24 2686615348 ps
T800 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1359057096 Mar 14 12:23:28 PM PDT 24 Mar 14 12:23:29 PM PDT 24 563722405 ps
T801 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4006361121 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:57 PM PDT 24 476390002 ps
T85 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3244570865 Mar 14 12:19:47 PM PDT 24 Mar 14 12:19:48 PM PDT 24 558495131 ps
T802 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2298297134 Mar 14 12:21:14 PM PDT 24 Mar 14 12:21:15 PM PDT 24 488729684 ps
T803 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3811448458 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:25 PM PDT 24 391056985 ps
T136 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1930674953 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:30 PM PDT 24 3558124001 ps
T804 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1564587105 Mar 14 12:24:15 PM PDT 24 Mar 14 12:24:16 PM PDT 24 324446614 ps
T805 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.800779362 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:57 PM PDT 24 381754900 ps
T122 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1051249890 Mar 14 12:24:12 PM PDT 24 Mar 14 12:24:13 PM PDT 24 424245666 ps
T109 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2236367191 Mar 14 12:23:35 PM PDT 24 Mar 14 12:23:36 PM PDT 24 575861903 ps
T143 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2692409738 Mar 14 12:22:11 PM PDT 24 Mar 14 12:22:15 PM PDT 24 1227988752 ps
T806 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.795973380 Mar 14 12:23:26 PM PDT 24 Mar 14 12:23:27 PM PDT 24 335750900 ps
T78 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.554408857 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:28 PM PDT 24 801385270 ps
T70 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2259930827 Mar 14 12:23:19 PM PDT 24 Mar 14 12:23:28 PM PDT 24 8714363863 ps
T807 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.524229568 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 294861448 ps
T808 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3930911921 Mar 14 12:24:03 PM PDT 24 Mar 14 12:24:04 PM PDT 24 470678420 ps
T809 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2406452046 Mar 14 12:19:28 PM PDT 24 Mar 14 12:19:29 PM PDT 24 870108647 ps
T810 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3502611536 Mar 14 12:20:39 PM PDT 24 Mar 14 12:20:41 PM PDT 24 318409014 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.126641825 Mar 14 12:22:53 PM PDT 24 Mar 14 12:22:54 PM PDT 24 489117655 ps
T137 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1904260592 Mar 14 12:23:46 PM PDT 24 Mar 14 12:23:50 PM PDT 24 539746373 ps
T138 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1033417777 Mar 14 12:23:48 PM PDT 24 Mar 14 12:23:57 PM PDT 24 1926582464 ps
T812 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.802571446 Mar 14 12:23:28 PM PDT 24 Mar 14 12:23:29 PM PDT 24 374548625 ps
T139 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1800381129 Mar 14 12:19:41 PM PDT 24 Mar 14 12:19:45 PM PDT 24 4064638329 ps
T813 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.678413150 Mar 14 12:24:29 PM PDT 24 Mar 14 12:24:31 PM PDT 24 443285161 ps
T74 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.610783079 Mar 14 12:23:28 PM PDT 24 Mar 14 12:23:30 PM PDT 24 521719645 ps
T814 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2369326406 Mar 14 12:23:50 PM PDT 24 Mar 14 12:23:51 PM PDT 24 509383282 ps
T140 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2765946932 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:18 PM PDT 24 2342071128 ps
T75 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1336584818 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:22 PM PDT 24 480770925 ps
T76 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1152236156 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:45 PM PDT 24 7684993937 ps
T815 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2772550457 Mar 14 12:23:26 PM PDT 24 Mar 14 12:23:27 PM PDT 24 460413282 ps
T816 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1135401954 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:41 PM PDT 24 430872255 ps
T141 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1362726589 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:49 PM PDT 24 2614141983 ps
T123 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.962391069 Mar 14 12:21:15 PM PDT 24 Mar 14 12:21:20 PM PDT 24 979341555 ps
T83 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.314758427 Mar 14 12:20:20 PM PDT 24 Mar 14 12:20:23 PM PDT 24 367681237 ps
T817 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3416288413 Mar 14 12:22:23 PM PDT 24 Mar 14 12:22:24 PM PDT 24 484847752 ps
T124 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3170520793 Mar 14 12:19:08 PM PDT 24 Mar 14 12:19:12 PM PDT 24 962145345 ps
T818 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3741010972 Mar 14 12:21:00 PM PDT 24 Mar 14 12:21:02 PM PDT 24 391642088 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.29682462 Mar 14 12:20:48 PM PDT 24 Mar 14 12:20:50 PM PDT 24 478452097 ps
T820 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3399892473 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:51 PM PDT 24 446488024 ps
T821 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2616136712 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:13 PM PDT 24 477276053 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4105831426 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:24 PM PDT 24 2227008589 ps
T823 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1612958450 Mar 14 12:23:50 PM PDT 24 Mar 14 12:23:52 PM PDT 24 513581549 ps
T824 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4163177504 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:21 PM PDT 24 543691761 ps
T84 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2410428986 Mar 14 12:22:37 PM PDT 24 Mar 14 12:22:40 PM PDT 24 539800648 ps
T825 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.612177041 Mar 14 12:21:44 PM PDT 24 Mar 14 12:21:46 PM PDT 24 434424877 ps
T125 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2803060979 Mar 14 12:20:48 PM PDT 24 Mar 14 12:20:53 PM PDT 24 6932554979 ps
T826 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2106772669 Mar 14 12:24:16 PM PDT 24 Mar 14 12:24:17 PM PDT 24 283873197 ps
T827 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1908745419 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:26 PM PDT 24 326741128 ps
T828 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3728713851 Mar 14 12:23:54 PM PDT 24 Mar 14 12:23:56 PM PDT 24 2428479656 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.109413664 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:28 PM PDT 24 400204015 ps
T830 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3295154013 Mar 14 12:22:58 PM PDT 24 Mar 14 12:23:11 PM PDT 24 5107350669 ps
T831 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2431409937 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:14 PM PDT 24 496417852 ps
T832 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1870140 Mar 14 12:20:56 PM PDT 24 Mar 14 12:21:07 PM PDT 24 5071416083 ps
T833 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.25693964 Mar 14 12:21:23 PM PDT 24 Mar 14 12:21:25 PM PDT 24 401754427 ps
T834 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2869235394 Mar 14 12:19:04 PM PDT 24 Mar 14 12:19:06 PM PDT 24 2325457690 ps
T835 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3818358756 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:31 PM PDT 24 4654920155 ps
T836 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3803161197 Mar 14 12:24:16 PM PDT 24 Mar 14 12:24:17 PM PDT 24 425052998 ps
T837 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1060285998 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:31 PM PDT 24 288777536 ps
T838 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1805349943 Mar 14 12:22:53 PM PDT 24 Mar 14 12:22:54 PM PDT 24 537381843 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2310580076 Mar 14 12:20:28 PM PDT 24 Mar 14 12:20:29 PM PDT 24 378015939 ps
T840 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1217510090 Mar 14 12:24:25 PM PDT 24 Mar 14 12:24:28 PM PDT 24 402976177 ps
T126 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2098014047 Mar 14 12:21:51 PM PDT 24 Mar 14 12:21:52 PM PDT 24 363426014 ps
T127 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.466112713 Mar 14 12:20:53 PM PDT 24 Mar 14 12:20:55 PM PDT 24 416307707 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.212411376 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:57 PM PDT 24 293722168 ps
T128 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1317054427 Mar 14 12:21:50 PM PDT 24 Mar 14 12:21:51 PM PDT 24 352719747 ps
T842 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.503161852 Mar 14 12:22:32 PM PDT 24 Mar 14 12:22:33 PM PDT 24 462250394 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.545590229 Mar 14 12:24:23 PM PDT 24 Mar 14 12:25:22 PM PDT 24 17040415018 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.81886449 Mar 14 12:24:13 PM PDT 24 Mar 14 12:24:25 PM PDT 24 4248253980 ps
T844 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4197880440 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:13 PM PDT 24 280813528 ps
T87 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2141267869 Mar 14 12:23:32 PM PDT 24 Mar 14 12:23:44 PM PDT 24 7783415715 ps
T845 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1494129268 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:31 PM PDT 24 309192380 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.187928997 Mar 14 12:21:09 PM PDT 24 Mar 14 12:21:12 PM PDT 24 703527622 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.911347177 Mar 14 12:23:56 PM PDT 24 Mar 14 12:24:01 PM PDT 24 1368738396 ps
T848 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1179439879 Mar 14 12:20:57 PM PDT 24 Mar 14 12:20:59 PM PDT 24 1064643338 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3947370003 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:25 PM PDT 24 311515349 ps
T349 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2159918885 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:26 PM PDT 24 8334343294 ps
T850 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1666041696 Mar 14 12:19:12 PM PDT 24 Mar 14 12:19:14 PM PDT 24 524557025 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.427375792 Mar 14 12:20:28 PM PDT 24 Mar 14 12:20:31 PM PDT 24 519769795 ps
T852 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1807387112 Mar 14 12:20:54 PM PDT 24 Mar 14 12:20:55 PM PDT 24 290441838 ps
T853 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1131131525 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:31 PM PDT 24 4354059909 ps
T854 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2306137879 Mar 14 12:19:42 PM PDT 24 Mar 14 12:19:51 PM PDT 24 2478660472 ps
T855 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4142214082 Mar 14 12:23:43 PM PDT 24 Mar 14 12:23:44 PM PDT 24 433700225 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.652924479 Mar 14 12:19:45 PM PDT 24 Mar 14 12:19:46 PM PDT 24 373539300 ps
T130 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1426853079 Mar 14 12:24:17 PM PDT 24 Mar 14 12:24:18 PM PDT 24 337770238 ps
T856 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.762699503 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:26 PM PDT 24 660116617 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3844108069 Mar 14 12:23:54 PM PDT 24 Mar 14 12:23:56 PM PDT 24 677293302 ps
T858 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.433079801 Mar 14 12:21:45 PM PDT 24 Mar 14 12:21:49 PM PDT 24 548511102 ps
T859 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3265413905 Mar 14 12:19:41 PM PDT 24 Mar 14 12:20:44 PM PDT 24 51817664646 ps
T860 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3599882009 Mar 14 12:22:50 PM PDT 24 Mar 14 12:22:53 PM PDT 24 1150743552 ps
T861 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2498228911 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:27 PM PDT 24 565556872 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.853321743 Mar 14 12:24:13 PM PDT 24 Mar 14 12:24:15 PM PDT 24 1288199960 ps
T863 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3935502317 Mar 14 12:23:38 PM PDT 24 Mar 14 12:23:40 PM PDT 24 386645476 ps
T864 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1774639313 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:14 PM PDT 24 1171685046 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3031257945 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 375515592 ps
T866 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1790124345 Mar 14 12:24:17 PM PDT 24 Mar 14 12:24:18 PM PDT 24 540199923 ps
T867 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2356230582 Mar 14 12:23:45 PM PDT 24 Mar 14 12:23:47 PM PDT 24 521453115 ps
T868 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2724613348 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:31 PM PDT 24 384347075 ps
T869 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1855591968 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:58 PM PDT 24 464190728 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2807306730 Mar 14 12:19:44 PM PDT 24 Mar 14 12:19:46 PM PDT 24 350358276 ps
T871 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2430863093 Mar 14 12:24:12 PM PDT 24 Mar 14 12:24:13 PM PDT 24 637485478 ps
T348 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3163528822 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:33 PM PDT 24 4582948944 ps
T872 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4080483596 Mar 14 12:20:29 PM PDT 24 Mar 14 12:20:31 PM PDT 24 460923741 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1596728219 Mar 14 12:20:54 PM PDT 24 Mar 14 12:21:05 PM PDT 24 4566518971 ps
T350 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3184760981 Mar 14 12:22:47 PM PDT 24 Mar 14 12:22:54 PM PDT 24 8500018287 ps
T874 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3689286416 Mar 14 12:23:40 PM PDT 24 Mar 14 12:23:41 PM PDT 24 473587323 ps
T875 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1334408525 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:29 PM PDT 24 4161547929 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.48006483 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:38 PM PDT 24 709741285 ps
T877 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3510937167 Mar 14 12:24:27 PM PDT 24 Mar 14 12:24:28 PM PDT 24 359514665 ps
T878 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4211477390 Mar 14 12:21:38 PM PDT 24 Mar 14 12:21:38 PM PDT 24 475812700 ps
T131 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2453489521 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:26 PM PDT 24 496490344 ps
T132 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3218221812 Mar 14 12:23:46 PM PDT 24 Mar 14 12:23:48 PM PDT 24 508058317 ps
T879 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4065374327 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:41 PM PDT 24 415728797 ps
T880 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2405712989 Mar 14 12:24:14 PM PDT 24 Mar 14 12:24:16 PM PDT 24 383839358 ps
T881 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.245772364 Mar 14 12:20:58 PM PDT 24 Mar 14 12:21:01 PM PDT 24 2166600468 ps
T882 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3495210982 Mar 14 12:22:37 PM PDT 24 Mar 14 12:22:39 PM PDT 24 531320298 ps
T883 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1651027272 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:43 PM PDT 24 8017379459 ps
T884 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4272659123 Mar 14 12:23:27 PM PDT 24 Mar 14 12:23:29 PM PDT 24 445768689 ps
T133 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.298240951 Mar 14 12:22:24 PM PDT 24 Mar 14 12:22:28 PM PDT 24 5144725218 ps
T134 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.409052279 Mar 14 12:20:42 PM PDT 24 Mar 14 12:20:45 PM PDT 24 964485644 ps
T885 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2590113145 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:27 PM PDT 24 498618933 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3747043818 Mar 14 12:24:05 PM PDT 24 Mar 14 12:24:07 PM PDT 24 418141175 ps
T887 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2643018436 Mar 14 12:22:04 PM PDT 24 Mar 14 12:22:07 PM PDT 24 499006917 ps
T888 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4012096686 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:41 PM PDT 24 300482367 ps
T889 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.675634200 Mar 14 12:24:12 PM PDT 24 Mar 14 12:24:15 PM PDT 24 4015120606 ps
T890 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1796587884 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:12 PM PDT 24 282650402 ps
T891 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.902503042 Mar 14 12:23:58 PM PDT 24 Mar 14 12:24:18 PM PDT 24 7907703158 ps
T892 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2692486118 Mar 14 12:23:28 PM PDT 24 Mar 14 12:23:31 PM PDT 24 4183999721 ps
T893 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4147061061 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:27 PM PDT 24 2388553490 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2736968685 Mar 14 12:20:58 PM PDT 24 Mar 14 12:21:01 PM PDT 24 789443440 ps
T895 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3416318456 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:21 PM PDT 24 643210185 ps
T896 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.108672455 Mar 14 12:20:34 PM PDT 24 Mar 14 12:20:36 PM PDT 24 515387818 ps
T897 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3229112335 Mar 14 12:24:12 PM PDT 24 Mar 14 12:24:19 PM PDT 24 5245461733 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1057162657 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:28 PM PDT 24 4714068283 ps
T899 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3095700495 Mar 14 12:19:47 PM PDT 24 Mar 14 12:19:49 PM PDT 24 713304071 ps
T900 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4181310966 Mar 14 12:23:45 PM PDT 24 Mar 14 12:23:48 PM PDT 24 473523699 ps
T901 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3630437965 Mar 14 12:24:10 PM PDT 24 Mar 14 12:24:12 PM PDT 24 394749710 ps
T902 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1408430716 Mar 14 12:23:50 PM PDT 24 Mar 14 12:23:51 PM PDT 24 562517865 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.320904360 Mar 14 12:23:40 PM PDT 24 Mar 14 12:23:43 PM PDT 24 566459072 ps
T904 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1007766817 Mar 14 12:20:34 PM PDT 24 Mar 14 12:20:35 PM PDT 24 425655348 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.787915729 Mar 14 12:24:30 PM PDT 24 Mar 14 12:24:31 PM PDT 24 398997059 ps
T906 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.385363735 Mar 14 12:23:24 PM PDT 24 Mar 14 12:23:26 PM PDT 24 494309656 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.70404993 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:21 PM PDT 24 485144672 ps
T908 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.618244779 Mar 14 12:23:43 PM PDT 24 Mar 14 12:24:07 PM PDT 24 8658554521 ps
T909 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4169081001 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:22 PM PDT 24 390088609 ps
T910 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1991072286 Mar 14 12:24:11 PM PDT 24 Mar 14 12:24:12 PM PDT 24 438932030 ps
T911 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2040050810 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:32 PM PDT 24 4483849647 ps

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1011662989
Short name T2
Test name
Test status
Simulation time 387196876656 ps
CPU time 223.45 seconds
Started Mar 14 12:38:18 PM PDT 24
Finished Mar 14 12:42:02 PM PDT 24
Peak memory 202152 kb
Host smart-0a07b6cd-affa-43ce-957b-dd425d7048ba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011662989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1011662989
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2543339921
Short name T8
Test name
Test status
Simulation time 96096314624 ps
CPU time 445.61 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:41:26 PM PDT 24
Peak memory 202484 kb
Host smart-56752483-a175-4442-9035-75d400987e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543339921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2543339921
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.553539391
Short name T11
Test name
Test status
Simulation time 67578294516 ps
CPU time 78.26 seconds
Started Mar 14 12:34:20 PM PDT 24
Finished Mar 14 12:35:38 PM PDT 24
Peak memory 210600 kb
Host smart-0346a64f-5084-4ccf-944f-37f1bc99d200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553539391 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.553539391
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2716377714
Short name T17
Test name
Test status
Simulation time 174038698594 ps
CPU time 325.52 seconds
Started Mar 14 12:34:13 PM PDT 24
Finished Mar 14 12:39:39 PM PDT 24
Peak memory 210424 kb
Host smart-9579984e-48b1-4460-99d7-e7e1c432885b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716377714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2716377714
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.649204622
Short name T55
Test name
Test status
Simulation time 594101836808 ps
CPU time 1082.88 seconds
Started Mar 14 12:39:14 PM PDT 24
Finished Mar 14 12:57:17 PM PDT 24
Peak memory 210632 kb
Host smart-e19af321-49ac-4f05-99e8-63cf8a1842f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649204622 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.649204622
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.4245741141
Short name T153
Test name
Test status
Simulation time 1575827912603 ps
CPU time 303.8 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:41:38 PM PDT 24
Peak memory 210880 kb
Host smart-1588b7a4-5efa-49be-a211-dbaf409a33a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245741141 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.4245741141
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.691014004
Short name T38
Test name
Test status
Simulation time 617126707920 ps
CPU time 379.06 seconds
Started Mar 14 12:38:08 PM PDT 24
Finished Mar 14 12:44:27 PM PDT 24
Peak memory 202080 kb
Host smart-71f28660-f79e-4c74-ac95-4524a90a0586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691014004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.691014004
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.462927301
Short name T193
Test name
Test status
Simulation time 494109544119 ps
CPU time 287.65 seconds
Started Mar 14 12:35:44 PM PDT 24
Finished Mar 14 12:40:32 PM PDT 24
Peak memory 201660 kb
Host smart-a227eef3-7e06-4f67-a53e-e04ef87980f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462927301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.462927301
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1929024497
Short name T150
Test name
Test status
Simulation time 533468823519 ps
CPU time 327.62 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:39:31 PM PDT 24
Peak memory 202036 kb
Host smart-a487543c-29e9-4bc3-8b82-d334a71c03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929024497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1929024497
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1700487701
Short name T26
Test name
Test status
Simulation time 364693322931 ps
CPU time 439.62 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 202140 kb
Host smart-cd0eff81-41f2-4987-bf0c-af7ae7881553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700487701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1700487701
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3795575062
Short name T68
Test name
Test status
Simulation time 748375936 ps
CPU time 2.02 seconds
Started Mar 14 12:23:55 PM PDT 24
Finished Mar 14 12:23:58 PM PDT 24
Peak memory 209908 kb
Host smart-2e6750e7-3418-4009-8297-9d403486f271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795575062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3795575062
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1712328440
Short name T158
Test name
Test status
Simulation time 489480490919 ps
CPU time 1065.54 seconds
Started Mar 14 12:36:13 PM PDT 24
Finished Mar 14 12:54:00 PM PDT 24
Peak memory 202032 kb
Host smart-304c772c-f65e-4e4d-8a0a-1935ca1a891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712328440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1712328440
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2277799135
Short name T226
Test name
Test status
Simulation time 565227646064 ps
CPU time 666.72 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:45:11 PM PDT 24
Peak memory 202136 kb
Host smart-caf24fd0-b25b-428e-bfbb-63e11757768f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277799135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2277799135
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.506550339
Short name T230
Test name
Test status
Simulation time 513242420914 ps
CPU time 984.66 seconds
Started Mar 14 12:37:05 PM PDT 24
Finished Mar 14 12:53:30 PM PDT 24
Peak memory 202092 kb
Host smart-395f3db8-d927-4b4f-bd0f-caeb07e2ac85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506550339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.506550339
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1704066051
Short name T145
Test name
Test status
Simulation time 438827825714 ps
CPU time 1030.03 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:51:19 PM PDT 24
Peak memory 210592 kb
Host smart-5a1b9d42-0867-49e9-95ca-6e245567c639
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704066051 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1704066051
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3509155229
Short name T416
Test name
Test status
Simulation time 315793475 ps
CPU time 0.99 seconds
Started Mar 14 12:34:13 PM PDT 24
Finished Mar 14 12:34:15 PM PDT 24
Peak memory 201808 kb
Host smart-b930f65c-9323-4be3-a8c1-9136d0f5cdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509155229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3509155229
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2787978803
Short name T39
Test name
Test status
Simulation time 502760479973 ps
CPU time 314.71 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:40:14 PM PDT 24
Peak memory 202180 kb
Host smart-521a4e18-beb5-4fb0-99e2-31ba599978e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787978803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2787978803
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3171443453
Short name T21
Test name
Test status
Simulation time 549096102024 ps
CPU time 219.62 seconds
Started Mar 14 12:36:08 PM PDT 24
Finished Mar 14 12:39:47 PM PDT 24
Peak memory 210740 kb
Host smart-f6c2a836-0369-4ca9-a45b-d9b41ee5eb34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171443453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3171443453
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.351146937
Short name T89
Test name
Test status
Simulation time 4181457314 ps
CPU time 10.77 seconds
Started Mar 14 12:34:08 PM PDT 24
Finished Mar 14 12:34:19 PM PDT 24
Peak memory 217716 kb
Host smart-918f9452-d1af-4461-a4b2-d9b9e4593d4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351146937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.351146937
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3160427338
Short name T245
Test name
Test status
Simulation time 366491402701 ps
CPU time 409.86 seconds
Started Mar 14 12:34:13 PM PDT 24
Finished Mar 14 12:41:04 PM PDT 24
Peak memory 202116 kb
Host smart-e7a7acf5-0756-4887-b8ba-3cee00b2051b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160427338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3160427338
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.112348496
Short name T121
Test name
Test status
Simulation time 437530380 ps
CPU time 1.29 seconds
Started Mar 14 12:21:47 PM PDT 24
Finished Mar 14 12:21:48 PM PDT 24
Peak memory 201548 kb
Host smart-a4f446a7-1de3-4726-9c96-9803f6750a7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112348496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.112348496
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2687965384
Short name T199
Test name
Test status
Simulation time 536992378694 ps
CPU time 538.33 seconds
Started Mar 14 12:34:50 PM PDT 24
Finished Mar 14 12:43:49 PM PDT 24
Peak memory 202112 kb
Host smart-20e752c4-f775-4c13-a4ea-53074d10dc5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687965384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2687965384
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1380019864
Short name T156
Test name
Test status
Simulation time 567708034944 ps
CPU time 923.88 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:51:50 PM PDT 24
Peak memory 202224 kb
Host smart-923227bc-c12f-4f33-bbcc-53c2b524d57d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380019864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1380019864
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.348911267
Short name T144
Test name
Test status
Simulation time 352819002409 ps
CPU time 395.15 seconds
Started Mar 14 12:34:31 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 202072 kb
Host smart-1d98bda6-a1a4-4763-b68f-35c358f9ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348911267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.348911267
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1166377808
Short name T118
Test name
Test status
Simulation time 326569679422 ps
CPU time 695.57 seconds
Started Mar 14 12:36:02 PM PDT 24
Finished Mar 14 12:47:38 PM PDT 24
Peak memory 202104 kb
Host smart-497a4349-0485-4a88-8416-12d8d352a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166377808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1166377808
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1022411078
Short name T309
Test name
Test status
Simulation time 558958266659 ps
CPU time 1357.57 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:56:40 PM PDT 24
Peak memory 202220 kb
Host smart-a8bbb070-4152-4358-adb6-a10610b25c32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022411078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1022411078
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.466640748
Short name T10
Test name
Test status
Simulation time 412178641518 ps
CPU time 517.38 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:43:57 PM PDT 24
Peak memory 202056 kb
Host smart-dbd00bce-27f1-4fbd-b650-3a548ea8b1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466640748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
466640748
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2977379925
Short name T169
Test name
Test status
Simulation time 330310335586 ps
CPU time 67.11 seconds
Started Mar 14 12:38:24 PM PDT 24
Finished Mar 14 12:39:32 PM PDT 24
Peak memory 202080 kb
Host smart-5c3a6d12-7a5e-4447-b0d9-5957f3d1f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977379925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2977379925
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.879573213
Short name T270
Test name
Test status
Simulation time 366436659325 ps
CPU time 798.69 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:47:40 PM PDT 24
Peak memory 202008 kb
Host smart-020383c5-e1a6-43d6-a31b-837122f43da7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879573213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.879573213
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2520676808
Short name T267
Test name
Test status
Simulation time 479501450118 ps
CPU time 1166.49 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 202136 kb
Host smart-9ddda234-2ddd-40cc-8963-89f9c33936ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520676808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2520676808
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3453548027
Short name T178
Test name
Test status
Simulation time 489325601222 ps
CPU time 191.63 seconds
Started Mar 14 12:38:23 PM PDT 24
Finished Mar 14 12:41:35 PM PDT 24
Peak memory 202096 kb
Host smart-ba77e53e-ca86-4dd5-b0a6-5e5d1b866dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453548027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3453548027
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2159918885
Short name T349
Test name
Test status
Simulation time 8334343294 ps
CPU time 7.82 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 201836 kb
Host smart-041067e9-7ee2-4689-9c35-221566fad403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159918885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2159918885
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.626748575
Short name T58
Test name
Test status
Simulation time 1937794528 ps
CPU time 3.05 seconds
Started Mar 14 12:20:33 PM PDT 24
Finished Mar 14 12:20:37 PM PDT 24
Peak memory 201588 kb
Host smart-f6df2a22-6d6f-404e-b190-3cc690d54c17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626748575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.626748575
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3198409713
Short name T285
Test name
Test status
Simulation time 520381620446 ps
CPU time 367.7 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:40:09 PM PDT 24
Peak memory 202080 kb
Host smart-1a51a072-cad9-4905-a648-92ceba8919a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198409713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3198409713
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.387379981
Short name T312
Test name
Test status
Simulation time 343076775841 ps
CPU time 803.74 seconds
Started Mar 14 12:37:16 PM PDT 24
Finished Mar 14 12:50:40 PM PDT 24
Peak memory 202024 kb
Host smart-3e6bf121-3b1a-4888-b20e-918ae9b7e1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387379981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
387379981
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.871338097
Short name T27
Test name
Test status
Simulation time 404915381577 ps
CPU time 833.88 seconds
Started Mar 14 12:36:00 PM PDT 24
Finished Mar 14 12:49:54 PM PDT 24
Peak memory 202124 kb
Host smart-4daa9e1f-6097-477b-8f12-72663e484022
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871338097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.871338097
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2521069619
Short name T239
Test name
Test status
Simulation time 836180192441 ps
CPU time 456.76 seconds
Started Mar 14 12:36:29 PM PDT 24
Finished Mar 14 12:44:06 PM PDT 24
Peak memory 210720 kb
Host smart-f59a56aa-6378-46e4-83ef-37a58953f166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521069619 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2521069619
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2496393248
Short name T292
Test name
Test status
Simulation time 532027363933 ps
CPU time 1105.34 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:55:00 PM PDT 24
Peak memory 202136 kb
Host smart-ecf3ea6d-4dc9-4933-8ae1-0212c1ae18f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496393248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2496393248
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.4097666269
Short name T224
Test name
Test status
Simulation time 163002034341 ps
CPU time 396.15 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 202140 kb
Host smart-e62d3ee7-fdf9-4574-bf96-4c9198212c8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097666269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.4097666269
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2283846774
Short name T189
Test name
Test status
Simulation time 354703046403 ps
CPU time 232.13 seconds
Started Mar 14 12:37:06 PM PDT 24
Finished Mar 14 12:40:58 PM PDT 24
Peak memory 202212 kb
Host smart-a56f42d0-6cf4-4f0e-b281-0328e3ae0b45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283846774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2283846774
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2284549409
Short name T43
Test name
Test status
Simulation time 137356992800 ps
CPU time 261.74 seconds
Started Mar 14 12:37:35 PM PDT 24
Finished Mar 14 12:41:57 PM PDT 24
Peak memory 210812 kb
Host smart-fa3bba3e-51b9-43e6-b05c-c5f88d4b8c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284549409 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2284549409
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1991282437
Short name T179
Test name
Test status
Simulation time 550310267391 ps
CPU time 335.6 seconds
Started Mar 14 12:34:48 PM PDT 24
Finished Mar 14 12:40:25 PM PDT 24
Peak memory 202136 kb
Host smart-a89f6e47-9f7d-41b1-857a-19373a0efc0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991282437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1991282437
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2333008514
Short name T262
Test name
Test status
Simulation time 162895400725 ps
CPU time 401.32 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 202156 kb
Host smart-738abe8b-cc98-4436-8718-2d0eff3352dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333008514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2333008514
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2159177503
Short name T254
Test name
Test status
Simulation time 349984475697 ps
CPU time 835.46 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:49:27 PM PDT 24
Peak memory 202116 kb
Host smart-41593bb6-351c-41bd-b017-4454a3fc793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159177503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2159177503
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3795392618
Short name T217
Test name
Test status
Simulation time 327790410115 ps
CPU time 631.5 seconds
Started Mar 14 12:34:30 PM PDT 24
Finished Mar 14 12:45:02 PM PDT 24
Peak memory 218824 kb
Host smart-b986045a-3c33-4988-b6b6-2303e66e0e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795392618 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3795392618
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3277541805
Short name T268
Test name
Test status
Simulation time 164613410664 ps
CPU time 209.23 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:39:10 PM PDT 24
Peak memory 202128 kb
Host smart-3c9d8b51-b59c-4e54-ae17-8c94290f2cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277541805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3277541805
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.829873312
Short name T252
Test name
Test status
Simulation time 526106553095 ps
CPU time 1187.67 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:55:06 PM PDT 24
Peak memory 202064 kb
Host smart-fb62bb4c-7cc4-43a4-95cc-fc71d4c10b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829873312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.829873312
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1456852184
Short name T61
Test name
Test status
Simulation time 185199602268 ps
CPU time 199.54 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:37:46 PM PDT 24
Peak memory 202064 kb
Host smart-8b265fa6-61a3-4a85-847b-525851f697cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456852184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1456852184
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.929846686
Short name T278
Test name
Test status
Simulation time 518173957696 ps
CPU time 427.78 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:41:08 PM PDT 24
Peak memory 202004 kb
Host smart-1edd0425-2eb4-4b3a-ae26-cc541820a923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929846686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.929846686
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2126293756
Short name T369
Test name
Test status
Simulation time 333956033323 ps
CPU time 579.1 seconds
Started Mar 14 12:34:48 PM PDT 24
Finished Mar 14 12:44:29 PM PDT 24
Peak memory 202136 kb
Host smart-bea5fbcb-a77e-486b-9a4e-997b2411af98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126293756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2126293756
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3298181936
Short name T194
Test name
Test status
Simulation time 582505152233 ps
CPU time 281.88 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:39:52 PM PDT 24
Peak memory 202156 kb
Host smart-2734a92b-003e-478e-9436-ef135ca9c60d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298181936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3298181936
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2549029581
Short name T47
Test name
Test status
Simulation time 372877471102 ps
CPU time 935.83 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:53:23 PM PDT 24
Peak memory 202084 kb
Host smart-56fd9c42-16ca-4042-a607-8c3f3d4e7a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549029581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2549029581
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.407505556
Short name T315
Test name
Test status
Simulation time 350731732563 ps
CPU time 215.09 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:41:35 PM PDT 24
Peak memory 202012 kb
Host smart-4cd60d45-bcd8-4919-ad0a-4b599c839a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407505556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.407505556
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.4228124968
Short name T327
Test name
Test status
Simulation time 491067504481 ps
CPU time 357.73 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:45:13 PM PDT 24
Peak memory 202076 kb
Host smart-c0fb5856-12fb-4bed-95f6-ea7b7719b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228124968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.4228124968
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1921264027
Short name T334
Test name
Test status
Simulation time 504749320230 ps
CPU time 1303.69 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:56:13 PM PDT 24
Peak memory 202052 kb
Host smart-e3291bf2-e70c-45e3-9d3e-8ea17808f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921264027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1921264027
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3289142305
Short name T263
Test name
Test status
Simulation time 174777271104 ps
CPU time 219.36 seconds
Started Mar 14 12:37:32 PM PDT 24
Finished Mar 14 12:41:12 PM PDT 24
Peak memory 202172 kb
Host smart-22457a93-6d12-4005-8672-f950024321ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289142305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3289142305
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2282238480
Short name T336
Test name
Test status
Simulation time 207124713124 ps
CPU time 156.17 seconds
Started Mar 14 12:38:32 PM PDT 24
Finished Mar 14 12:41:08 PM PDT 24
Peak memory 210748 kb
Host smart-1d78cf31-fa99-44cc-a71d-01fd0c2c7e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282238480 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2282238480
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4018581817
Short name T295
Test name
Test status
Simulation time 480489769376 ps
CPU time 596.29 seconds
Started Mar 14 12:38:33 PM PDT 24
Finished Mar 14 12:48:30 PM PDT 24
Peak memory 202152 kb
Host smart-c32285a4-7d3f-4dfe-96f1-ce5c264b71ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018581817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4018581817
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2652783588
Short name T4
Test name
Test status
Simulation time 163040072621 ps
CPU time 390.61 seconds
Started Mar 14 12:39:04 PM PDT 24
Finished Mar 14 12:45:35 PM PDT 24
Peak memory 202112 kb
Host smart-0d7d78d6-f742-415f-83ae-7d1f80ba83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652783588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2652783588
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1124020486
Short name T306
Test name
Test status
Simulation time 31739452720 ps
CPU time 77.6 seconds
Started Mar 14 12:39:17 PM PDT 24
Finished Mar 14 12:40:35 PM PDT 24
Peak memory 210456 kb
Host smart-f0559600-36a2-4811-84ec-2b429ff7fa1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124020486 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1124020486
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.109413664
Short name T829
Test name
Test status
Simulation time 400204015 ps
CPU time 2.02 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 209904 kb
Host smart-13aec974-f877-4a65-907f-a5ceef4538a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109413664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.109413664
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3796051717
Short name T221
Test name
Test status
Simulation time 103906661864 ps
CPU time 376.86 seconds
Started Mar 14 12:35:01 PM PDT 24
Finished Mar 14 12:41:18 PM PDT 24
Peak memory 202400 kb
Host smart-c2a67a63-ade9-446c-9509-7d3c97bac469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796051717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3796051717
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2307501385
Short name T330
Test name
Test status
Simulation time 122142558239 ps
CPU time 136.86 seconds
Started Mar 14 12:35:39 PM PDT 24
Finished Mar 14 12:37:56 PM PDT 24
Peak memory 210728 kb
Host smart-32b223f1-0b7e-48bd-ba6a-9993694563db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307501385 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2307501385
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1172960031
Short name T231
Test name
Test status
Simulation time 162590515135 ps
CPU time 398.78 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:43:05 PM PDT 24
Peak memory 202116 kb
Host smart-3b57c3eb-6a2e-4927-ae26-6e33082fa52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172960031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1172960031
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.3897750874
Short name T62
Test name
Test status
Simulation time 160694716926 ps
CPU time 62.47 seconds
Started Mar 14 12:34:11 PM PDT 24
Finished Mar 14 12:35:13 PM PDT 24
Peak memory 202108 kb
Host smart-ec5036ad-001f-40f2-b93e-1d65ccb13bf8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897750874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.3897750874
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.59187264
Short name T205
Test name
Test status
Simulation time 69782924336 ps
CPU time 402.66 seconds
Started Mar 14 12:35:11 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 202356 kb
Host smart-46f700fd-aca3-4f9c-8bdf-46034acd2e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59187264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.59187264
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3315713024
Short name T253
Test name
Test status
Simulation time 61357002259 ps
CPU time 168.62 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:38:07 PM PDT 24
Peak memory 210860 kb
Host smart-216975fb-be5c-449c-840d-f0d1bbaf3950
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315713024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3315713024
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.76113992
Short name T680
Test name
Test status
Simulation time 3287713922370 ps
CPU time 2283.42 seconds
Started Mar 14 12:35:39 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 210712 kb
Host smart-ae9f71ba-b1c5-466c-924a-032de73317fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76113992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.76113992
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2909960145
Short name T305
Test name
Test status
Simulation time 330869770479 ps
CPU time 189.76 seconds
Started Mar 14 12:36:07 PM PDT 24
Finished Mar 14 12:39:17 PM PDT 24
Peak memory 202036 kb
Host smart-a5dbdcc4-4c4a-4496-b51a-25e3bcc87121
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909960145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2909960145
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2262331088
Short name T119
Test name
Test status
Simulation time 329370948847 ps
CPU time 58.05 seconds
Started Mar 14 12:36:15 PM PDT 24
Finished Mar 14 12:37:13 PM PDT 24
Peak memory 202168 kb
Host smart-5bdf7dd6-b72d-437a-85b1-1378ea181ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262331088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2262331088
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1462773204
Short name T107
Test name
Test status
Simulation time 482913752654 ps
CPU time 571.77 seconds
Started Mar 14 12:37:09 PM PDT 24
Finished Mar 14 12:46:41 PM PDT 24
Peak memory 202004 kb
Host smart-e921b7e1-91b2-487a-ba79-7560bea9e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462773204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1462773204
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2347010615
Short name T319
Test name
Test status
Simulation time 510120063756 ps
CPU time 1271.4 seconds
Started Mar 14 12:37:25 PM PDT 24
Finished Mar 14 12:58:36 PM PDT 24
Peak memory 202144 kb
Host smart-bed46e74-2536-4fe7-965b-a57a58238d0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347010615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2347010615
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.207245244
Short name T271
Test name
Test status
Simulation time 500609517209 ps
CPU time 327.28 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:43:46 PM PDT 24
Peak memory 202080 kb
Host smart-425f379d-7920-4a52-a5fa-5ec868ed4593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207245244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.207245244
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2298626864
Short name T326
Test name
Test status
Simulation time 440363522136 ps
CPU time 274.19 seconds
Started Mar 14 12:39:16 PM PDT 24
Finished Mar 14 12:43:50 PM PDT 24
Peak memory 202124 kb
Host smart-f6fa12c8-0644-486b-a52c-b1134c1a7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298626864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2298626864
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2738653427
Short name T286
Test name
Test status
Simulation time 50953617936 ps
CPU time 179.02 seconds
Started Mar 14 12:39:20 PM PDT 24
Finished Mar 14 12:42:20 PM PDT 24
Peak memory 217888 kb
Host smart-788a364e-04ec-4d3e-a466-bc426f43ec79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738653427 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2738653427
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3310707
Short name T269
Test name
Test status
Simulation time 336784424542 ps
CPU time 445.85 seconds
Started Mar 14 12:34:15 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 202108 kb
Host smart-414c7c28-e679-4f2f-a0cc-7e20cb79f327
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating.3310707
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1334408525
Short name T875
Test name
Test status
Simulation time 4161547929 ps
CPU time 8.72 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 201688 kb
Host smart-179934c5-d91f-4934-a6e3-1a9215b31ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334408525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1334408525
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.124662138
Short name T272
Test name
Test status
Simulation time 329510426059 ps
CPU time 745.49 seconds
Started Mar 14 12:34:48 PM PDT 24
Finished Mar 14 12:47:13 PM PDT 24
Peak memory 202104 kb
Host smart-f455a677-8b09-4fe8-b8c9-0d82dcc4180d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124662138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
124662138
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2862073396
Short name T761
Test name
Test status
Simulation time 166831518469 ps
CPU time 191.96 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:38:13 PM PDT 24
Peak memory 202048 kb
Host smart-f24fea57-d071-47a0-b485-abc434a9c88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862073396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2862073396
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1603369641
Short name T213
Test name
Test status
Simulation time 86782446055 ps
CPU time 444.25 seconds
Started Mar 14 12:35:31 PM PDT 24
Finished Mar 14 12:42:58 PM PDT 24
Peak memory 202404 kb
Host smart-bc2a902a-de83-4cdb-879e-0cc7f87ae281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603369641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1603369641
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3122573242
Short name T332
Test name
Test status
Simulation time 560056321329 ps
CPU time 1279.14 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:56:50 PM PDT 24
Peak memory 202140 kb
Host smart-0fdb1aba-9293-4759-92a1-254fd0b1dedc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122573242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3122573242
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3633908079
Short name T218
Test name
Test status
Simulation time 127693333586 ps
CPU time 409.49 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 212360 kb
Host smart-08a150ba-298b-4167-b7ff-ae5ec7d7af6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633908079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3633908079
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3340159726
Short name T273
Test name
Test status
Simulation time 169334981474 ps
CPU time 50.33 seconds
Started Mar 14 12:36:17 PM PDT 24
Finished Mar 14 12:37:08 PM PDT 24
Peak memory 202100 kb
Host smart-74f22c19-c6d6-4a0d-8e6d-a9b1a3b4799a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340159726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3340159726
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2736898131
Short name T300
Test name
Test status
Simulation time 356441108511 ps
CPU time 223.26 seconds
Started Mar 14 12:36:17 PM PDT 24
Finished Mar 14 12:40:01 PM PDT 24
Peak memory 202092 kb
Host smart-fbc9e523-d21e-4bda-bf78-9709b6b10f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736898131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2736898131
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.4097778528
Short name T297
Test name
Test status
Simulation time 521001402782 ps
CPU time 578.46 seconds
Started Mar 14 12:37:45 PM PDT 24
Finished Mar 14 12:47:24 PM PDT 24
Peak memory 202048 kb
Host smart-7ea69c9f-1ba0-4971-b24c-6178dc22f809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097778528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.4097778528
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.990920285
Short name T304
Test name
Test status
Simulation time 561438693848 ps
CPU time 389.6 seconds
Started Mar 14 12:39:21 PM PDT 24
Finished Mar 14 12:45:52 PM PDT 24
Peak memory 201980 kb
Host smart-c5516cc2-00d4-4d8c-adb0-7dacbe511727
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990920285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.990920285
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1179439879
Short name T848
Test name
Test status
Simulation time 1064643338 ps
CPU time 1.93 seconds
Started Mar 14 12:20:57 PM PDT 24
Finished Mar 14 12:20:59 PM PDT 24
Peak memory 201764 kb
Host smart-f6aefa4a-a49e-4ec6-9451-99a63a6a4717
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179439879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1179439879
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3265413905
Short name T859
Test name
Test status
Simulation time 51817664646 ps
CPU time 62.28 seconds
Started Mar 14 12:19:41 PM PDT 24
Finished Mar 14 12:20:44 PM PDT 24
Peak memory 201704 kb
Host smart-d5a7d612-9a5c-479a-ace9-3344248e0f92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265413905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3265413905
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3095700495
Short name T899
Test name
Test status
Simulation time 713304071 ps
CPU time 2.32 seconds
Started Mar 14 12:19:47 PM PDT 24
Finished Mar 14 12:19:49 PM PDT 24
Peak memory 201452 kb
Host smart-6f568f84-0293-4f31-bc02-f941f1eda2be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095700495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3095700495
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1666041696
Short name T850
Test name
Test status
Simulation time 524557025 ps
CPU time 1.6 seconds
Started Mar 14 12:19:12 PM PDT 24
Finished Mar 14 12:19:14 PM PDT 24
Peak memory 201520 kb
Host smart-0750407a-8735-47bb-99bb-d9c6edf182a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666041696 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1666041696
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2629617711
Short name T60
Test name
Test status
Simulation time 352366440 ps
CPU time 1.56 seconds
Started Mar 14 12:24:59 PM PDT 24
Finished Mar 14 12:25:00 PM PDT 24
Peak memory 201432 kb
Host smart-e95dde5c-31a6-4e94-8820-46a0ca4eeb94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629617711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2629617711
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3031257945
Short name T865
Test name
Test status
Simulation time 375515592 ps
CPU time 1.03 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 201520 kb
Host smart-cc07560e-f1a8-4485-8013-10ebe3280bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031257945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3031257945
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2040050810
Short name T911
Test name
Test status
Simulation time 4483849647 ps
CPU time 9.35 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:32 PM PDT 24
Peak memory 201740 kb
Host smart-6523c545-b1fb-4097-ba31-2b428d3a47ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040050810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2040050810
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.320904360
Short name T903
Test name
Test status
Simulation time 566459072 ps
CPU time 2.28 seconds
Started Mar 14 12:23:40 PM PDT 24
Finished Mar 14 12:23:43 PM PDT 24
Peak memory 201760 kb
Host smart-e66c820d-619c-46c6-8da9-89f570258a20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320904360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.320904360
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2259930827
Short name T70
Test name
Test status
Simulation time 8714363863 ps
CPU time 7.83 seconds
Started Mar 14 12:23:19 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 201568 kb
Host smart-ac9ae8cd-2803-4cf0-926d-4c1ec8a94414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259930827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2259930827
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.409052279
Short name T134
Test name
Test status
Simulation time 964485644 ps
CPU time 2.84 seconds
Started Mar 14 12:20:42 PM PDT 24
Finished Mar 14 12:20:45 PM PDT 24
Peak memory 202068 kb
Host smart-d1abbb01-d136-480a-87e3-ebfdb6e9e78e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409052279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.409052279
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1942216716
Short name T120
Test name
Test status
Simulation time 1151598503 ps
CPU time 5.41 seconds
Started Mar 14 12:20:12 PM PDT 24
Finished Mar 14 12:20:18 PM PDT 24
Peak memory 201728 kb
Host smart-562e6509-7891-49a1-922f-9fe579d18834
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942216716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1942216716
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.853321743
Short name T862
Test name
Test status
Simulation time 1288199960 ps
CPU time 2.32 seconds
Started Mar 14 12:24:13 PM PDT 24
Finished Mar 14 12:24:15 PM PDT 24
Peak memory 200608 kb
Host smart-d6726b33-e5e3-4606-b8ce-ee95e41e226d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853321743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.853321743
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2406452046
Short name T809
Test name
Test status
Simulation time 870108647 ps
CPU time 1.46 seconds
Started Mar 14 12:19:28 PM PDT 24
Finished Mar 14 12:19:29 PM PDT 24
Peak memory 210744 kb
Host smart-7a563960-f0f6-4d45-b862-10ccb4ec8ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406452046 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2406452046
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1317054427
Short name T128
Test name
Test status
Simulation time 352719747 ps
CPU time 1.06 seconds
Started Mar 14 12:21:50 PM PDT 24
Finished Mar 14 12:21:51 PM PDT 24
Peak memory 201484 kb
Host smart-9353d7d1-9f54-49b4-9f2c-f75f3ab139be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317054427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1317054427
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1855591968
Short name T869
Test name
Test status
Simulation time 464190728 ps
CPU time 1.73 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:58 PM PDT 24
Peak memory 201432 kb
Host smart-ebd8c152-c3ba-4ed6-b78d-a6e00c03ebbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855591968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1855591968
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2724613348
Short name T868
Test name
Test status
Simulation time 384347075 ps
CPU time 2.45 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:31 PM PDT 24
Peak memory 200172 kb
Host smart-87dd1522-283c-4365-b546-1d379c5cce76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724613348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2724613348
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1169923601
Short name T65
Test name
Test status
Simulation time 4635788651 ps
CPU time 11.96 seconds
Started Mar 14 12:20:54 PM PDT 24
Finished Mar 14 12:21:06 PM PDT 24
Peak memory 201844 kb
Host smart-ac4f7bc1-45f8-44ae-898e-e92235eceaf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169923601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1169923601
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2498228911
Short name T861
Test name
Test status
Simulation time 565556872 ps
CPU time 1.51 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 200920 kb
Host smart-7a4da846-7f02-48ba-b948-d6039151f325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498228911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2498228911
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2616136712
Short name T821
Test name
Test status
Simulation time 477276053 ps
CPU time 1.18 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 198332 kb
Host smart-8321dd53-8e89-4ceb-ae2b-b2714ba3c5bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616136712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2616136712
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3935502317
Short name T863
Test name
Test status
Simulation time 386645476 ps
CPU time 1.54 seconds
Started Mar 14 12:23:38 PM PDT 24
Finished Mar 14 12:23:40 PM PDT 24
Peak memory 201476 kb
Host smart-c3fd7283-1542-4969-971c-96f0d133d3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935502317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3935502317
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2521025470
Short name T57
Test name
Test status
Simulation time 4931512213 ps
CPU time 10.91 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 200408 kb
Host smart-c7842393-8abb-420e-8a82-96986d225ace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521025470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2521025470
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.902503042
Short name T891
Test name
Test status
Simulation time 7907703158 ps
CPU time 19.65 seconds
Started Mar 14 12:23:58 PM PDT 24
Finished Mar 14 12:24:18 PM PDT 24
Peak memory 200940 kb
Host smart-004f7b02-440d-48bb-aabb-2f3bb664dd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902503042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.902503042
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2430863093
Short name T871
Test name
Test status
Simulation time 637485478 ps
CPU time 1.15 seconds
Started Mar 14 12:24:12 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 201388 kb
Host smart-16db6175-a3a4-4b7e-9b43-e80d5cbb7b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430863093 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2430863093
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.70404993
Short name T907
Test name
Test status
Simulation time 485144672 ps
CPU time 0.99 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 201392 kb
Host smart-37e6a446-5806-49bf-88dc-cca87542fcab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70404993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.70404993
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3930911921
Short name T808
Test name
Test status
Simulation time 470678420 ps
CPU time 0.98 seconds
Started Mar 14 12:24:03 PM PDT 24
Finished Mar 14 12:24:04 PM PDT 24
Peak memory 200704 kb
Host smart-5472c645-dfdd-4f78-a736-5d187fe83f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930911921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3930911921
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1930674953
Short name T136
Test name
Test status
Simulation time 3558124001 ps
CPU time 9.29 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:30 PM PDT 24
Peak memory 201644 kb
Host smart-a172d910-dcde-4bcf-84cb-39e1b9a99b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930674953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1930674953
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1336584818
Short name T75
Test name
Test status
Simulation time 480770925 ps
CPU time 2.23 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:22 PM PDT 24
Peak memory 201708 kb
Host smart-236eb0be-51d2-47d1-a569-c7d481ac0768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336584818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1336584818
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3416318456
Short name T895
Test name
Test status
Simulation time 643210185 ps
CPU time 1.21 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 201464 kb
Host smart-10aa10e0-3687-4fea-a86e-31c81c1cec7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416318456 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3416318456
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.787915729
Short name T905
Test name
Test status
Simulation time 398997059 ps
CPU time 1.03 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 201460 kb
Host smart-1a7aaf98-c55c-4b81-be28-2712a4ddc6c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787915729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.787915729
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.29682462
Short name T819
Test name
Test status
Simulation time 478452097 ps
CPU time 0.93 seconds
Started Mar 14 12:20:48 PM PDT 24
Finished Mar 14 12:20:50 PM PDT 24
Peak memory 201584 kb
Host smart-8032ce49-fc0f-4573-bbbb-b1480a247efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29682462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.29682462
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4105831426
Short name T822
Test name
Test status
Simulation time 2227008589 ps
CPU time 3.29 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 201456 kb
Host smart-ef3941ef-bbb0-4622-b179-9468c2404b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105831426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4105831426
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4169081001
Short name T909
Test name
Test status
Simulation time 390088609 ps
CPU time 2.04 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:22 PM PDT 24
Peak memory 201640 kb
Host smart-cc4d5cab-6092-48ec-a821-cd829a2077d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169081001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4169081001
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.2529474554
Short name T81
Test name
Test status
Simulation time 4473644876 ps
CPU time 12.21 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:33 PM PDT 24
Peak memory 201624 kb
Host smart-f054474d-8728-4c4f-8fe0-6606be8441c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529474554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.2529474554
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1295970848
Short name T99
Test name
Test status
Simulation time 380822641 ps
CPU time 1.62 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 201348 kb
Host smart-0edb7764-3300-457e-90fa-967a9721efd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295970848 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1295970848
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.212411376
Short name T841
Test name
Test status
Simulation time 293722168 ps
CPU time 1.41 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 201480 kb
Host smart-c4258342-5037-4020-a872-3666f733bef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212411376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.212411376
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1805349943
Short name T838
Test name
Test status
Simulation time 537381843 ps
CPU time 1.02 seconds
Started Mar 14 12:22:53 PM PDT 24
Finished Mar 14 12:22:54 PM PDT 24
Peak memory 201592 kb
Host smart-705c8a89-1115-43fa-80c6-fcf948e8f431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805349943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1805349943
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3229112335
Short name T897
Test name
Test status
Simulation time 5245461733 ps
CPU time 6.97 seconds
Started Mar 14 12:24:12 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 201528 kb
Host smart-7c90ddd6-cde8-468f-b627-ed276844c737
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229112335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3229112335
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.48006483
Short name T876
Test name
Test status
Simulation time 709741285 ps
CPU time 3.04 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:38 PM PDT 24
Peak memory 201656 kb
Host smart-a22c7bd4-312b-4ed2-ba8b-318a6b4b7ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48006483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.48006483
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.251555197
Short name T63
Test name
Test status
Simulation time 4530094741 ps
CPU time 4.86 seconds
Started Mar 14 12:20:19 PM PDT 24
Finished Mar 14 12:20:24 PM PDT 24
Peak memory 201840 kb
Host smart-93daac47-4872-4e4a-b7fb-8367d7ee27d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251555197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.251555197
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3844108069
Short name T857
Test name
Test status
Simulation time 677293302 ps
CPU time 1.41 seconds
Started Mar 14 12:23:54 PM PDT 24
Finished Mar 14 12:23:56 PM PDT 24
Peak memory 201440 kb
Host smart-d014ee73-0808-46f2-9526-351a343cfcc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844108069 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3844108069
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2098014047
Short name T126
Test name
Test status
Simulation time 363426014 ps
CPU time 1.28 seconds
Started Mar 14 12:21:51 PM PDT 24
Finished Mar 14 12:21:52 PM PDT 24
Peak memory 201596 kb
Host smart-bdd2a975-d9eb-4517-87a7-804b12cc9082
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098014047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2098014047
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1908745419
Short name T827
Test name
Test status
Simulation time 326741128 ps
CPU time 1.06 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 200136 kb
Host smart-f1cce59e-a5c1-4ce3-aeae-71079921ec98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908745419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1908745419
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.245772364
Short name T881
Test name
Test status
Simulation time 2166600468 ps
CPU time 2.33 seconds
Started Mar 14 12:20:58 PM PDT 24
Finished Mar 14 12:21:01 PM PDT 24
Peak memory 201640 kb
Host smart-2de63235-b554-4b74-a269-3fe1a761c422
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245772364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.245772364
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3599882009
Short name T860
Test name
Test status
Simulation time 1150743552 ps
CPU time 2.98 seconds
Started Mar 14 12:22:50 PM PDT 24
Finished Mar 14 12:22:53 PM PDT 24
Peak memory 201800 kb
Host smart-c9a6d68a-0a1b-43d6-9b94-f4520faf0234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599882009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3599882009
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1131131525
Short name T853
Test name
Test status
Simulation time 4354059909 ps
CPU time 6.37 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:31 PM PDT 24
Peak memory 200752 kb
Host smart-0320b277-4402-4df9-9f2a-fcb7ef51fe79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131131525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1131131525
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1790124345
Short name T866
Test name
Test status
Simulation time 540199923 ps
CPU time 1.29 seconds
Started Mar 14 12:24:17 PM PDT 24
Finished Mar 14 12:24:18 PM PDT 24
Peak memory 201612 kb
Host smart-356c5a3f-cc9c-4fed-a828-8052406e9235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790124345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1790124345
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.466112713
Short name T127
Test name
Test status
Simulation time 416307707 ps
CPU time 1.65 seconds
Started Mar 14 12:20:53 PM PDT 24
Finished Mar 14 12:20:55 PM PDT 24
Peak memory 201548 kb
Host smart-c9687db7-8b83-49e9-ad57-87f6cadb0205
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466112713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.466112713
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1796587884
Short name T890
Test name
Test status
Simulation time 282650402 ps
CPU time 1.27 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:12 PM PDT 24
Peak memory 201168 kb
Host smart-fef10a6f-feab-473a-8243-ef2f8af3589a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796587884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1796587884
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3728713851
Short name T828
Test name
Test status
Simulation time 2428479656 ps
CPU time 1.98 seconds
Started Mar 14 12:23:54 PM PDT 24
Finished Mar 14 12:23:56 PM PDT 24
Peak memory 201476 kb
Host smart-e0d62ddd-ed6d-4093-89b7-6f39f581e669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728713851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3728713851
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1217510090
Short name T840
Test name
Test status
Simulation time 402976177 ps
CPU time 2.81 seconds
Started Mar 14 12:24:25 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 209956 kb
Host smart-e62c2927-1f04-4711-9d54-c60b9b129211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217510090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1217510090
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2692486118
Short name T892
Test name
Test status
Simulation time 4183999721 ps
CPU time 3.04 seconds
Started Mar 14 12:23:28 PM PDT 24
Finished Mar 14 12:23:31 PM PDT 24
Peak memory 201688 kb
Host smart-1224f781-39b7-471a-9eec-63fc3b596b01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692486118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2692486118
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3741010972
Short name T818
Test name
Test status
Simulation time 391642088 ps
CPU time 1.8 seconds
Started Mar 14 12:21:00 PM PDT 24
Finished Mar 14 12:21:02 PM PDT 24
Peak memory 201652 kb
Host smart-0b57dc96-0211-4791-86d9-212c45c67bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741010972 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3741010972
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.1426853079
Short name T130
Test name
Test status
Simulation time 337770238 ps
CPU time 0.95 seconds
Started Mar 14 12:24:17 PM PDT 24
Finished Mar 14 12:24:18 PM PDT 24
Peak memory 201472 kb
Host smart-2d27d02c-1aee-4346-9117-486e748802e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426853079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.1426853079
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2106772669
Short name T826
Test name
Test status
Simulation time 283873197 ps
CPU time 0.96 seconds
Started Mar 14 12:24:16 PM PDT 24
Finished Mar 14 12:24:17 PM PDT 24
Peak memory 201492 kb
Host smart-f6cc8b2c-4ed0-45f1-8115-9d81ab69c843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106772669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2106772669
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3295154013
Short name T830
Test name
Test status
Simulation time 5107350669 ps
CPU time 12.55 seconds
Started Mar 14 12:22:58 PM PDT 24
Finished Mar 14 12:23:11 PM PDT 24
Peak memory 201700 kb
Host smart-a03f356d-c931-43fd-a958-60d37d6c98b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295154013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3295154013
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2643018436
Short name T887
Test name
Test status
Simulation time 499006917 ps
CPU time 2.69 seconds
Started Mar 14 12:22:04 PM PDT 24
Finished Mar 14 12:22:07 PM PDT 24
Peak memory 210020 kb
Host smart-79cb5eff-dc35-4835-b8ef-02f5fbad0375
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643018436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2643018436
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.81886449
Short name T843
Test name
Test status
Simulation time 4248253980 ps
CPU time 11.76 seconds
Started Mar 14 12:24:13 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 201792 kb
Host smart-c6415cf9-d3ab-4f4b-bf44-893b38a5b9a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81886449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_int
g_err.81886449
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3630437965
Short name T901
Test name
Test status
Simulation time 394749710 ps
CPU time 1.74 seconds
Started Mar 14 12:24:10 PM PDT 24
Finished Mar 14 12:24:12 PM PDT 24
Peak memory 200804 kb
Host smart-b4aad4f1-462c-4237-89ad-26a990f51995
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630437965 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3630437965
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1904260592
Short name T137
Test name
Test status
Simulation time 539746373 ps
CPU time 1.98 seconds
Started Mar 14 12:23:46 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 201424 kb
Host smart-fd44c612-6b0f-48ba-b76a-52eb6b52c0d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904260592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1904260592
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4080483596
Short name T872
Test name
Test status
Simulation time 460923741 ps
CPU time 1.81 seconds
Started Mar 14 12:20:29 PM PDT 24
Finished Mar 14 12:20:31 PM PDT 24
Peak memory 201488 kb
Host smart-4a03d2ce-e04f-4065-8e68-de57ce906c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080483596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4080483596
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.423079975
Short name T59
Test name
Test status
Simulation time 2686615348 ps
CPU time 6.42 seconds
Started Mar 14 12:24:27 PM PDT 24
Finished Mar 14 12:24:33 PM PDT 24
Peak memory 201504 kb
Host smart-2934b686-7bc9-4780-9052-2f21009a2bea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423079975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.423079975
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.4163177504
Short name T824
Test name
Test status
Simulation time 543691761 ps
CPU time 2.61 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 201888 kb
Host smart-f2c9bb88-848c-484d-864c-bde2b48fbc29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163177504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.4163177504
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1566184913
Short name T69
Test name
Test status
Simulation time 4270898290 ps
CPU time 10.94 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 201880 kb
Host smart-46574772-d180-4b97-8b84-55234f0e24a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566184913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1566184913
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.427375792
Short name T851
Test name
Test status
Simulation time 519769795 ps
CPU time 2.07 seconds
Started Mar 14 12:20:28 PM PDT 24
Finished Mar 14 12:20:31 PM PDT 24
Peak memory 201540 kb
Host smart-9ed444e7-9d41-4640-8943-1a829a254664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427375792 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.427375792
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4272659123
Short name T884
Test name
Test status
Simulation time 445768689 ps
CPU time 1.1 seconds
Started Mar 14 12:23:27 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 200756 kb
Host smart-9737b767-e601-48c4-94cb-0882095508ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272659123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4272659123
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2310580076
Short name T839
Test name
Test status
Simulation time 378015939 ps
CPU time 0.95 seconds
Started Mar 14 12:20:28 PM PDT 24
Finished Mar 14 12:20:29 PM PDT 24
Peak memory 201592 kb
Host smart-82cbbb51-74fe-4066-983d-1faa64d3f543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310580076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2310580076
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1870140
Short name T832
Test name
Test status
Simulation time 5071416083 ps
CPU time 11.09 seconds
Started Mar 14 12:20:56 PM PDT 24
Finished Mar 14 12:21:07 PM PDT 24
Peak memory 201840 kb
Host smart-94ab25a5-fd2c-443e-96ce-3fe88bf2b9e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctr
l_same_csr_outstanding.1870140
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.610783079
Short name T74
Test name
Test status
Simulation time 521719645 ps
CPU time 2.12 seconds
Started Mar 14 12:23:28 PM PDT 24
Finished Mar 14 12:23:30 PM PDT 24
Peak memory 209656 kb
Host smart-58f6b31d-8823-4cdf-b71f-892efc804590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610783079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.610783079
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.618244779
Short name T908
Test name
Test status
Simulation time 8658554521 ps
CPU time 24.04 seconds
Started Mar 14 12:23:43 PM PDT 24
Finished Mar 14 12:24:07 PM PDT 24
Peak memory 201696 kb
Host smart-6f6ca366-411d-4c6f-b50f-5654b22df6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618244779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.618244779
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1007766817
Short name T904
Test name
Test status
Simulation time 425655348 ps
CPU time 1.33 seconds
Started Mar 14 12:20:34 PM PDT 24
Finished Mar 14 12:20:35 PM PDT 24
Peak memory 201640 kb
Host smart-fae27544-79e2-4795-9f98-7a85edaa4586
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007766817 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1007766817
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3218221812
Short name T132
Test name
Test status
Simulation time 508058317 ps
CPU time 2.08 seconds
Started Mar 14 12:23:46 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 201168 kb
Host smart-f1096524-07ad-4d77-8836-ab82cafea86e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218221812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3218221812
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.25693964
Short name T833
Test name
Test status
Simulation time 401754427 ps
CPU time 0.82 seconds
Started Mar 14 12:21:23 PM PDT 24
Finished Mar 14 12:21:25 PM PDT 24
Peak memory 201868 kb
Host smart-bd561d30-ffa8-4dbe-8011-4f84c2c0b006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.25693964
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1596728219
Short name T873
Test name
Test status
Simulation time 4566518971 ps
CPU time 11.26 seconds
Started Mar 14 12:20:54 PM PDT 24
Finished Mar 14 12:21:05 PM PDT 24
Peak memory 201776 kb
Host smart-1ac5dcd4-ca6d-4a4c-9efd-c8756727609e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596728219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1596728219
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2410428986
Short name T84
Test name
Test status
Simulation time 539800648 ps
CPU time 3.13 seconds
Started Mar 14 12:22:37 PM PDT 24
Finished Mar 14 12:22:40 PM PDT 24
Peak memory 201824 kb
Host smart-e8ae8fc2-14ae-4646-aaf3-dc77bfa76e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410428986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2410428986
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.440951321
Short name T64
Test name
Test status
Simulation time 4544714559 ps
CPU time 12.53 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 201408 kb
Host smart-e965ac9a-db1f-4c79-a292-d0faeb7102f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440951321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.440951321
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.962391069
Short name T123
Test name
Test status
Simulation time 979341555 ps
CPU time 5.32 seconds
Started Mar 14 12:21:15 PM PDT 24
Finished Mar 14 12:21:20 PM PDT 24
Peak memory 201764 kb
Host smart-807bd338-6b5b-4c40-9902-3e84e95f91e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962391069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.962391069
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2803060979
Short name T125
Test name
Test status
Simulation time 6932554979 ps
CPU time 5.27 seconds
Started Mar 14 12:20:48 PM PDT 24
Finished Mar 14 12:20:53 PM PDT 24
Peak memory 201712 kb
Host smart-f7bb635b-2b33-445a-9fdd-cba453e217bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803060979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2803060979
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.187928997
Short name T846
Test name
Test status
Simulation time 703527622 ps
CPU time 2.48 seconds
Started Mar 14 12:21:09 PM PDT 24
Finished Mar 14 12:21:12 PM PDT 24
Peak memory 201488 kb
Host smart-4d5d9496-df1d-476c-88fc-ec16180ccff3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187928997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.187928997
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3942565368
Short name T82
Test name
Test status
Simulation time 634920202 ps
CPU time 1.44 seconds
Started Mar 14 12:21:34 PM PDT 24
Finished Mar 14 12:21:36 PM PDT 24
Peak memory 201612 kb
Host smart-29b1bfc8-1e84-46d8-82a2-4055807d595c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942565368 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3942565368
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3416288413
Short name T817
Test name
Test status
Simulation time 484847752 ps
CPU time 1.08 seconds
Started Mar 14 12:22:23 PM PDT 24
Finished Mar 14 12:22:24 PM PDT 24
Peak memory 201868 kb
Host smart-82d420cc-cc56-44db-81e3-3231115c9c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416288413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3416288413
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1033417777
Short name T138
Test name
Test status
Simulation time 1926582464 ps
CPU time 8.22 seconds
Started Mar 14 12:23:48 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 201224 kb
Host smart-92fe7e4b-1564-40c0-b195-c963a6d29a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033417777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1033417777
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2141267869
Short name T87
Test name
Test status
Simulation time 7783415715 ps
CPU time 11.83 seconds
Started Mar 14 12:23:32 PM PDT 24
Finished Mar 14 12:23:44 PM PDT 24
Peak memory 201496 kb
Host smart-f734febe-f1d2-4a23-94aa-99eccb252b20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141267869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2141267869
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.108672455
Short name T896
Test name
Test status
Simulation time 515387818 ps
CPU time 1.92 seconds
Started Mar 14 12:20:34 PM PDT 24
Finished Mar 14 12:20:36 PM PDT 24
Peak memory 201588 kb
Host smart-fc2bee35-b0e2-4f62-9e1d-06f1de8f88d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108672455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.108672455
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1807387112
Short name T852
Test name
Test status
Simulation time 290441838 ps
CPU time 1.35 seconds
Started Mar 14 12:20:54 PM PDT 24
Finished Mar 14 12:20:55 PM PDT 24
Peak memory 201492 kb
Host smart-9ec81d17-b846-48a4-a863-fa2af6a55e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807387112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1807387112
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4142214082
Short name T855
Test name
Test status
Simulation time 433700225 ps
CPU time 1.17 seconds
Started Mar 14 12:23:43 PM PDT 24
Finished Mar 14 12:23:44 PM PDT 24
Peak memory 201460 kb
Host smart-0375af5b-2eaf-47e6-a2ec-a4ab7a45866f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142214082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4142214082
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3510937167
Short name T877
Test name
Test status
Simulation time 359514665 ps
CPU time 0.96 seconds
Started Mar 14 12:24:27 PM PDT 24
Finished Mar 14 12:24:28 PM PDT 24
Peak memory 201456 kb
Host smart-57948a13-da23-4353-b5c6-c9f23c204b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510937167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3510937167
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2182668209
Short name T798
Test name
Test status
Simulation time 313894965 ps
CPU time 1.06 seconds
Started Mar 14 12:23:42 PM PDT 24
Finished Mar 14 12:23:44 PM PDT 24
Peak memory 200104 kb
Host smart-3c1570f1-5e1c-473b-ada0-e4eabaa3c781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182668209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2182668209
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1991072286
Short name T910
Test name
Test status
Simulation time 438932030 ps
CPU time 1.28 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:12 PM PDT 24
Peak memory 201172 kb
Host smart-323028c5-b821-47da-bd9e-3f2be2ac27ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991072286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1991072286
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1359057096
Short name T800
Test name
Test status
Simulation time 563722405 ps
CPU time 0.75 seconds
Started Mar 14 12:23:28 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 201176 kb
Host smart-2d3df0c5-ec01-4ad1-8bd2-1c1b72309525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359057096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1359057096
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1612958450
Short name T823
Test name
Test status
Simulation time 513581549 ps
CPU time 1.6 seconds
Started Mar 14 12:23:50 PM PDT 24
Finished Mar 14 12:23:52 PM PDT 24
Peak memory 201424 kb
Host smart-6a33c351-f7d7-420f-be83-9b2e6d26a98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612958450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1612958450
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1408430716
Short name T902
Test name
Test status
Simulation time 562517865 ps
CPU time 0.77 seconds
Started Mar 14 12:23:50 PM PDT 24
Finished Mar 14 12:23:51 PM PDT 24
Peak memory 201428 kb
Host smart-8d9f9471-27bb-463c-aa56-bc22f8787bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408430716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1408430716
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2369326406
Short name T814
Test name
Test status
Simulation time 509383282 ps
CPU time 0.93 seconds
Started Mar 14 12:23:50 PM PDT 24
Finished Mar 14 12:23:51 PM PDT 24
Peak memory 201424 kb
Host smart-be6be516-9bb4-4a42-88b8-42cfa092b98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369326406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2369326406
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.911347177
Short name T847
Test name
Test status
Simulation time 1368738396 ps
CPU time 4.96 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:24:01 PM PDT 24
Peak memory 201656 kb
Host smart-1c284017-c5a1-400e-81bb-8dbe7e221f69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911347177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.911347177
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.298240951
Short name T133
Test name
Test status
Simulation time 5144725218 ps
CPU time 4.12 seconds
Started Mar 14 12:22:24 PM PDT 24
Finished Mar 14 12:22:28 PM PDT 24
Peak memory 201776 kb
Host smart-489e5802-c9df-4584-93cd-9404596eded0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298240951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.298240951
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2692409738
Short name T143
Test name
Test status
Simulation time 1227988752 ps
CPU time 3.71 seconds
Started Mar 14 12:22:11 PM PDT 24
Finished Mar 14 12:22:15 PM PDT 24
Peak memory 201468 kb
Host smart-5dc031c6-67d1-4832-93bb-b878a4c5bdb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692409738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2692409738
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3399892473
Short name T820
Test name
Test status
Simulation time 446488024 ps
CPU time 1.56 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:51 PM PDT 24
Peak memory 200628 kb
Host smart-0916a9b6-d9c0-469b-a7ae-99382282f7aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399892473 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3399892473
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.652924479
Short name T135
Test name
Test status
Simulation time 373539300 ps
CPU time 0.92 seconds
Started Mar 14 12:19:45 PM PDT 24
Finished Mar 14 12:19:46 PM PDT 24
Peak memory 201468 kb
Host smart-f1a7b54b-a23a-458e-bf58-cc9618b7df30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652924479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.652924479
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.126641825
Short name T811
Test name
Test status
Simulation time 489117655 ps
CPU time 0.96 seconds
Started Mar 14 12:22:53 PM PDT 24
Finished Mar 14 12:22:54 PM PDT 24
Peak memory 201584 kb
Host smart-f3b67e08-bf82-4a5a-86f8-65759a66106a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126641825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.126641825
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1800381129
Short name T139
Test name
Test status
Simulation time 4064638329 ps
CPU time 3.68 seconds
Started Mar 14 12:19:41 PM PDT 24
Finished Mar 14 12:19:45 PM PDT 24
Peak memory 201836 kb
Host smart-7ad54851-8580-44c9-be7e-cc3b525fe03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800381129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1800381129
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.314758427
Short name T83
Test name
Test status
Simulation time 367681237 ps
CPU time 3.04 seconds
Started Mar 14 12:20:20 PM PDT 24
Finished Mar 14 12:20:23 PM PDT 24
Peak memory 201736 kb
Host smart-5a951fa9-f49c-441b-bcf7-4003e5e67e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314758427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.314758427
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3184760981
Short name T350
Test name
Test status
Simulation time 8500018287 ps
CPU time 7.33 seconds
Started Mar 14 12:22:47 PM PDT 24
Finished Mar 14 12:22:54 PM PDT 24
Peak memory 201836 kb
Host smart-c75e5083-a5a9-48b1-90cd-9545209a0403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184760981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3184760981
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3495210982
Short name T882
Test name
Test status
Simulation time 531320298 ps
CPU time 1.33 seconds
Started Mar 14 12:22:37 PM PDT 24
Finished Mar 14 12:22:39 PM PDT 24
Peak memory 201592 kb
Host smart-0173605e-793d-47bd-97e4-a1d4334ac42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495210982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3495210982
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.802571446
Short name T812
Test name
Test status
Simulation time 374548625 ps
CPU time 1.49 seconds
Started Mar 14 12:23:28 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 201176 kb
Host smart-a51afa45-0f13-4e0e-8426-6e07ef2297a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802571446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.802571446
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.4181310966
Short name T900
Test name
Test status
Simulation time 473523699 ps
CPU time 1.71 seconds
Started Mar 14 12:23:45 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 200648 kb
Host smart-d8163162-9866-438d-a840-9b25482e9caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181310966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.4181310966
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4012096686
Short name T888
Test name
Test status
Simulation time 300482367 ps
CPU time 1.3 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:41 PM PDT 24
Peak memory 201232 kb
Host smart-4a328e49-3694-4f90-b5ee-64d29e963deb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012096686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4012096686
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3803161197
Short name T836
Test name
Test status
Simulation time 425052998 ps
CPU time 1.16 seconds
Started Mar 14 12:24:16 PM PDT 24
Finished Mar 14 12:24:17 PM PDT 24
Peak memory 201476 kb
Host smart-fa6c4cba-388c-41dd-a36a-b4b8b1461091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803161197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3803161197
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1135401954
Short name T816
Test name
Test status
Simulation time 430872255 ps
CPU time 0.9 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:41 PM PDT 24
Peak memory 200580 kb
Host smart-143815bc-6779-41f9-84cb-6c3dafb0cfe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135401954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1135401954
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3502611536
Short name T810
Test name
Test status
Simulation time 318409014 ps
CPU time 1.45 seconds
Started Mar 14 12:20:39 PM PDT 24
Finished Mar 14 12:20:41 PM PDT 24
Peak memory 201872 kb
Host smart-783229ae-7c92-4450-b0da-7eb73bc603b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502611536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3502611536
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4006361121
Short name T801
Test name
Test status
Simulation time 476390002 ps
CPU time 0.86 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 201436 kb
Host smart-9bae84e1-2384-44fc-8bb9-6e27c7824277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006361121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4006361121
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.800779362
Short name T805
Test name
Test status
Simulation time 381754900 ps
CPU time 0.88 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 201432 kb
Host smart-c15687fa-3920-4089-8055-903ace12505c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800779362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.800779362
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1494129268
Short name T845
Test name
Test status
Simulation time 309192380 ps
CPU time 0.81 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 201468 kb
Host smart-9df52fdb-d451-47ae-881c-62b79e717d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494129268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1494129268
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2453489521
Short name T131
Test name
Test status
Simulation time 496490344 ps
CPU time 2.51 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:26 PM PDT 24
Peak memory 201644 kb
Host smart-a7dcaf31-bee1-4677-a691-4d9ad61927d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453489521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2453489521
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.545590229
Short name T129
Test name
Test status
Simulation time 17040415018 ps
CPU time 59.85 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:25:22 PM PDT 24
Peak memory 201764 kb
Host smart-a5c6ae68-65fa-42ce-a859-40cce480f8f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545590229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.545590229
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3170520793
Short name T124
Test name
Test status
Simulation time 962145345 ps
CPU time 2.95 seconds
Started Mar 14 12:19:08 PM PDT 24
Finished Mar 14 12:19:12 PM PDT 24
Peak memory 201428 kb
Host smart-5582cbe5-3e76-4f9c-b6fc-b3b318c1333d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170520793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3170520793
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2236367191
Short name T109
Test name
Test status
Simulation time 575861903 ps
CPU time 1.15 seconds
Started Mar 14 12:23:35 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 200496 kb
Host smart-502cea10-5e65-4629-a848-140c9cff8370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236367191 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2236367191
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3747043818
Short name T886
Test name
Test status
Simulation time 418141175 ps
CPU time 1.28 seconds
Started Mar 14 12:24:05 PM PDT 24
Finished Mar 14 12:24:07 PM PDT 24
Peak memory 200736 kb
Host smart-159e61cd-0d24-408c-93b3-3fea9f409940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747043818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3747043818
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3811448458
Short name T803
Test name
Test status
Simulation time 391056985 ps
CPU time 1.45 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 201464 kb
Host smart-f3b1a1c0-66ea-4f3d-b00c-b80535fcb108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811448458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3811448458
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2869235394
Short name T834
Test name
Test status
Simulation time 2325457690 ps
CPU time 1.92 seconds
Started Mar 14 12:19:04 PM PDT 24
Finished Mar 14 12:19:06 PM PDT 24
Peak memory 201632 kb
Host smart-813fb58c-d118-4212-9bd9-a6ed6b309e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869235394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2869235394
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2736968685
Short name T894
Test name
Test status
Simulation time 789443440 ps
CPU time 2.04 seconds
Started Mar 14 12:20:58 PM PDT 24
Finished Mar 14 12:21:01 PM PDT 24
Peak memory 201828 kb
Host smart-17818047-946e-44bb-befc-1e11ee825aff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736968685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2736968685
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1651027272
Short name T883
Test name
Test status
Simulation time 8017379459 ps
CPU time 19.07 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:43 PM PDT 24
Peak memory 201756 kb
Host smart-e32841e6-1011-4d1c-9097-5ccd2f42b2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651027272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1651027272
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.524229568
Short name T807
Test name
Test status
Simulation time 294861448 ps
CPU time 0.98 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 201472 kb
Host smart-42ec78e7-7358-4080-8e55-df402d88f7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524229568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.524229568
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2405712989
Short name T880
Test name
Test status
Simulation time 383839358 ps
CPU time 1.55 seconds
Started Mar 14 12:24:14 PM PDT 24
Finished Mar 14 12:24:16 PM PDT 24
Peak memory 200196 kb
Host smart-b27f75bf-2495-4a83-aad9-d2f104e84327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405712989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2405712989
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4211477390
Short name T878
Test name
Test status
Simulation time 475812700 ps
CPU time 0.81 seconds
Started Mar 14 12:21:38 PM PDT 24
Finished Mar 14 12:21:38 PM PDT 24
Peak memory 201488 kb
Host smart-17d297d7-f868-4ecc-b7ef-da1ade8a7958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211477390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.4211477390
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1564587105
Short name T804
Test name
Test status
Simulation time 324446614 ps
CPU time 1.45 seconds
Started Mar 14 12:24:15 PM PDT 24
Finished Mar 14 12:24:16 PM PDT 24
Peak memory 201184 kb
Host smart-c90fd0c2-0a4d-40c7-a1f9-cce8ff4c60fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564587105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1564587105
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1060285998
Short name T837
Test name
Test status
Simulation time 288777536 ps
CPU time 1.34 seconds
Started Mar 14 12:24:30 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 201464 kb
Host smart-3fcf25bd-c07a-478d-91cd-54b7ddfe64f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060285998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1060285998
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.503161852
Short name T842
Test name
Test status
Simulation time 462250394 ps
CPU time 1.7 seconds
Started Mar 14 12:22:32 PM PDT 24
Finished Mar 14 12:22:33 PM PDT 24
Peak memory 201588 kb
Host smart-e44ae37e-ef64-4ad8-b180-02f3fd0ee440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503161852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.503161852
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.678413150
Short name T813
Test name
Test status
Simulation time 443285161 ps
CPU time 1.63 seconds
Started Mar 14 12:24:29 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 201464 kb
Host smart-1c5039a7-2590-4556-ba4a-6b9cabadd169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678413150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.678413150
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1159866820
Short name T799
Test name
Test status
Simulation time 386855900 ps
CPU time 0.94 seconds
Started Mar 14 12:24:14 PM PDT 24
Finished Mar 14 12:24:16 PM PDT 24
Peak memory 200184 kb
Host smart-01f7278b-7749-4d92-a6de-7cb3736be7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159866820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1159866820
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2298297134
Short name T802
Test name
Test status
Simulation time 488729684 ps
CPU time 0.83 seconds
Started Mar 14 12:21:14 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 201488 kb
Host smart-e3f5164c-b85c-462f-b1cb-4cbc6a98ff99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298297134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2298297134
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2356230582
Short name T867
Test name
Test status
Simulation time 521453115 ps
CPU time 0.99 seconds
Started Mar 14 12:23:45 PM PDT 24
Finished Mar 14 12:23:47 PM PDT 24
Peak memory 200000 kb
Host smart-91438eb7-bbac-41f1-9e73-46d0bf5b5122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356230582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2356230582
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.385363735
Short name T906
Test name
Test status
Simulation time 494309656 ps
CPU time 1.27 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 200228 kb
Host smart-edd8b7d4-6d42-4731-948e-01bfa3416dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385363735 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.385363735
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2431409937
Short name T831
Test name
Test status
Simulation time 496417852 ps
CPU time 1.82 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:14 PM PDT 24
Peak memory 200020 kb
Host smart-68eda6f9-330a-4a8a-ada5-9ded8717c01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431409937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2431409937
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.795973380
Short name T806
Test name
Test status
Simulation time 335750900 ps
CPU time 0.81 seconds
Started Mar 14 12:23:26 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 201336 kb
Host smart-6a885742-5bed-48e1-9c96-7bd242a9b9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795973380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.795973380
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2306137879
Short name T854
Test name
Test status
Simulation time 2478660472 ps
CPU time 7.85 seconds
Started Mar 14 12:19:42 PM PDT 24
Finished Mar 14 12:19:51 PM PDT 24
Peak memory 201656 kb
Host smart-1825d605-8b65-4cb1-8b2e-928de6c73d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306137879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2306137879
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1135496987
Short name T77
Test name
Test status
Simulation time 514038220 ps
CPU time 1.26 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 201492 kb
Host smart-f3f19a43-dc0c-4173-83ef-ee4ea3e6ae41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135496987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1135496987
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.762699503
Short name T856
Test name
Test status
Simulation time 660116617 ps
CPU time 1.41 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 200688 kb
Host smart-b95268e9-c345-4beb-b10f-e36130b1b8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762699503 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.762699503
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.612177041
Short name T825
Test name
Test status
Simulation time 434424877 ps
CPU time 1.81 seconds
Started Mar 14 12:21:44 PM PDT 24
Finished Mar 14 12:21:46 PM PDT 24
Peak memory 201592 kb
Host smart-8dbc07a3-6be4-4967-809e-e9cdb970b54c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612177041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.612177041
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4197880440
Short name T844
Test name
Test status
Simulation time 280813528 ps
CPU time 1.36 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 199124 kb
Host smart-c0f80d95-3294-44e1-9226-8361e6eaf213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197880440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4197880440
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2765946932
Short name T140
Test name
Test status
Simulation time 2342071128 ps
CPU time 6.48 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:18 PM PDT 24
Peak memory 200268 kb
Host smart-71015b45-79ba-4146-91da-e862a20422da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765946932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2765946932
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.433079801
Short name T858
Test name
Test status
Simulation time 548511102 ps
CPU time 3.46 seconds
Started Mar 14 12:21:45 PM PDT 24
Finished Mar 14 12:21:49 PM PDT 24
Peak memory 201852 kb
Host smart-8023cfaf-b850-45c1-9970-a5cc3d33cbac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433079801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.433079801
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.675634200
Short name T889
Test name
Test status
Simulation time 4015120606 ps
CPU time 2.82 seconds
Started Mar 14 12:24:12 PM PDT 24
Finished Mar 14 12:24:15 PM PDT 24
Peak memory 201424 kb
Host smart-04252eb5-65dc-4022-8b7f-f64d086a3378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675634200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.675634200
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3836587878
Short name T86
Test name
Test status
Simulation time 649097658 ps
CPU time 1.33 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 199472 kb
Host smart-de9d4668-c24f-4f29-a96e-87d0f1e0a818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836587878 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3836587878
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1051249890
Short name T122
Test name
Test status
Simulation time 424245666 ps
CPU time 0.98 seconds
Started Mar 14 12:24:12 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 200224 kb
Host smart-c65d64af-0285-4299-950f-5b939bfc5e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051249890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1051249890
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2772550457
Short name T815
Test name
Test status
Simulation time 460413282 ps
CPU time 1.78 seconds
Started Mar 14 12:23:26 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 201188 kb
Host smart-f9f0a238-6a7b-4554-99cc-6674c57cbd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772550457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2772550457
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1362726589
Short name T141
Test name
Test status
Simulation time 2614141983 ps
CPU time 9.21 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:49 PM PDT 24
Peak memory 201508 kb
Host smart-6d60f95c-0094-452f-a7d1-bfa3b937df17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362726589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1362726589
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2590113145
Short name T885
Test name
Test status
Simulation time 498618933 ps
CPU time 1.87 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 200352 kb
Host smart-6689a98b-2d6a-4135-8ccd-1b9370e72abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590113145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2590113145
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1057162657
Short name T898
Test name
Test status
Simulation time 4714068283 ps
CPU time 2.92 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 200672 kb
Host smart-ba47ec2c-fd7f-4176-b631-4999f65b958e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057162657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1057162657
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3244570865
Short name T85
Test name
Test status
Simulation time 558495131 ps
CPU time 1.02 seconds
Started Mar 14 12:19:47 PM PDT 24
Finished Mar 14 12:19:48 PM PDT 24
Peak memory 201656 kb
Host smart-1bc0d50f-50e6-489e-a1c9-f7c3bc130997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244570865 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3244570865
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1586400314
Short name T142
Test name
Test status
Simulation time 366671651 ps
CPU time 0.97 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:13 PM PDT 24
Peak memory 198532 kb
Host smart-ce72ff64-a5f9-476f-8e3a-2515430f35e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586400314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1586400314
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2807306730
Short name T870
Test name
Test status
Simulation time 350358276 ps
CPU time 1.14 seconds
Started Mar 14 12:19:44 PM PDT 24
Finished Mar 14 12:19:46 PM PDT 24
Peak memory 201468 kb
Host smart-3b51a64f-311d-46d3-8e30-24265cc9b001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807306730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2807306730
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.4147061061
Short name T893
Test name
Test status
Simulation time 2388553490 ps
CPU time 2.26 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 200624 kb
Host smart-ff05b114-f267-468f-8425-34a0c54ccafb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147061061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.4147061061
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.554408857
Short name T78
Test name
Test status
Simulation time 801385270 ps
CPU time 2.37 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 201428 kb
Host smart-6349f07a-8f4d-40a0-9900-3a7466734168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554408857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.554408857
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1152236156
Short name T76
Test name
Test status
Simulation time 7684993937 ps
CPU time 19.5 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:45 PM PDT 24
Peak memory 201560 kb
Host smart-2fa64b81-ea0c-48d9-90f6-a00ecebbb426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152236156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1152236156
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3689286416
Short name T874
Test name
Test status
Simulation time 473587323 ps
CPU time 1.32 seconds
Started Mar 14 12:23:40 PM PDT 24
Finished Mar 14 12:23:41 PM PDT 24
Peak memory 201528 kb
Host smart-fb7999af-017f-4a44-9edd-ba8daef48acd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689286416 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3689286416
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4065374327
Short name T879
Test name
Test status
Simulation time 415728797 ps
CPU time 0.96 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:41 PM PDT 24
Peak memory 201452 kb
Host smart-1e202dd6-7e2f-4f2b-9722-3724f7771f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065374327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4065374327
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3947370003
Short name T849
Test name
Test status
Simulation time 311515349 ps
CPU time 0.85 seconds
Started Mar 14 12:23:24 PM PDT 24
Finished Mar 14 12:23:25 PM PDT 24
Peak memory 199912 kb
Host smart-fa4b77d1-a71f-40b4-980c-b2c2be284900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947370003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3947370003
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3818358756
Short name T835
Test name
Test status
Simulation time 4654920155 ps
CPU time 18.94 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:31 PM PDT 24
Peak memory 199572 kb
Host smart-7ed48fe6-588b-4d92-bf21-f5f1b882656b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818358756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3818358756
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1774639313
Short name T864
Test name
Test status
Simulation time 1171685046 ps
CPU time 2.66 seconds
Started Mar 14 12:24:11 PM PDT 24
Finished Mar 14 12:24:14 PM PDT 24
Peak memory 214772 kb
Host smart-4f539a3f-14c8-4f0d-acd4-4a9ff00a0ada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774639313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1774639313
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3163528822
Short name T348
Test name
Test status
Simulation time 4582948944 ps
CPU time 7.17 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:33 PM PDT 24
Peak memory 201448 kb
Host smart-119dd6bf-9ee0-4c70-ae79-9e597cbb3734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163528822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3163528822
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1809834570
Short name T481
Test name
Test status
Simulation time 408570126 ps
CPU time 0.73 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:34:02 PM PDT 24
Peak memory 201720 kb
Host smart-9a999887-f2ed-4139-ad11-453fac9eaa4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809834570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1809834570
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.482940579
Short name T586
Test name
Test status
Simulation time 165979082179 ps
CPU time 28 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:34:33 PM PDT 24
Peak memory 202092 kb
Host smart-f223ce40-0751-4a2c-a8ce-415092af9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482940579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.482940579
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1259731605
Short name T541
Test name
Test status
Simulation time 325023378642 ps
CPU time 673.16 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:45:17 PM PDT 24
Peak memory 202108 kb
Host smart-f264db60-cbed-41f1-ada1-6d5ac2373f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259731605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1259731605
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.559077063
Short name T452
Test name
Test status
Simulation time 325220489203 ps
CPU time 818.36 seconds
Started Mar 14 12:34:06 PM PDT 24
Finished Mar 14 12:47:44 PM PDT 24
Peak memory 202068 kb
Host smart-04bbf843-1c1f-497b-963d-ae48ea6fa6e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=559077063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.559077063
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1465401299
Short name T764
Test name
Test status
Simulation time 328654310654 ps
CPU time 150.07 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:36:34 PM PDT 24
Peak memory 202216 kb
Host smart-60478ac1-7668-4399-89db-7592baad69f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465401299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1465401299
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3647208527
Short name T160
Test name
Test status
Simulation time 327945340756 ps
CPU time 198.66 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:37:24 PM PDT 24
Peak memory 202104 kb
Host smart-f25c769d-ad48-48e4-a700-35784b313b88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647208527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3647208527
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2812707855
Short name T7
Test name
Test status
Simulation time 389467781232 ps
CPU time 238.23 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:37:58 PM PDT 24
Peak memory 202072 kb
Host smart-89528974-04e0-46d7-93aa-e325a277da86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812707855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2812707855
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3801994542
Short name T216
Test name
Test status
Simulation time 93674274427 ps
CPU time 458.68 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 202368 kb
Host smart-d835eabd-a8b5-449a-a985-856ee3ab23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801994542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3801994542
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.780564890
Short name T561
Test name
Test status
Simulation time 31096919867 ps
CPU time 36.14 seconds
Started Mar 14 12:34:06 PM PDT 24
Finished Mar 14 12:34:43 PM PDT 24
Peak memory 201960 kb
Host smart-0c130952-3f3b-454a-b954-d4ec928654aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780564890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.780564890
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1044946125
Short name T499
Test name
Test status
Simulation time 4374237087 ps
CPU time 11.11 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:34:14 PM PDT 24
Peak memory 201900 kb
Host smart-bd017919-cb68-4bb5-90e9-d586304f6833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044946125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1044946125
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.33184934
Short name T588
Test name
Test status
Simulation time 5917590527 ps
CPU time 8.02 seconds
Started Mar 14 12:34:10 PM PDT 24
Finished Mar 14 12:34:19 PM PDT 24
Peak memory 201952 kb
Host smart-68dfe99b-ed73-44cd-90f3-4fd9e1ab3fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33184934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.33184934
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1079252561
Short name T781
Test name
Test status
Simulation time 111671641641 ps
CPU time 595.16 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:44:00 PM PDT 24
Peak memory 211704 kb
Host smart-a382922e-b6e3-4a9f-9d97-b6e40ca84861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079252561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1079252561
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.841061973
Short name T24
Test name
Test status
Simulation time 27977300319 ps
CPU time 52.01 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:34:52 PM PDT 24
Peak memory 210468 kb
Host smart-fa2e2d02-5cc1-479e-a674-aaef829e3d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841061973 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.841061973
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.346746516
Short name T244
Test name
Test status
Simulation time 360320383132 ps
CPU time 707.24 seconds
Started Mar 14 12:34:10 PM PDT 24
Finished Mar 14 12:45:57 PM PDT 24
Peak memory 202136 kb
Host smart-7ee1717b-6e52-4881-8431-06b03780e3de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346746516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.346746516
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3527712234
Short name T752
Test name
Test status
Simulation time 157892516163 ps
CPU time 358.69 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:40:02 PM PDT 24
Peak memory 202192 kb
Host smart-7babe936-b748-4d29-8e9b-6a9604bfc70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527712234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3527712234
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2216122022
Short name T560
Test name
Test status
Simulation time 167125511010 ps
CPU time 77.98 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:35:16 PM PDT 24
Peak memory 202060 kb
Host smart-70568470-1287-408f-b926-6f1c935d58c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216122022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2216122022
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3752074172
Short name T677
Test name
Test status
Simulation time 169464614706 ps
CPU time 98.6 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:35:38 PM PDT 24
Peak memory 202128 kb
Host smart-cac32b2b-4f65-4c77-91c6-0435c4ccf234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752074172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3752074172
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.322298237
Short name T117
Test name
Test status
Simulation time 165997410290 ps
CPU time 111.93 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:35:56 PM PDT 24
Peak memory 202108 kb
Host smart-9e360574-c774-4cb4-bf2d-a7b3f55557ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=322298237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.322298237
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2249693797
Short name T698
Test name
Test status
Simulation time 178322807556 ps
CPU time 393.92 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:40:36 PM PDT 24
Peak memory 202060 kb
Host smart-93d58b76-b7f8-4c52-a3a3-ba2710ce3eae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249693797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2249693797
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1511662236
Short name T581
Test name
Test status
Simulation time 198889800172 ps
CPU time 141.85 seconds
Started Mar 14 12:34:08 PM PDT 24
Finished Mar 14 12:36:30 PM PDT 24
Peak memory 202156 kb
Host smart-22802861-e623-4b50-baa9-7ad32bbcfba8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511662236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1511662236
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1897946115
Short name T691
Test name
Test status
Simulation time 97732827224 ps
CPU time 551.06 seconds
Started Mar 14 12:34:10 PM PDT 24
Finished Mar 14 12:43:21 PM PDT 24
Peak memory 202484 kb
Host smart-f9ea2c4b-1755-46d4-89b7-beac1d0fd04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897946115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1897946115
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1367345091
Short name T728
Test name
Test status
Simulation time 27362165216 ps
CPU time 31.32 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:34:30 PM PDT 24
Peak memory 201908 kb
Host smart-41bf4da8-fc51-4663-8a6a-76e6fc97aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367345091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1367345091
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1260366739
Short name T397
Test name
Test status
Simulation time 5381634887 ps
CPU time 7.14 seconds
Started Mar 14 12:34:28 PM PDT 24
Finished Mar 14 12:34:35 PM PDT 24
Peak memory 201928 kb
Host smart-772ab214-7716-4fdd-918d-fe78532a0b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260366739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1260366739
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1952984760
Short name T71
Test name
Test status
Simulation time 4112740493 ps
CPU time 3.48 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:17 PM PDT 24
Peak memory 217620 kb
Host smart-ba814fd9-97e1-4b24-a360-22c01513669d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952984760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1952984760
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2765542020
Short name T439
Test name
Test status
Simulation time 5756922662 ps
CPU time 3.84 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:34:06 PM PDT 24
Peak memory 201864 kb
Host smart-c27d85f2-87d4-47a1-a8f8-c60306937f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765542020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2765542020
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3959159880
Short name T639
Test name
Test status
Simulation time 324419960 ps
CPU time 1.03 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:34:40 PM PDT 24
Peak memory 201860 kb
Host smart-7705d6f0-0f7a-43b0-b94e-c8024cba5c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959159880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3959159880
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2764490696
Short name T301
Test name
Test status
Simulation time 167945722982 ps
CPU time 394.31 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:41:11 PM PDT 24
Peak memory 202092 kb
Host smart-650b1ebb-ec14-423b-8de1-fc3cab441177
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764490696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2764490696
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3793943023
Short name T697
Test name
Test status
Simulation time 379635908738 ps
CPU time 813.63 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:48:08 PM PDT 24
Peak memory 202120 kb
Host smart-1bf8780b-758a-43ed-ba6a-04606476086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793943023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3793943023
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3016599599
Short name T260
Test name
Test status
Simulation time 331062799943 ps
CPU time 378.53 seconds
Started Mar 14 12:34:35 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 202228 kb
Host smart-31ca5340-147c-4f34-8700-337cd628b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016599599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3016599599
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1067671866
Short name T506
Test name
Test status
Simulation time 334393910937 ps
CPU time 376.1 seconds
Started Mar 14 12:35:36 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 200672 kb
Host smart-4c9423c8-f3ba-406d-9ed5-47dcdfb80e45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067671866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1067671866
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1838589545
Short name T636
Test name
Test status
Simulation time 488386490252 ps
CPU time 335.77 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:41:26 PM PDT 24
Peak memory 201700 kb
Host smart-fe38aced-18aa-4706-9467-66a11baf24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838589545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1838589545
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1181679894
Short name T556
Test name
Test status
Simulation time 326624236533 ps
CPU time 369.95 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:40:40 PM PDT 24
Peak memory 201968 kb
Host smart-b8c94398-6729-4728-855c-780ca7bd85b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181679894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1181679894
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2376428769
Short name T604
Test name
Test status
Simulation time 440183667248 ps
CPU time 517.84 seconds
Started Mar 14 12:34:35 PM PDT 24
Finished Mar 14 12:43:13 PM PDT 24
Peak memory 202116 kb
Host smart-38122bc3-df68-4e74-9f4b-32249a0619e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376428769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2376428769
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1400672830
Short name T566
Test name
Test status
Simulation time 412467332735 ps
CPU time 166.18 seconds
Started Mar 14 12:34:32 PM PDT 24
Finished Mar 14 12:37:18 PM PDT 24
Peak memory 202220 kb
Host smart-e71699a4-39c4-489a-9252-84f2d5ef252d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400672830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1400672830
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2966375613
Short name T658
Test name
Test status
Simulation time 92028910539 ps
CPU time 351.29 seconds
Started Mar 14 12:34:44 PM PDT 24
Finished Mar 14 12:40:36 PM PDT 24
Peak memory 202376 kb
Host smart-93514a8c-b912-4fbd-8719-5ca43dd59dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966375613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2966375613
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3265455341
Short name T678
Test name
Test status
Simulation time 30190817716 ps
CPU time 68.94 seconds
Started Mar 14 12:34:35 PM PDT 24
Finished Mar 14 12:35:44 PM PDT 24
Peak memory 201956 kb
Host smart-e5caa1ff-cb78-4e5b-8f0c-cc19ed15d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265455341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3265455341
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2640303230
Short name T97
Test name
Test status
Simulation time 4047893121 ps
CPU time 10.31 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:36:01 PM PDT 24
Peak memory 201508 kb
Host smart-0b51c514-67c0-41bf-a43f-f07f5957e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640303230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2640303230
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.866364559
Short name T367
Test name
Test status
Simulation time 5857349385 ps
CPU time 3.22 seconds
Started Mar 14 12:34:35 PM PDT 24
Finished Mar 14 12:34:38 PM PDT 24
Peak memory 201928 kb
Host smart-8ee5a262-3e16-4ab0-91d8-8e4c3e06778f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866364559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.866364559
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1168480878
Short name T23
Test name
Test status
Simulation time 62379892589 ps
CPU time 268.53 seconds
Started Mar 14 12:34:40 PM PDT 24
Finished Mar 14 12:39:10 PM PDT 24
Peak memory 210752 kb
Host smart-e7940f5a-df14-416c-88a5-2d7921928ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168480878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1168480878
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3204134640
Short name T429
Test name
Test status
Simulation time 382514801 ps
CPU time 0.81 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:34:39 PM PDT 24
Peak memory 201912 kb
Host smart-ee8c43e3-979e-4849-b558-dfbc99132cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204134640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3204134640
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3206566566
Short name T152
Test name
Test status
Simulation time 519221631049 ps
CPU time 59.58 seconds
Started Mar 14 12:34:41 PM PDT 24
Finished Mar 14 12:35:43 PM PDT 24
Peak memory 202192 kb
Host smart-7700bd2a-fa50-4519-81df-84eb388930cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206566566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3206566566
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.267004188
Short name T793
Test name
Test status
Simulation time 332667572811 ps
CPU time 789.63 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:47:49 PM PDT 24
Peak memory 202052 kb
Host smart-07dbbd8f-f43b-4b91-819a-4989afcbb65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267004188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.267004188
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2272904989
Short name T474
Test name
Test status
Simulation time 496324472700 ps
CPU time 555.17 seconds
Started Mar 14 12:34:42 PM PDT 24
Finished Mar 14 12:43:59 PM PDT 24
Peak memory 201996 kb
Host smart-f4507144-639c-42e5-bbba-b9ab87c18161
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272904989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2272904989
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1147283586
Short name T716
Test name
Test status
Simulation time 324275202665 ps
CPU time 337.46 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:40:16 PM PDT 24
Peak memory 202212 kb
Host smart-ad562f8b-5310-4378-b62a-4ff237554713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147283586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1147283586
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2668812641
Short name T627
Test name
Test status
Simulation time 490285292188 ps
CPU time 1105.04 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:53:04 PM PDT 24
Peak memory 202028 kb
Host smart-4d2a3e9d-09c2-4da9-aba4-74ef5a49f8d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668812641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2668812641
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3297527321
Short name T718
Test name
Test status
Simulation time 357972424277 ps
CPU time 398.76 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:41:17 PM PDT 24
Peak memory 202124 kb
Host smart-f5010983-3527-4ad4-b03f-513d3a5ce335
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297527321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3297527321
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2158026569
Short name T501
Test name
Test status
Simulation time 184091044998 ps
CPU time 227.03 seconds
Started Mar 14 12:34:42 PM PDT 24
Finished Mar 14 12:38:31 PM PDT 24
Peak memory 201624 kb
Host smart-8b0008f7-bea0-4eab-939c-4b9178033754
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158026569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2158026569
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.987103485
Short name T531
Test name
Test status
Simulation time 91688396348 ps
CPU time 522.87 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:43:22 PM PDT 24
Peak memory 202396 kb
Host smart-8c03b3a7-67bb-487a-8ed8-6f9ced612186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987103485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.987103485
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1891886140
Short name T730
Test name
Test status
Simulation time 25965202943 ps
CPU time 30.83 seconds
Started Mar 14 12:34:47 PM PDT 24
Finished Mar 14 12:35:18 PM PDT 24
Peak memory 201924 kb
Host smart-6efd26ae-9065-495c-bcf7-e87baa14c6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891886140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1891886140
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.10369576
Short name T589
Test name
Test status
Simulation time 4675494867 ps
CPU time 3.57 seconds
Started Mar 14 12:34:40 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 201892 kb
Host smart-3f475583-6bc4-4095-9d84-ce3a3648fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10369576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.10369576
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.834855687
Short name T562
Test name
Test status
Simulation time 5543015488 ps
CPU time 4.16 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:34:42 PM PDT 24
Peak memory 201956 kb
Host smart-7b334a84-96c6-42f3-bc18-caa06b6fba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834855687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.834855687
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.923712878
Short name T331
Test name
Test status
Simulation time 386033474430 ps
CPU time 66.15 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:35:44 PM PDT 24
Peak memory 202148 kb
Host smart-398a563e-ee78-4d78-b404-4a8abc8ac6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923712878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
923712878
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.971447710
Short name T289
Test name
Test status
Simulation time 107267181922 ps
CPU time 131.85 seconds
Started Mar 14 12:34:42 PM PDT 24
Finished Mar 14 12:36:55 PM PDT 24
Peak memory 218068 kb
Host smart-a6dd0810-dfb7-40fd-9bf4-007490613949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971447710 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.971447710
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1537408207
Short name T497
Test name
Test status
Simulation time 335511571 ps
CPU time 1.43 seconds
Started Mar 14 12:34:51 PM PDT 24
Finished Mar 14 12:34:55 PM PDT 24
Peak memory 201888 kb
Host smart-d98f05fa-2a39-4452-8604-12b9be419375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537408207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1537408207
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2602107150
Short name T283
Test name
Test status
Simulation time 376116994727 ps
CPU time 558.36 seconds
Started Mar 14 12:34:49 PM PDT 24
Finished Mar 14 12:44:08 PM PDT 24
Peak memory 202172 kb
Host smart-27de15e9-4d9c-443d-b812-3fc909d65ce8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602107150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2602107150
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1066765050
Short name T92
Test name
Test status
Simulation time 363962424109 ps
CPU time 220.19 seconds
Started Mar 14 12:34:49 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 202112 kb
Host smart-b4880638-e78a-4711-a594-b61c8929b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066765050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1066765050
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3606384415
Short name T236
Test name
Test status
Simulation time 167047961082 ps
CPU time 411.23 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:42:42 PM PDT 24
Peak memory 201772 kb
Host smart-799a49aa-6480-44d1-883e-0ac6edc971f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606384415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3606384415
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1103216976
Short name T161
Test name
Test status
Simulation time 328233989461 ps
CPU time 737.46 seconds
Started Mar 14 12:34:39 PM PDT 24
Finished Mar 14 12:46:57 PM PDT 24
Peak memory 202080 kb
Host smart-90a9072c-80be-4e6b-98eb-7eecbfbe2ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103216976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1103216976
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1337121108
Short name T441
Test name
Test status
Simulation time 161479709854 ps
CPU time 359.73 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:40:38 PM PDT 24
Peak memory 202044 kb
Host smart-c8dce820-6536-44c4-82fb-c4d7ef6f019f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337121108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1337121108
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1409206469
Short name T379
Test name
Test status
Simulation time 600952122062 ps
CPU time 1479.64 seconds
Started Mar 14 12:34:49 PM PDT 24
Finished Mar 14 12:59:29 PM PDT 24
Peak memory 202228 kb
Host smart-c4905e47-402d-45cb-8638-c3921d18c85b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409206469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1409206469
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2613698125
Short name T492
Test name
Test status
Simulation time 87344280071 ps
CPU time 372.15 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:42:22 PM PDT 24
Peak memory 202288 kb
Host smart-f2257000-5d6e-46b3-9ff3-09a9d0b84c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613698125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2613698125
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.4180291962
Short name T465
Test name
Test status
Simulation time 47251658186 ps
CPU time 30.44 seconds
Started Mar 14 12:34:47 PM PDT 24
Finished Mar 14 12:35:18 PM PDT 24
Peak memory 201924 kb
Host smart-8411084f-3850-4f91-ab82-1a463f5be19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180291962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.4180291962
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.595796328
Short name T410
Test name
Test status
Simulation time 4568796146 ps
CPU time 3.18 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:36:13 PM PDT 24
Peak memory 201764 kb
Host smart-7e6542b2-422d-4d1c-ace3-7c7dda653914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595796328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.595796328
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3920327981
Short name T784
Test name
Test status
Simulation time 6017643560 ps
CPU time 15.57 seconds
Started Mar 14 12:34:38 PM PDT 24
Finished Mar 14 12:34:54 PM PDT 24
Peak memory 202028 kb
Host smart-6851ae47-3842-4d4c-a5ed-6cfcf7462bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920327981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3920327981
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3959051412
Short name T726
Test name
Test status
Simulation time 152567507539 ps
CPU time 152.54 seconds
Started Mar 14 12:34:51 PM PDT 24
Finished Mar 14 12:37:26 PM PDT 24
Peak memory 210768 kb
Host smart-17fb843c-36a8-4312-8c9a-a385f87a11a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959051412 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3959051412
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1644654532
Short name T681
Test name
Test status
Simulation time 307861957 ps
CPU time 1.31 seconds
Started Mar 14 12:34:58 PM PDT 24
Finished Mar 14 12:35:00 PM PDT 24
Peak memory 201836 kb
Host smart-9e184f20-0c38-4c97-962c-a0bb516e98d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644654532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1644654532
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1929411322
Short name T710
Test name
Test status
Simulation time 325418032612 ps
CPU time 695.09 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:46:35 PM PDT 24
Peak memory 202200 kb
Host smart-d4e43c7b-0d82-4561-b6d7-49f9a8b3b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929411322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1929411322
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3657461103
Short name T299
Test name
Test status
Simulation time 493230858299 ps
CPU time 1271.5 seconds
Started Mar 14 12:34:49 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 202124 kb
Host smart-10d93e89-d1dc-4732-a3f2-6a01a4ffa851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657461103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3657461103
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3900657365
Short name T482
Test name
Test status
Simulation time 329592407356 ps
CPU time 193.61 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 201948 kb
Host smart-056b237e-f0f0-4960-991d-3ea9004d65ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900657365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3900657365
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1646014844
Short name T321
Test name
Test status
Simulation time 166603824899 ps
CPU time 33.03 seconds
Started Mar 14 12:34:47 PM PDT 24
Finished Mar 14 12:35:20 PM PDT 24
Peak memory 202084 kb
Host smart-4a67422d-dd77-4e6a-84bb-c45177ff5764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646014844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1646014844
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.4011804706
Short name T368
Test name
Test status
Simulation time 484831059726 ps
CPU time 303.2 seconds
Started Mar 14 12:34:49 PM PDT 24
Finished Mar 14 12:39:53 PM PDT 24
Peak memory 202152 kb
Host smart-a41042cc-8a3b-4b66-a7bc-1fe494a9788f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011804706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.4011804706
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1524206560
Short name T583
Test name
Test status
Simulation time 218243155863 ps
CPU time 331.47 seconds
Started Mar 14 12:34:51 PM PDT 24
Finished Mar 14 12:40:23 PM PDT 24
Peak memory 202152 kb
Host smart-2cdf7c73-e5ab-42b8-a271-f6682a122fc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524206560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1524206560
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2823300676
Short name T459
Test name
Test status
Simulation time 197170608562 ps
CPU time 207.22 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:39:37 PM PDT 24
Peak memory 201924 kb
Host smart-22f4ffe9-39e4-48af-8d17-80e543311366
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823300676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2823300676
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3341129141
Short name T649
Test name
Test status
Simulation time 92817991295 ps
CPU time 353.16 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:40:53 PM PDT 24
Peak memory 202320 kb
Host smart-209f996d-6fbc-4c95-8403-ddfa423bda01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341129141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3341129141
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3468645276
Short name T582
Test name
Test status
Simulation time 21697273053 ps
CPU time 24.13 seconds
Started Mar 14 12:35:02 PM PDT 24
Finished Mar 14 12:35:26 PM PDT 24
Peak memory 201764 kb
Host smart-eabef285-53d4-4824-bfe2-1dddc1908db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468645276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3468645276
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.620187825
Short name T412
Test name
Test status
Simulation time 4177113790 ps
CPU time 3.35 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:35:03 PM PDT 24
Peak memory 201868 kb
Host smart-231eb545-4066-42fc-a042-03931d2bff85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620187825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.620187825
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2294530373
Short name T407
Test name
Test status
Simulation time 5967508610 ps
CPU time 3.89 seconds
Started Mar 14 12:34:51 PM PDT 24
Finished Mar 14 12:34:55 PM PDT 24
Peak memory 201892 kb
Host smart-0fc0b3b2-d127-48ed-8101-2218d4098052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294530373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2294530373
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3628825760
Short name T420
Test name
Test status
Simulation time 177492517408 ps
CPU time 385.1 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:41:24 PM PDT 24
Peak memory 202140 kb
Host smart-e32f6828-ba4a-47b4-bca0-8fec680b2930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628825760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3628825760
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2512211483
Short name T287
Test name
Test status
Simulation time 30692233066 ps
CPU time 82.43 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:36:22 PM PDT 24
Peak memory 210812 kb
Host smart-3e22a18b-c7ce-4daf-aad1-5aa98760781a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512211483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2512211483
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2258011244
Short name T446
Test name
Test status
Simulation time 377589165 ps
CPU time 1.54 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:35:12 PM PDT 24
Peak memory 201868 kb
Host smart-6c363595-32ea-470f-bc85-b513887cba0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258011244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2258011244
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1844902343
Short name T736
Test name
Test status
Simulation time 323830983349 ps
CPU time 728.02 seconds
Started Mar 14 12:35:02 PM PDT 24
Finished Mar 14 12:47:10 PM PDT 24
Peak memory 202064 kb
Host smart-a68b2000-b893-403b-bea8-08fe2d87686b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844902343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1844902343
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2622308041
Short name T656
Test name
Test status
Simulation time 328250121704 ps
CPU time 723.32 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:47:04 PM PDT 24
Peak memory 202184 kb
Host smart-268a8fe5-e73f-4e36-af2b-76cd1199a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622308041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2622308041
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2404240148
Short name T413
Test name
Test status
Simulation time 343193807084 ps
CPU time 736.44 seconds
Started Mar 14 12:35:02 PM PDT 24
Finished Mar 14 12:47:18 PM PDT 24
Peak memory 202196 kb
Host smart-44bc4a21-3bbd-4eb5-a983-6b6bf63f15aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404240148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2404240148
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2794031378
Short name T739
Test name
Test status
Simulation time 373982176891 ps
CPU time 238.57 seconds
Started Mar 14 12:34:59 PM PDT 24
Finished Mar 14 12:38:58 PM PDT 24
Peak memory 202112 kb
Host smart-f3648179-03ed-4481-bce5-11c009fcc799
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794031378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2794031378
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.559682336
Short name T425
Test name
Test status
Simulation time 613448062801 ps
CPU time 364.23 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:41:05 PM PDT 24
Peak memory 202128 kb
Host smart-124b6947-3fab-4fcf-bb61-b09464d2c8e2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559682336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.559682336
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3250586347
Short name T773
Test name
Test status
Simulation time 25772589004 ps
CPU time 62.03 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:36:02 PM PDT 24
Peak memory 201924 kb
Host smart-f5b2a675-789a-4e10-8bd4-836764a24012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250586347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3250586347
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1009153729
Short name T769
Test name
Test status
Simulation time 3700363146 ps
CPU time 9.1 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:35:09 PM PDT 24
Peak memory 201908 kb
Host smart-48aae8cc-40ce-4f29-ab71-5085d735cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009153729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1009153729
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3395330895
Short name T741
Test name
Test status
Simulation time 5912684676 ps
CPU time 4.01 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:35:04 PM PDT 24
Peak memory 201768 kb
Host smart-95908538-194c-40d3-a78c-d516f5ffeca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395330895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3395330895
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1468020579
Short name T732
Test name
Test status
Simulation time 173769391074 ps
CPU time 100.26 seconds
Started Mar 14 12:35:14 PM PDT 24
Finished Mar 14 12:36:55 PM PDT 24
Peak memory 202072 kb
Host smart-699411a7-b3ee-407a-adcf-9444e417aab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468020579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1468020579
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3736096010
Short name T753
Test name
Test status
Simulation time 78890988163 ps
CPU time 166.14 seconds
Started Mar 14 12:35:00 PM PDT 24
Finished Mar 14 12:37:46 PM PDT 24
Peak memory 210828 kb
Host smart-7c1a75b5-1b28-49c1-b6db-4bd5ac719b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736096010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3736096010
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2527156196
Short name T103
Test name
Test status
Simulation time 312734867 ps
CPU time 0.95 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:35:11 PM PDT 24
Peak memory 201776 kb
Host smart-2837d3b5-4326-4aba-af68-8652d1d567af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527156196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2527156196
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2831896928
Short name T241
Test name
Test status
Simulation time 386277341549 ps
CPU time 76.66 seconds
Started Mar 14 12:35:11 PM PDT 24
Finished Mar 14 12:36:28 PM PDT 24
Peak memory 202104 kb
Host smart-79a3acd7-3d92-4c37-bad8-61153fc97f5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831896928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2831896928
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3507128705
Short name T264
Test name
Test status
Simulation time 168338514229 ps
CPU time 45.36 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:35:56 PM PDT 24
Peak memory 202200 kb
Host smart-71cff1eb-1940-4531-b936-ec385472957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507128705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3507128705
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1272132029
Short name T181
Test name
Test status
Simulation time 326948743119 ps
CPU time 181.5 seconds
Started Mar 14 12:35:08 PM PDT 24
Finished Mar 14 12:38:10 PM PDT 24
Peak memory 202140 kb
Host smart-489c6466-e7b0-45e3-9240-ce9d9afdaf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272132029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1272132029
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.322441336
Short name T464
Test name
Test status
Simulation time 486566481611 ps
CPU time 422.95 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:42:13 PM PDT 24
Peak memory 202064 kb
Host smart-3833406a-5bc3-418f-be82-2d7bed3e5b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=322441336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.322441336
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3066664729
Short name T48
Test name
Test status
Simulation time 488205298080 ps
CPU time 548.76 seconds
Started Mar 14 12:35:08 PM PDT 24
Finished Mar 14 12:44:18 PM PDT 24
Peak memory 202060 kb
Host smart-8a2447fe-a14a-4fd8-a32c-fca85da4942d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066664729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3066664729
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1957420095
Short name T620
Test name
Test status
Simulation time 326831663953 ps
CPU time 745.03 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:47:36 PM PDT 24
Peak memory 202200 kb
Host smart-d563d79d-72fb-4bad-ad2c-89bd95c0740c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957420095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1957420095
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2566248170
Short name T644
Test name
Test status
Simulation time 559716701029 ps
CPU time 687.62 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:46:38 PM PDT 24
Peak memory 202088 kb
Host smart-c4e1d5e2-9abf-4be4-a636-e6f5f8ff3cb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566248170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2566248170
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2487581707
Short name T520
Test name
Test status
Simulation time 413934364805 ps
CPU time 218.27 seconds
Started Mar 14 12:35:11 PM PDT 24
Finished Mar 14 12:38:49 PM PDT 24
Peak memory 202244 kb
Host smart-4abc7949-c2a0-4418-8256-03b213cc6c56
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487581707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2487581707
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3428436574
Short name T417
Test name
Test status
Simulation time 36143948303 ps
CPU time 21.55 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:35:31 PM PDT 24
Peak memory 201912 kb
Host smart-d31f8fcd-5f15-4fa1-a35d-3c210e5b21c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428436574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3428436574
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4040164103
Short name T364
Test name
Test status
Simulation time 3127157974 ps
CPU time 2.56 seconds
Started Mar 14 12:35:12 PM PDT 24
Finished Mar 14 12:35:15 PM PDT 24
Peak memory 201848 kb
Host smart-457638b6-e858-4588-ab9b-7c4b02851c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040164103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4040164103
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.26054393
Short name T708
Test name
Test status
Simulation time 6010217958 ps
CPU time 16.1 seconds
Started Mar 14 12:35:12 PM PDT 24
Finished Mar 14 12:35:28 PM PDT 24
Peak memory 201888 kb
Host smart-91526803-ce9f-4caf-98e2-83b8c4b79ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26054393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.26054393
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2854527699
Short name T632
Test name
Test status
Simulation time 231656613999 ps
CPU time 532.38 seconds
Started Mar 14 12:35:12 PM PDT 24
Finished Mar 14 12:44:05 PM PDT 24
Peak memory 213208 kb
Host smart-f56d8ed2-d919-4260-8fe5-c810e4bc70cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854527699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2854527699
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2842590151
Short name T15
Test name
Test status
Simulation time 65061950332 ps
CPU time 118.95 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:37:08 PM PDT 24
Peak memory 210824 kb
Host smart-be4e4425-7c3f-48e9-a69d-97e7d4f56815
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842590151 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2842590151
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1649950596
Short name T640
Test name
Test status
Simulation time 426330742 ps
CPU time 0.89 seconds
Started Mar 14 12:35:20 PM PDT 24
Finished Mar 14 12:35:21 PM PDT 24
Peak memory 201864 kb
Host smart-88f6059f-543f-4f96-8f5a-a5bea9168dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649950596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1649950596
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1713844562
Short name T652
Test name
Test status
Simulation time 161419851737 ps
CPU time 107.65 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:36:57 PM PDT 24
Peak memory 202180 kb
Host smart-fb05cb18-4118-4f4b-845a-fd7c0c0c5a66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713844562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1713844562
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3205665571
Short name T662
Test name
Test status
Simulation time 166008852133 ps
CPU time 86.84 seconds
Started Mar 14 12:35:09 PM PDT 24
Finished Mar 14 12:36:37 PM PDT 24
Peak memory 202176 kb
Host smart-9de4c0a6-3144-431b-863a-4e1f579afa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205665571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3205665571
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2249297383
Short name T242
Test name
Test status
Simulation time 169692611680 ps
CPU time 189.95 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:38:20 PM PDT 24
Peak memory 202272 kb
Host smart-0873747c-029e-4c3a-8de2-52ed148aac23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249297383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2249297383
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3690271462
Short name T422
Test name
Test status
Simulation time 166300426284 ps
CPU time 189.73 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:38:20 PM PDT 24
Peak memory 202116 kb
Host smart-ea4b5c38-cbce-4bc6-84c3-6547e0c595af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690271462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3690271462
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2736367996
Short name T274
Test name
Test status
Simulation time 327872738838 ps
CPU time 363.3 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 202140 kb
Host smart-e440d137-f83c-414c-8e20-a8e928e51745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736367996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2736367996
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2712871086
Short name T106
Test name
Test status
Simulation time 491775243598 ps
CPU time 545.57 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:44:16 PM PDT 24
Peak memory 202192 kb
Host smart-fc22b2e7-97d0-44d2-b95d-629e7ca0742a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712871086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2712871086
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1956854817
Short name T448
Test name
Test status
Simulation time 404433362993 ps
CPU time 252.87 seconds
Started Mar 14 12:35:10 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 202148 kb
Host smart-63913f3c-82a2-481c-8675-0ca4bf2340bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956854817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1956854817
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.236018772
Short name T9
Test name
Test status
Simulation time 99862726046 ps
CPU time 383.68 seconds
Started Mar 14 12:35:20 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 202420 kb
Host smart-73ee9189-c320-4bea-bcd7-5b0e417d1ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236018772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.236018772
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.430981356
Short name T389
Test name
Test status
Simulation time 39455773520 ps
CPU time 91.35 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:36:50 PM PDT 24
Peak memory 201856 kb
Host smart-23f877dc-95cf-45f9-a6d7-6c28d6617ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430981356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.430981356
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2885338522
Short name T466
Test name
Test status
Simulation time 5202372178 ps
CPU time 7.01 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:35:26 PM PDT 24
Peak memory 201936 kb
Host smart-fdb6370d-428f-416e-a0df-96cc359c949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885338522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2885338522
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3881020623
Short name T557
Test name
Test status
Simulation time 6033460546 ps
CPU time 14.37 seconds
Started Mar 14 12:35:11 PM PDT 24
Finished Mar 14 12:35:25 PM PDT 24
Peak memory 201888 kb
Host smart-4f8be8bd-ea0f-406e-b679-f7ea3c26d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881020623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3881020623
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.86355223
Short name T495
Test name
Test status
Simulation time 415749340 ps
CPU time 1.07 seconds
Started Mar 14 12:35:20 PM PDT 24
Finished Mar 14 12:35:22 PM PDT 24
Peak memory 201892 kb
Host smart-6c3876cc-b9e8-46f3-a096-8cc895b9e501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86355223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.86355223
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4086461756
Short name T259
Test name
Test status
Simulation time 162396184136 ps
CPU time 386.06 seconds
Started Mar 14 12:35:20 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 202036 kb
Host smart-5bff1ee9-68a8-4bb4-b73b-895789364776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086461756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4086461756
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1004499537
Short name T477
Test name
Test status
Simulation time 161100552463 ps
CPU time 185.19 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:38:24 PM PDT 24
Peak memory 202076 kb
Host smart-93efb0c1-465d-4632-980a-16190083a33e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004499537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1004499537
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2795786428
Short name T613
Test name
Test status
Simulation time 165230840351 ps
CPU time 385.12 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 202108 kb
Host smart-b079f132-f92c-4ef6-9cc1-677054008d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795786428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2795786428
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2747860626
Short name T757
Test name
Test status
Simulation time 329132013864 ps
CPU time 195.49 seconds
Started Mar 14 12:35:17 PM PDT 24
Finished Mar 14 12:38:33 PM PDT 24
Peak memory 202192 kb
Host smart-8ca7614d-b5c4-4133-b010-f1f1b63dc731
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747860626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2747860626
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1995283503
Short name T471
Test name
Test status
Simulation time 167554435045 ps
CPU time 97.54 seconds
Started Mar 14 12:35:23 PM PDT 24
Finished Mar 14 12:37:01 PM PDT 24
Peak memory 202120 kb
Host smart-8b9a8548-22f6-4a29-87a0-8fc252ead191
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995283503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1995283503
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1997404337
Short name T734
Test name
Test status
Simulation time 602639087591 ps
CPU time 1472.92 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:59:52 PM PDT 24
Peak memory 202228 kb
Host smart-566daf58-48ed-4e17-8f83-350f9e626dea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997404337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1997404337
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.267133794
Short name T618
Test name
Test status
Simulation time 61314094214 ps
CPU time 248.18 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:39:27 PM PDT 24
Peak memory 202464 kb
Host smart-1811df41-8d8f-4ae2-9048-9f4dc6a56833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267133794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.267133794
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2478534643
Short name T190
Test name
Test status
Simulation time 29521023486 ps
CPU time 70.5 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:36:30 PM PDT 24
Peak memory 201956 kb
Host smart-cc9eece0-b42d-44c4-be51-1562d05d76ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478534643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2478534643
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2456470402
Short name T509
Test name
Test status
Simulation time 3656153049 ps
CPU time 2.88 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:35:22 PM PDT 24
Peak memory 201928 kb
Host smart-2bea8044-b3da-4d2c-aafe-b5cd6a038754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456470402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2456470402
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3834326998
Short name T400
Test name
Test status
Simulation time 5837137597 ps
CPU time 4.42 seconds
Started Mar 14 12:35:19 PM PDT 24
Finished Mar 14 12:35:24 PM PDT 24
Peak memory 201936 kb
Host smart-6454939d-a4b9-44ba-9e94-a6c3765e9a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834326998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3834326998
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.439440197
Short name T114
Test name
Test status
Simulation time 171728507794 ps
CPU time 199.37 seconds
Started Mar 14 12:35:21 PM PDT 24
Finished Mar 14 12:38:41 PM PDT 24
Peak memory 202124 kb
Host smart-3f5d127e-8665-452d-aa0e-8b61a5e88f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439440197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
439440197
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3956459961
Short name T612
Test name
Test status
Simulation time 32440954471 ps
CPU time 22.91 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:35:41 PM PDT 24
Peak memory 210472 kb
Host smart-ee70d712-b885-4ee2-addc-ccd0aa8d82dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956459961 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3956459961
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1095114398
Short name T383
Test name
Test status
Simulation time 533634679 ps
CPU time 1.78 seconds
Started Mar 14 12:35:33 PM PDT 24
Finished Mar 14 12:35:35 PM PDT 24
Peak memory 201896 kb
Host smart-4755b7e6-790d-4190-b924-866b49be14fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095114398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1095114398
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3709373267
Short name T164
Test name
Test status
Simulation time 522540485342 ps
CPU time 226.16 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:39:17 PM PDT 24
Peak memory 202196 kb
Host smart-01ba94fa-1c26-42d7-aff9-291038d37418
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709373267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3709373267
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2119946304
Short name T165
Test name
Test status
Simulation time 331532174339 ps
CPU time 201.95 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:38:53 PM PDT 24
Peak memory 202292 kb
Host smart-ed68103c-0365-4486-a376-a0472d6e8caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119946304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2119946304
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1713585360
Short name T617
Test name
Test status
Simulation time 168097046033 ps
CPU time 75.72 seconds
Started Mar 14 12:35:28 PM PDT 24
Finished Mar 14 12:36:46 PM PDT 24
Peak memory 202172 kb
Host smart-10827bac-51e3-408e-8289-27c4da16bd31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713585360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1713585360
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1489490605
Short name T335
Test name
Test status
Simulation time 321995386641 ps
CPU time 681.48 seconds
Started Mar 14 12:35:20 PM PDT 24
Finished Mar 14 12:46:42 PM PDT 24
Peak memory 202200 kb
Host smart-ea1880b6-8192-4fd4-a86a-33361a810acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489490605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1489490605
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2442220414
Short name T360
Test name
Test status
Simulation time 322513355415 ps
CPU time 681.65 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:46:54 PM PDT 24
Peak memory 202116 kb
Host smart-15a1bfaf-25a0-4d36-a11e-6b2b5fd7e475
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442220414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2442220414
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.341605443
Short name T542
Test name
Test status
Simulation time 602360667481 ps
CPU time 537.55 seconds
Started Mar 14 12:35:31 PM PDT 24
Finished Mar 14 12:44:31 PM PDT 24
Peak memory 202112 kb
Host smart-0b9a1a9e-061b-46fd-a426-950c458a678a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341605443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.341605443
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1019980701
Short name T463
Test name
Test status
Simulation time 194047250909 ps
CPU time 486.49 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:43:37 PM PDT 24
Peak memory 202228 kb
Host smart-c0af3f74-93c4-41b0-a8bc-0a9fcb3c42f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019980701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1019980701
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3532913652
Short name T530
Test name
Test status
Simulation time 21643481858 ps
CPU time 50.58 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:36:22 PM PDT 24
Peak memory 201904 kb
Host smart-515f4b1d-c329-4c49-8d95-ef6345d57f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532913652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3532913652
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4129896575
Short name T370
Test name
Test status
Simulation time 2663166802 ps
CPU time 6.72 seconds
Started Mar 14 12:35:31 PM PDT 24
Finished Mar 14 12:35:39 PM PDT 24
Peak memory 201916 kb
Host smart-9aa0d88f-ccce-4f83-9f72-5e6f0044e12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129896575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4129896575
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1643799557
Short name T440
Test name
Test status
Simulation time 5892361978 ps
CPU time 3.97 seconds
Started Mar 14 12:35:18 PM PDT 24
Finished Mar 14 12:35:22 PM PDT 24
Peak memory 201912 kb
Host smart-a9d4675e-7378-4a7f-bba4-38acdf599a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643799557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1643799557
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3973521155
Short name T532
Test name
Test status
Simulation time 163585611883 ps
CPU time 807.37 seconds
Started Mar 14 12:35:28 PM PDT 24
Finished Mar 14 12:48:55 PM PDT 24
Peak memory 202372 kb
Host smart-165dd937-3037-4acb-9598-338b78dcf436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973521155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3973521155
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2899840708
Short name T795
Test name
Test status
Simulation time 53842152500 ps
CPU time 60.01 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:36:31 PM PDT 24
Peak memory 210460 kb
Host smart-d94484ba-2461-471c-aed2-2ffb9d586f4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899840708 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2899840708
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.958382232
Short name T611
Test name
Test status
Simulation time 401768387 ps
CPU time 1.09 seconds
Started Mar 14 12:35:43 PM PDT 24
Finished Mar 14 12:35:45 PM PDT 24
Peak memory 201860 kb
Host smart-81ad6ed1-242d-4b3e-a6a4-bf05f67a677b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958382232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.958382232
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3194819788
Short name T676
Test name
Test status
Simulation time 329212327547 ps
CPU time 187.27 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:38:37 PM PDT 24
Peak memory 202136 kb
Host smart-5a0a284e-32b0-4611-9eb8-1e761d795bab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194819788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3194819788
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2995966090
Short name T282
Test name
Test status
Simulation time 190345018201 ps
CPU time 235.35 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:39:27 PM PDT 24
Peak memory 202056 kb
Host smart-08ec06f4-6745-4de9-b657-6f9d8f7febf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995966090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2995966090
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.119968904
Short name T200
Test name
Test status
Simulation time 330031262676 ps
CPU time 60.45 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:36:32 PM PDT 24
Peak memory 202048 kb
Host smart-73eb654e-b385-4d05-8df7-4d3afc23668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119968904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.119968904
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.298420173
Short name T157
Test name
Test status
Simulation time 176132855979 ps
CPU time 99.46 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:37:11 PM PDT 24
Peak memory 202144 kb
Host smart-81b418d6-d671-42e6-96eb-3ed28dd7ecf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=298420173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.298420173
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3046071635
Short name T543
Test name
Test status
Simulation time 162149381718 ps
CPU time 396.02 seconds
Started Mar 14 12:35:31 PM PDT 24
Finished Mar 14 12:42:08 PM PDT 24
Peak memory 202216 kb
Host smart-238cd80e-f037-49bd-99f2-e0687a12544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046071635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3046071635
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1844905066
Short name T498
Test name
Test status
Simulation time 327365510858 ps
CPU time 157.45 seconds
Started Mar 14 12:35:30 PM PDT 24
Finished Mar 14 12:38:10 PM PDT 24
Peak memory 202188 kb
Host smart-0d3dea55-9396-4f13-afcf-40a4b5ff0bed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844905066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1844905066
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2002115411
Short name T631
Test name
Test status
Simulation time 406558890393 ps
CPU time 253.67 seconds
Started Mar 14 12:35:29 PM PDT 24
Finished Mar 14 12:39:44 PM PDT 24
Peak memory 202164 kb
Host smart-64571fe8-14b2-4cd9-87f6-631ba3177b26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002115411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2002115411
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2992545879
Short name T534
Test name
Test status
Simulation time 92588169852 ps
CPU time 364.46 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 202456 kb
Host smart-b450397d-ca95-456b-a661-27a586aebae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992545879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2992545879
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1295176688
Short name T702
Test name
Test status
Simulation time 45279120141 ps
CPU time 25.71 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:36:07 PM PDT 24
Peak memory 201944 kb
Host smart-3442e169-efb3-4f9e-adf2-838a4aee4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295176688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1295176688
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2634195826
Short name T514
Test name
Test status
Simulation time 4168848981 ps
CPU time 3.09 seconds
Started Mar 14 12:35:28 PM PDT 24
Finished Mar 14 12:35:31 PM PDT 24
Peak memory 201880 kb
Host smart-036d77e0-ca0d-4cc7-b634-060a4e2cb1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634195826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2634195826
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3090354079
Short name T724
Test name
Test status
Simulation time 5910399329 ps
CPU time 8.52 seconds
Started Mar 14 12:35:31 PM PDT 24
Finished Mar 14 12:35:41 PM PDT 24
Peak memory 201936 kb
Host smart-825d717e-6fcb-4574-9349-8b50622b0245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090354079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3090354079
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3596870621
Short name T362
Test name
Test status
Simulation time 50104308800 ps
CPU time 14.83 seconds
Started Mar 14 12:35:42 PM PDT 24
Finished Mar 14 12:35:57 PM PDT 24
Peak memory 201904 kb
Host smart-20ab5a86-59f3-436b-8448-6b06164e7481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596870621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3596870621
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4277198079
Short name T40
Test name
Test status
Simulation time 165140286319 ps
CPU time 109.4 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:37:31 PM PDT 24
Peak memory 210856 kb
Host smart-69925de8-7822-4c29-92cb-12815874de35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277198079 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4277198079
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.23135359
Short name T418
Test name
Test status
Simulation time 296669431 ps
CPU time 1.25 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:16 PM PDT 24
Peak memory 201852 kb
Host smart-d8a1eaaa-3094-45c7-9bd0-c6d7ee5a0a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23135359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.23135359
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1158957049
Short name T303
Test name
Test status
Simulation time 165595476686 ps
CPU time 105.48 seconds
Started Mar 14 12:34:24 PM PDT 24
Finished Mar 14 12:36:09 PM PDT 24
Peak memory 202180 kb
Host smart-9ee8b143-7425-4a84-8c79-1cf560605628
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158957049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1158957049
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1381900248
Short name T345
Test name
Test status
Simulation time 330351112733 ps
CPU time 839.28 seconds
Started Mar 14 12:34:12 PM PDT 24
Finished Mar 14 12:48:12 PM PDT 24
Peak memory 202204 kb
Host smart-ff1f23bd-9287-466d-812c-f9ea32535a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381900248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1381900248
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2092088023
Short name T745
Test name
Test status
Simulation time 163049985163 ps
CPU time 197.99 seconds
Started Mar 14 12:34:20 PM PDT 24
Finished Mar 14 12:37:38 PM PDT 24
Peak memory 202188 kb
Host smart-9b57047a-4bad-488c-8d51-d4a5ee3a72f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092088023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2092088023
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.734062444
Short name T458
Test name
Test status
Simulation time 329506129528 ps
CPU time 725.67 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:46:05 PM PDT 24
Peak memory 202052 kb
Host smart-916f308a-a1cd-4d19-a051-861c4b27ab71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=734062444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.734062444
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2200146279
Short name T387
Test name
Test status
Simulation time 165014463652 ps
CPU time 378.67 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:40:22 PM PDT 24
Peak memory 202080 kb
Host smart-d1cba262-014c-483c-a68d-c2a6d377a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200146279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2200146279
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3797525458
Short name T755
Test name
Test status
Simulation time 327847627174 ps
CPU time 798.73 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:47:23 PM PDT 24
Peak memory 202068 kb
Host smart-3dfa0a84-9ca9-4872-8392-a953c5a3c746
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797525458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3797525458
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.703753262
Short name T162
Test name
Test status
Simulation time 354094589857 ps
CPU time 207.02 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:37:36 PM PDT 24
Peak memory 202200 kb
Host smart-ede0bd86-1ecd-4a7f-b85d-f8ec19e27c2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703753262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_w
akeup.703753262
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1549251439
Short name T386
Test name
Test status
Simulation time 599559991253 ps
CPU time 239.71 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:38:00 PM PDT 24
Peak memory 202148 kb
Host smart-081bc0d3-35b0-43a6-8c43-6bcaf0e9d3db
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549251439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1549251439
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3704414527
Short name T215
Test name
Test status
Simulation time 116085292745 ps
CPU time 463.46 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:41:43 PM PDT 24
Peak memory 202444 kb
Host smart-0c772225-ecda-4ef7-a06f-a710525cd262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704414527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3704414527
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.336984777
Short name T646
Test name
Test status
Simulation time 30574226437 ps
CPU time 70.02 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:35:09 PM PDT 24
Peak memory 201936 kb
Host smart-09cb5002-4c30-4c58-b30d-0f9fc3b1227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336984777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.336984777
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4209200997
Short name T384
Test name
Test status
Simulation time 3239575013 ps
CPU time 8.22 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:22 PM PDT 24
Peak memory 202028 kb
Host smart-3584a191-0155-42a2-b352-8922eed81924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209200997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4209200997
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1118166870
Short name T72
Test name
Test status
Simulation time 8025702744 ps
CPU time 5.72 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:34:28 PM PDT 24
Peak memory 218480 kb
Host smart-a42c911d-78d6-4f95-a1a6-a6e0f5fcb23d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118166870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1118166870
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3650021633
Short name T771
Test name
Test status
Simulation time 5893933154 ps
CPU time 15.71 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:34:16 PM PDT 24
Peak memory 201984 kb
Host smart-9180b5e3-097b-4675-b72e-918af6ba1f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650021633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3650021633
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3495355753
Short name T14
Test name
Test status
Simulation time 457283086 ps
CPU time 0.8 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:35:41 PM PDT 24
Peak memory 201720 kb
Host smart-e3547a71-e96b-4b44-919e-37bbecef2a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495355753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3495355753
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3331168381
Short name T791
Test name
Test status
Simulation time 187297689199 ps
CPU time 37.71 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:36:18 PM PDT 24
Peak memory 202008 kb
Host smart-514eb5ae-a8be-44e1-8aa9-17c4a84fe645
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331168381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3331168381
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.96020411
Short name T522
Test name
Test status
Simulation time 162474172856 ps
CPU time 410.22 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 202064 kb
Host smart-8f3f3d32-fc8b-4f88-8b8e-8ec99a160367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96020411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.96020411
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1519893941
Short name T462
Test name
Test status
Simulation time 164904449278 ps
CPU time 102.53 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:37:23 PM PDT 24
Peak memory 202016 kb
Host smart-ffc82bf3-d9d1-4816-bff8-9a8732b0e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519893941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1519893941
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3526664517
Short name T641
Test name
Test status
Simulation time 169175138154 ps
CPU time 213.98 seconds
Started Mar 14 12:35:43 PM PDT 24
Finished Mar 14 12:39:18 PM PDT 24
Peak memory 202112 kb
Host smart-7741cf49-63d7-4d71-922c-6b47ba308d90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526664517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3526664517
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1840954307
Short name T516
Test name
Test status
Simulation time 163023993895 ps
CPU time 392.56 seconds
Started Mar 14 12:35:42 PM PDT 24
Finished Mar 14 12:42:15 PM PDT 24
Peak memory 202212 kb
Host smart-a8fca015-6623-45c0-bf12-d2d82e5e10d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840954307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1840954307
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1702894078
Short name T415
Test name
Test status
Simulation time 324438194193 ps
CPU time 583.97 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:45:25 PM PDT 24
Peak memory 202144 kb
Host smart-7742cdb1-db58-4338-b8d2-6a03dd9e7047
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702894078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1702894078
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1957001639
Short name T625
Test name
Test status
Simulation time 560543781395 ps
CPU time 1450.02 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:59:51 PM PDT 24
Peak memory 202188 kb
Host smart-17b6177e-11eb-4dc4-b42b-7d742f274359
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957001639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1957001639
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.472072083
Short name T713
Test name
Test status
Simulation time 591760219070 ps
CPU time 1275.89 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:56:57 PM PDT 24
Peak memory 202020 kb
Host smart-6ea049d2-9855-4a1e-be59-62b4b714889f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472072083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.472072083
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2067693000
Short name T564
Test name
Test status
Simulation time 117642964076 ps
CPU time 394.49 seconds
Started Mar 14 12:35:42 PM PDT 24
Finished Mar 14 12:42:17 PM PDT 24
Peak memory 202448 kb
Host smart-066cbf20-4507-4858-bff3-bb028955f388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067693000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2067693000
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2198042133
Short name T576
Test name
Test status
Simulation time 23182656198 ps
CPU time 4.6 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:35:45 PM PDT 24
Peak memory 201872 kb
Host smart-fcd01195-2a84-4d9b-b754-f71737893fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198042133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2198042133
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1791297345
Short name T737
Test name
Test status
Simulation time 3621649688 ps
CPU time 4.35 seconds
Started Mar 14 12:35:43 PM PDT 24
Finished Mar 14 12:35:48 PM PDT 24
Peak memory 201932 kb
Host smart-55003232-df1a-4e09-b6c6-a09aa8bc9c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791297345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1791297345
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3832398421
Short name T673
Test name
Test status
Simulation time 5853787512 ps
CPU time 4.39 seconds
Started Mar 14 12:35:44 PM PDT 24
Finished Mar 14 12:35:50 PM PDT 24
Peak memory 201948 kb
Host smart-60fdd795-c01f-4622-8d8c-3868b343cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832398421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3832398421
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1900718537
Short name T580
Test name
Test status
Simulation time 469411575 ps
CPU time 0.77 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:35:51 PM PDT 24
Peak memory 201896 kb
Host smart-6dd47daa-dedb-4f9e-a310-6cc92a546ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900718537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1900718537
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.366418865
Short name T666
Test name
Test status
Simulation time 162854695788 ps
CPU time 101.91 seconds
Started Mar 14 12:35:52 PM PDT 24
Finished Mar 14 12:37:34 PM PDT 24
Peak memory 202192 kb
Host smart-5ff30716-5aff-482f-9601-b5ff41fbe142
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366418865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.366418865
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3144420107
Short name T115
Test name
Test status
Simulation time 379468760836 ps
CPU time 868.78 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:50:18 PM PDT 24
Peak memory 201924 kb
Host smart-1d859ae2-9f68-4355-9286-910f765ff7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144420107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3144420107
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.454040895
Short name T184
Test name
Test status
Simulation time 164809641007 ps
CPU time 150.95 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:38:12 PM PDT 24
Peak memory 202124 kb
Host smart-f7100b1b-f50b-47da-a633-e5367d942cc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=454040895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.454040895
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2452982835
Short name T643
Test name
Test status
Simulation time 162076050054 ps
CPU time 23.51 seconds
Started Mar 14 12:35:41 PM PDT 24
Finished Mar 14 12:36:04 PM PDT 24
Peak memory 202104 kb
Host smart-f8684a50-c5d5-454d-8b8b-54ad874e79c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452982835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2452982835
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3593123204
Short name T587
Test name
Test status
Simulation time 322282644752 ps
CPU time 113.53 seconds
Started Mar 14 12:35:43 PM PDT 24
Finished Mar 14 12:37:37 PM PDT 24
Peak memory 202168 kb
Host smart-3aff4122-a964-4a21-bdad-de3e82cefdf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593123204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3593123204
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.873651396
Short name T558
Test name
Test status
Simulation time 222168609457 ps
CPU time 256.99 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:40:06 PM PDT 24
Peak memory 202028 kb
Host smart-fbb54bf2-ddd2-46dd-81ce-0693e55680b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873651396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.873651396
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3682805293
Short name T552
Test name
Test status
Simulation time 213484651700 ps
CPU time 91.46 seconds
Started Mar 14 12:35:48 PM PDT 24
Finished Mar 14 12:37:20 PM PDT 24
Peak memory 202032 kb
Host smart-2c6a2981-8612-4ce6-9e84-ff56466fc800
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682805293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3682805293
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1357803770
Short name T210
Test name
Test status
Simulation time 124846677638 ps
CPU time 617.85 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:46:07 PM PDT 24
Peak memory 202400 kb
Host smart-668c605b-e92f-49c3-9e55-87917ded42ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357803770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1357803770
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1073858197
Short name T683
Test name
Test status
Simulation time 45005596032 ps
CPU time 16.03 seconds
Started Mar 14 12:35:48 PM PDT 24
Finished Mar 14 12:36:05 PM PDT 24
Peak memory 201956 kb
Host smart-9682a611-606d-4bdd-a9f0-b7b09e953999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073858197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1073858197
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2789130082
Short name T778
Test name
Test status
Simulation time 3838626497 ps
CPU time 5.14 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:35:55 PM PDT 24
Peak memory 201864 kb
Host smart-e2fcd09b-b0ec-431d-ba71-03cccddf0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789130082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2789130082
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1429660368
Short name T665
Test name
Test status
Simulation time 5645640584 ps
CPU time 3.76 seconds
Started Mar 14 12:35:40 PM PDT 24
Finished Mar 14 12:35:44 PM PDT 24
Peak memory 201916 kb
Host smart-1e364ee1-5564-4b17-872b-b28041c839b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429660368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1429660368
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.983301240
Short name T22
Test name
Test status
Simulation time 68880915277 ps
CPU time 164.75 seconds
Started Mar 14 12:35:48 PM PDT 24
Finished Mar 14 12:38:33 PM PDT 24
Peak memory 210708 kb
Host smart-a3c8b353-2102-4fad-802a-de42c3ddd6b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983301240 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.983301240
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3599239450
Short name T372
Test name
Test status
Simulation time 320525869 ps
CPU time 1.31 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:36:02 PM PDT 24
Peak memory 201872 kb
Host smart-00ed6f40-bc9f-4d26-bc05-a650eec53c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599239450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3599239450
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4041874390
Short name T243
Test name
Test status
Simulation time 168147929895 ps
CPU time 61.84 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:37:03 PM PDT 24
Peak memory 202100 kb
Host smart-743daff6-539e-4893-bf66-74d8328b45df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041874390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4041874390
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3831737895
Short name T310
Test name
Test status
Simulation time 494518529159 ps
CPU time 596.68 seconds
Started Mar 14 12:35:52 PM PDT 24
Finished Mar 14 12:45:49 PM PDT 24
Peak memory 202080 kb
Host smart-92b0f80a-4606-4712-9ea9-6fb10cd6adb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831737895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3831737895
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.983719266
Short name T374
Test name
Test status
Simulation time 165279431144 ps
CPU time 118.53 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:37:48 PM PDT 24
Peak memory 202160 kb
Host smart-afed2c49-6ded-49f9-b3e0-bf6c03ce63f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=983719266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.983719266
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2167165086
Short name T294
Test name
Test status
Simulation time 162534200142 ps
CPU time 197.66 seconds
Started Mar 14 12:35:48 PM PDT 24
Finished Mar 14 12:39:06 PM PDT 24
Peak memory 202140 kb
Host smart-63b3ea78-4443-443d-83f1-fe9465716d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167165086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2167165086
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.83898678
Short name T371
Test name
Test status
Simulation time 489154565860 ps
CPU time 111.07 seconds
Started Mar 14 12:35:48 PM PDT 24
Finished Mar 14 12:37:40 PM PDT 24
Peak memory 202144 kb
Host smart-dc84be5f-96c0-4520-9d43-7db1ecfc23de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=83898678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixed
.83898678
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2472785864
Short name T659
Test name
Test status
Simulation time 573994506408 ps
CPU time 1395.02 seconds
Started Mar 14 12:36:00 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 202104 kb
Host smart-4b93f963-c812-4131-ba8b-ecd889cc7c38
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472785864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2472785864
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.951650461
Short name T486
Test name
Test status
Simulation time 401465797746 ps
CPU time 960.17 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:51:58 PM PDT 24
Peak memory 202148 kb
Host smart-44a6a090-4fa5-412a-8bbd-76c90b226799
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951650461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.951650461
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3309123959
Short name T353
Test name
Test status
Simulation time 86328528478 ps
CPU time 432.14 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:43:11 PM PDT 24
Peak memory 202472 kb
Host smart-adb19821-0c37-48f4-a9c0-501d39544116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309123959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3309123959
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.660711162
Short name T797
Test name
Test status
Simulation time 46465616663 ps
CPU time 27.08 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:36:25 PM PDT 24
Peak memory 201964 kb
Host smart-54acfb10-7889-4d35-b6aa-377b4ba0fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660711162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.660711162
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.164544788
Short name T559
Test name
Test status
Simulation time 5202740729 ps
CPU time 6.18 seconds
Started Mar 14 12:35:57 PM PDT 24
Finished Mar 14 12:36:04 PM PDT 24
Peak memory 201920 kb
Host smart-df93a310-6318-46bb-95f6-89b4b086972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164544788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.164544788
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3017469229
Short name T709
Test name
Test status
Simulation time 5799527145 ps
CPU time 14.42 seconds
Started Mar 14 12:35:49 PM PDT 24
Finished Mar 14 12:36:04 PM PDT 24
Peak memory 201920 kb
Host smart-325ba39d-41e5-46de-8405-47865985305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017469229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3017469229
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2196210701
Short name T747
Test name
Test status
Simulation time 424479590836 ps
CPU time 211.21 seconds
Started Mar 14 12:36:00 PM PDT 24
Finished Mar 14 12:39:31 PM PDT 24
Peak memory 213104 kb
Host smart-fcca5103-c882-4c39-897a-0d239aa2cc7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196210701 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2196210701
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2807158429
Short name T80
Test name
Test status
Simulation time 472314110 ps
CPU time 1.77 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:36:03 PM PDT 24
Peak memory 201888 kb
Host smart-f15a51bf-376d-4c88-9d51-86d527cebe2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807158429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2807158429
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3053273861
Short name T570
Test name
Test status
Simulation time 169248552918 ps
CPU time 88.61 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:37:30 PM PDT 24
Peak memory 202108 kb
Host smart-7f796661-edbc-419f-af18-1f7613fcf181
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053273861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3053273861
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.821130773
Short name T671
Test name
Test status
Simulation time 337320015925 ps
CPU time 744.89 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 202096 kb
Host smart-385c3414-5ee4-4cb1-b8ed-11417d3baf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821130773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.821130773
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1073787334
Short name T540
Test name
Test status
Simulation time 493660260828 ps
CPU time 205.14 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 202108 kb
Host smart-8d1a4ff2-4864-41e1-9b75-44104be7b451
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073787334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1073787334
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3720951025
Short name T12
Test name
Test status
Simulation time 164018048659 ps
CPU time 383.77 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:42:25 PM PDT 24
Peak memory 202144 kb
Host smart-a2d13cad-5bd6-4c7f-818e-7faa4e6e4a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720951025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3720951025
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2087752011
Short name T111
Test name
Test status
Simulation time 490293432310 ps
CPU time 295.78 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 202068 kb
Host smart-e520595e-8dfd-4f82-b185-880ad9aa2b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087752011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2087752011
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1746951476
Short name T720
Test name
Test status
Simulation time 575317632227 ps
CPU time 693.23 seconds
Started Mar 14 12:35:57 PM PDT 24
Finished Mar 14 12:47:30 PM PDT 24
Peak memory 202136 kb
Host smart-1372ddc4-1ff5-4b3a-a784-0753a43d727d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746951476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1746951476
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.534161606
Short name T409
Test name
Test status
Simulation time 191197170095 ps
CPU time 470.59 seconds
Started Mar 14 12:35:59 PM PDT 24
Finished Mar 14 12:43:49 PM PDT 24
Peak memory 202056 kb
Host smart-bcebdd3d-64dc-4752-a7ed-6561f839d883
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534161606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.534161606
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2968120996
Short name T220
Test name
Test status
Simulation time 113375584233 ps
CPU time 532.28 seconds
Started Mar 14 12:35:59 PM PDT 24
Finished Mar 14 12:44:52 PM PDT 24
Peak memory 202516 kb
Host smart-fb524942-d8aa-42ee-8d9b-1be64e8d4918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968120996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2968120996
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.719135429
Short name T411
Test name
Test status
Simulation time 43013258228 ps
CPU time 55.57 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:36:54 PM PDT 24
Peak memory 201868 kb
Host smart-10f2b2f2-0bd4-4009-b84b-cecefa21bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719135429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.719135429
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2651466193
Short name T729
Test name
Test status
Simulation time 5297240932 ps
CPU time 13.93 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:36:15 PM PDT 24
Peak memory 201936 kb
Host smart-e8a59459-86ef-4c65-9a8a-7105822862d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651466193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2651466193
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2079894380
Short name T693
Test name
Test status
Simulation time 5999267442 ps
CPU time 14.3 seconds
Started Mar 14 12:36:01 PM PDT 24
Finished Mar 14 12:36:16 PM PDT 24
Peak memory 201928 kb
Host smart-df5923f7-a4bf-4694-95a6-9babf7999253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079894380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2079894380
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3570821652
Short name T34
Test name
Test status
Simulation time 184943233369 ps
CPU time 219.14 seconds
Started Mar 14 12:35:58 PM PDT 24
Finished Mar 14 12:39:37 PM PDT 24
Peak memory 202140 kb
Host smart-577ea12c-81d3-4672-aea5-daa060312b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570821652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3570821652
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.606347799
Short name T337
Test name
Test status
Simulation time 47650559622 ps
CPU time 130.67 seconds
Started Mar 14 12:36:00 PM PDT 24
Finished Mar 14 12:38:11 PM PDT 24
Peak memory 210812 kb
Host smart-4320ade0-0c12-485d-be6a-92b58b08aabe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606347799 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.606347799
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4133120261
Short name T792
Test name
Test status
Simulation time 382717383 ps
CPU time 1.57 seconds
Started Mar 14 12:36:08 PM PDT 24
Finished Mar 14 12:36:10 PM PDT 24
Peak memory 201868 kb
Host smart-9bce3587-1357-4aa0-ae8b-5a64628aa329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133120261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4133120261
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3063442821
Short name T228
Test name
Test status
Simulation time 337423839861 ps
CPU time 204.13 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:39:34 PM PDT 24
Peak memory 202048 kb
Host smart-d8dd524d-8dd2-40d3-8f63-312f5f9b0754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063442821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3063442821
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.473344719
Short name T381
Test name
Test status
Simulation time 164204624070 ps
CPU time 421.48 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:43:11 PM PDT 24
Peak memory 202068 kb
Host smart-158c8c5e-2dd7-456e-96cc-d6df4da9bbc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=473344719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.473344719
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3108390524
Short name T5
Test name
Test status
Simulation time 166253050695 ps
CPU time 199.78 seconds
Started Mar 14 12:36:08 PM PDT 24
Finished Mar 14 12:39:28 PM PDT 24
Peak memory 202032 kb
Host smart-33399945-8038-4046-9a89-f5b4e95134f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108390524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3108390524
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2544376210
Short name T790
Test name
Test status
Simulation time 324370535441 ps
CPU time 150.56 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:38:41 PM PDT 24
Peak memory 202096 kb
Host smart-77c500d9-59e7-4844-a553-8fc1879d2a1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544376210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2544376210
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3412876521
Short name T685
Test name
Test status
Simulation time 177281041565 ps
CPU time 104.5 seconds
Started Mar 14 12:36:07 PM PDT 24
Finished Mar 14 12:37:52 PM PDT 24
Peak memory 202140 kb
Host smart-3253fa4a-8622-4379-a6d8-9038af644789
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412876521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3412876521
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.3842559700
Short name T95
Test name
Test status
Simulation time 401255407928 ps
CPU time 250.71 seconds
Started Mar 14 12:36:06 PM PDT 24
Finished Mar 14 12:40:17 PM PDT 24
Peak memory 202204 kb
Host smart-00313650-b52e-4d9f-a06d-3069ad379c31
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842559700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.3842559700
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3823988212
Short name T524
Test name
Test status
Simulation time 109583169186 ps
CPU time 445.49 seconds
Started Mar 14 12:36:08 PM PDT 24
Finished Mar 14 12:43:34 PM PDT 24
Peak memory 202356 kb
Host smart-01500f72-f433-4011-a8fd-8882a0125b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823988212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3823988212
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.873030013
Short name T703
Test name
Test status
Simulation time 33281447998 ps
CPU time 75.98 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:37:26 PM PDT 24
Peak memory 201928 kb
Host smart-580ae252-0171-46f5-a061-62e49ea11e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873030013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.873030013
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.592825403
Short name T682
Test name
Test status
Simulation time 2754139682 ps
CPU time 7.53 seconds
Started Mar 14 12:36:08 PM PDT 24
Finished Mar 14 12:36:16 PM PDT 24
Peak memory 201956 kb
Host smart-1d7e4beb-0c30-4113-ad33-73a1a0f6eb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592825403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.592825403
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1171991724
Short name T597
Test name
Test status
Simulation time 5724458894 ps
CPU time 4.01 seconds
Started Mar 14 12:36:07 PM PDT 24
Finished Mar 14 12:36:11 PM PDT 24
Peak memory 201768 kb
Host smart-327b99d6-39a1-40a5-ac74-8798d1006472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171991724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1171991724
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.141491722
Short name T491
Test name
Test status
Simulation time 287011578642 ps
CPU time 491.96 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:44:22 PM PDT 24
Peak memory 210684 kb
Host smart-0ab852dd-b830-4ca8-bc45-d98a3f8cd13b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141491722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
141491722
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2394112095
Short name T385
Test name
Test status
Simulation time 352996459 ps
CPU time 1.01 seconds
Started Mar 14 12:36:14 PM PDT 24
Finished Mar 14 12:36:16 PM PDT 24
Peak memory 201912 kb
Host smart-3f289afe-fc9c-4a82-9a89-a7c3d654c39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394112095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2394112095
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2130015114
Short name T706
Test name
Test status
Simulation time 486100770515 ps
CPU time 307.17 seconds
Started Mar 14 12:36:16 PM PDT 24
Finished Mar 14 12:41:23 PM PDT 24
Peak memory 202024 kb
Host smart-b3ac2230-6e94-4601-9955-902d21c2ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130015114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2130015114
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1792040453
Short name T650
Test name
Test status
Simulation time 331192894565 ps
CPU time 297.32 seconds
Started Mar 14 12:36:16 PM PDT 24
Finished Mar 14 12:41:13 PM PDT 24
Peak memory 202028 kb
Host smart-95430ff1-ffc0-4717-95f9-80cd860a490b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792040453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1792040453
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2907274369
Short name T170
Test name
Test status
Simulation time 330445076459 ps
CPU time 143.02 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:38:33 PM PDT 24
Peak memory 202092 kb
Host smart-a53921c2-9257-4467-b7d3-c2c76adcccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907274369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2907274369
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3024286977
Short name T647
Test name
Test status
Simulation time 492522991517 ps
CPU time 629.61 seconds
Started Mar 14 12:36:09 PM PDT 24
Finished Mar 14 12:46:39 PM PDT 24
Peak memory 202136 kb
Host smart-03f4c7b0-e0ce-408a-a056-2b8af8da18bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024286977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3024286977
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.483290078
Short name T196
Test name
Test status
Simulation time 398775116183 ps
CPU time 81.48 seconds
Started Mar 14 12:36:14 PM PDT 24
Finished Mar 14 12:37:36 PM PDT 24
Peak memory 202164 kb
Host smart-d3c5d281-bd5c-4657-bddd-721029758c8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483290078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.483290078
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3775110664
Short name T749
Test name
Test status
Simulation time 400057376573 ps
CPU time 282.8 seconds
Started Mar 14 12:36:16 PM PDT 24
Finished Mar 14 12:40:58 PM PDT 24
Peak memory 202260 kb
Host smart-add8da80-7edc-499f-ba3a-bf7fb58b9af1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775110664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3775110664
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1790480541
Short name T208
Test name
Test status
Simulation time 130698228662 ps
CPU time 358.57 seconds
Started Mar 14 12:36:18 PM PDT 24
Finished Mar 14 12:42:16 PM PDT 24
Peak memory 202412 kb
Host smart-e6d127e9-bb8c-4553-af2d-82dbb1c6b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790480541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1790480541
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.592095053
Short name T688
Test name
Test status
Simulation time 33970908486 ps
CPU time 83.2 seconds
Started Mar 14 12:36:16 PM PDT 24
Finished Mar 14 12:37:39 PM PDT 24
Peak memory 201960 kb
Host smart-a799d5c5-e60c-4304-9ec4-01a71f206922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592095053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.592095053
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.633010172
Short name T545
Test name
Test status
Simulation time 3127324020 ps
CPU time 3.93 seconds
Started Mar 14 12:36:18 PM PDT 24
Finished Mar 14 12:36:22 PM PDT 24
Peak memory 201776 kb
Host smart-446ae0db-8048-4bb3-967f-9c7b3b12bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633010172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.633010172
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.137912196
Short name T528
Test name
Test status
Simulation time 6071479704 ps
CPU time 15.13 seconds
Started Mar 14 12:36:10 PM PDT 24
Finished Mar 14 12:36:25 PM PDT 24
Peak memory 201860 kb
Host smart-f0402fe9-cf87-482b-9041-a2610fbe4028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137912196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.137912196
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2871029684
Short name T116
Test name
Test status
Simulation time 1041649404656 ps
CPU time 758.32 seconds
Started Mar 14 12:36:15 PM PDT 24
Finished Mar 14 12:48:54 PM PDT 24
Peak memory 210692 kb
Host smart-1e2313ca-c173-4b5a-9b7a-8b0d20a07c9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871029684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2871029684
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1670697060
Short name T66
Test name
Test status
Simulation time 197715088193 ps
CPU time 249.17 seconds
Started Mar 14 12:36:14 PM PDT 24
Finished Mar 14 12:40:24 PM PDT 24
Peak memory 218604 kb
Host smart-349efa11-a31d-4268-8991-140c8dd5aa3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670697060 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1670697060
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3186156319
Short name T722
Test name
Test status
Simulation time 432568704 ps
CPU time 1.51 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:36:28 PM PDT 24
Peak memory 201912 kb
Host smart-4eaca5df-1aad-442b-929c-ef0757c77d18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186156319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3186156319
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2392082070
Short name T329
Test name
Test status
Simulation time 169497117078 ps
CPU time 24.55 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:36:50 PM PDT 24
Peak memory 202056 kb
Host smart-33c54e2e-2e21-434f-b218-bb40f937eb18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392082070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2392082070
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3657521333
Short name T233
Test name
Test status
Simulation time 159045120088 ps
CPU time 191.97 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:39:37 PM PDT 24
Peak memory 202092 kb
Host smart-4b02341d-1bca-41fb-ba7a-7fa93a07d10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657521333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3657521333
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.44003073
Short name T594
Test name
Test status
Simulation time 329482266886 ps
CPU time 851.18 seconds
Started Mar 14 12:36:15 PM PDT 24
Finished Mar 14 12:50:27 PM PDT 24
Peak memory 202064 kb
Host smart-138e2209-0525-48a0-a0d4-bfdb62b3773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44003073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.44003073
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2155692537
Short name T553
Test name
Test status
Simulation time 329085052476 ps
CPU time 342.12 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:42:07 PM PDT 24
Peak memory 202172 kb
Host smart-99487e86-4ead-476e-a4e1-1f532fa25e4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155692537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2155692537
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3442627040
Short name T555
Test name
Test status
Simulation time 165380154172 ps
CPU time 355.99 seconds
Started Mar 14 12:36:14 PM PDT 24
Finished Mar 14 12:42:11 PM PDT 24
Peak memory 202132 kb
Host smart-6c6a22b4-1f2d-4646-a400-b12336136167
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442627040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3442627040
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.4045759951
Short name T789
Test name
Test status
Simulation time 566920049737 ps
CPU time 1239.65 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:57:06 PM PDT 24
Peak memory 202196 kb
Host smart-0a4e1216-b9c6-4d7e-973b-15dbd83bebf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045759951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.4045759951
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2147998437
Short name T479
Test name
Test status
Simulation time 604809934542 ps
CPU time 719.67 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:48:26 PM PDT 24
Peak memory 202064 kb
Host smart-045d30bb-f217-430c-9760-62d8d9ce51fe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147998437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2147998437
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2796781754
Short name T207
Test name
Test status
Simulation time 141669776029 ps
CPU time 491.01 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:44:37 PM PDT 24
Peak memory 202396 kb
Host smart-297c9253-3503-414d-9ef6-2ac452428882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796781754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2796781754
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1047641300
Short name T354
Test name
Test status
Simulation time 35067503712 ps
CPU time 5.69 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:36:32 PM PDT 24
Peak memory 201932 kb
Host smart-6ef182cd-7aaf-4533-80cf-119f7a0e1cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047641300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1047641300
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1936619901
Short name T442
Test name
Test status
Simulation time 5069778998 ps
CPU time 6.69 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:36:33 PM PDT 24
Peak memory 201880 kb
Host smart-e104fda3-c1c5-45b8-ac64-7907e6afd82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936619901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1936619901
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2602571281
Short name T455
Test name
Test status
Simulation time 5914571038 ps
CPU time 7.27 seconds
Started Mar 14 12:36:15 PM PDT 24
Finished Mar 14 12:36:22 PM PDT 24
Peak memory 201832 kb
Host smart-c6ae87ac-63fa-4af5-888a-2cc0c5c4df09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602571281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2602571281
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3364968035
Short name T435
Test name
Test status
Simulation time 208442025370 ps
CPU time 483.45 seconds
Started Mar 14 12:36:28 PM PDT 24
Finished Mar 14 12:44:32 PM PDT 24
Peak memory 202128 kb
Host smart-0a62cea0-7220-4a2a-a416-69883761b12c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364968035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3364968035
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3696435893
Short name T519
Test name
Test status
Simulation time 506460751 ps
CPU time 0.96 seconds
Started Mar 14 12:36:35 PM PDT 24
Finished Mar 14 12:36:36 PM PDT 24
Peak memory 201820 kb
Host smart-dccfab1d-241d-4d14-a4af-78b5499daee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696435893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3696435893
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.549425315
Short name T155
Test name
Test status
Simulation time 336284897718 ps
CPU time 208.55 seconds
Started Mar 14 12:36:35 PM PDT 24
Finished Mar 14 12:40:04 PM PDT 24
Peak memory 202188 kb
Host smart-0e94bc52-3cd2-48e9-943d-d7eb7d8b2ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549425315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.549425315
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3230551667
Short name T399
Test name
Test status
Simulation time 336654027789 ps
CPU time 739.32 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:48:45 PM PDT 24
Peak memory 202084 kb
Host smart-1c5dbbb1-84dd-4dae-9e93-259eaa1e8b15
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230551667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3230551667
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3579406780
Short name T403
Test name
Test status
Simulation time 164623246414 ps
CPU time 103.86 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:38:09 PM PDT 24
Peak memory 202156 kb
Host smart-fb0f3c96-154f-49c6-a736-32b356958ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579406780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3579406780
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.395404723
Short name T609
Test name
Test status
Simulation time 329898590903 ps
CPU time 798.72 seconds
Started Mar 14 12:36:26 PM PDT 24
Finished Mar 14 12:49:44 PM PDT 24
Peak memory 202104 kb
Host smart-327b17bf-c53c-468d-8349-3c8fa2d7818c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=395404723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.395404723
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4149967559
Short name T456
Test name
Test status
Simulation time 400533220215 ps
CPU time 238.91 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:40:33 PM PDT 24
Peak memory 202168 kb
Host smart-1485e75e-3651-43db-baae-2a6ba2289050
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149967559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4149967559
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1511548669
Short name T529
Test name
Test status
Simulation time 102592146653 ps
CPU time 553.23 seconds
Started Mar 14 12:36:32 PM PDT 24
Finished Mar 14 12:45:46 PM PDT 24
Peak memory 202416 kb
Host smart-3e502785-4f23-4fd3-8209-c08786267d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511548669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1511548669
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.841781199
Short name T460
Test name
Test status
Simulation time 30734558452 ps
CPU time 11.41 seconds
Started Mar 14 12:36:33 PM PDT 24
Finished Mar 14 12:36:45 PM PDT 24
Peak memory 201900 kb
Host smart-04f39938-462c-4334-a0fe-edcab6f2a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841781199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.841781199
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3248400668
Short name T428
Test name
Test status
Simulation time 3303304260 ps
CPU time 8.1 seconds
Started Mar 14 12:36:36 PM PDT 24
Finished Mar 14 12:36:45 PM PDT 24
Peak memory 201948 kb
Host smart-508e5bc6-df2c-4ba5-a87f-8e9a0451735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248400668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3248400668
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3660270464
Short name T687
Test name
Test status
Simulation time 6092809502 ps
CPU time 2.34 seconds
Started Mar 14 12:36:25 PM PDT 24
Finished Mar 14 12:36:27 PM PDT 24
Peak memory 201928 kb
Host smart-eb242832-408a-4dfe-84cf-bc88010951e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660270464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3660270464
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2075698097
Short name T53
Test name
Test status
Simulation time 329628429641 ps
CPU time 427.72 seconds
Started Mar 14 12:36:36 PM PDT 24
Finished Mar 14 12:43:43 PM PDT 24
Peak memory 212844 kb
Host smart-5572d1d4-c9f4-499d-ac7b-4cb6fae2cd09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075698097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2075698097
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2503918828
Short name T653
Test name
Test status
Simulation time 405478965 ps
CPU time 0.87 seconds
Started Mar 14 12:36:52 PM PDT 24
Finished Mar 14 12:36:53 PM PDT 24
Peak memory 201876 kb
Host smart-fe9b60ca-22bf-45e8-9696-9b6202260442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503918828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2503918828
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1515857047
Short name T317
Test name
Test status
Simulation time 366938874984 ps
CPU time 419.64 seconds
Started Mar 14 12:36:44 PM PDT 24
Finished Mar 14 12:43:43 PM PDT 24
Peak memory 202132 kb
Host smart-53de29df-125b-41a7-9aa3-c1b6838e4a5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515857047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1515857047
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1215347588
Short name T615
Test name
Test status
Simulation time 523433940193 ps
CPU time 1209.86 seconds
Started Mar 14 12:36:45 PM PDT 24
Finished Mar 14 12:56:55 PM PDT 24
Peak memory 202128 kb
Host smart-c5e172cd-1b41-4a61-9bbe-7232dc879435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215347588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1215347588
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1083429211
Short name T776
Test name
Test status
Simulation time 159159913453 ps
CPU time 54.91 seconds
Started Mar 14 12:36:37 PM PDT 24
Finished Mar 14 12:37:32 PM PDT 24
Peak memory 202112 kb
Host smart-13468c2a-9c31-4d20-a556-f060701bc0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083429211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1083429211
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2724408453
Short name T366
Test name
Test status
Simulation time 335332029000 ps
CPU time 371.28 seconds
Started Mar 14 12:36:33 PM PDT 24
Finished Mar 14 12:42:45 PM PDT 24
Peak memory 202084 kb
Host smart-6386e8fa-533b-4c4d-b7ba-c5cf2b8ece9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724408453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2724408453
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4204975335
Short name T227
Test name
Test status
Simulation time 166369995581 ps
CPU time 100.19 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:38:14 PM PDT 24
Peak memory 202188 kb
Host smart-586c0154-2d3a-4271-a3e9-33fe2df0ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204975335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4204975335
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3021666661
Short name T601
Test name
Test status
Simulation time 501560143759 ps
CPU time 1080.09 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:54:35 PM PDT 24
Peak memory 201976 kb
Host smart-e1c1fd7b-b74c-42b2-b44f-a3d6ac48d58b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021666661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3021666661
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1913031670
Short name T250
Test name
Test status
Simulation time 385000471212 ps
CPU time 103.55 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:38:18 PM PDT 24
Peak memory 202056 kb
Host smart-08e9b955-f67d-40ae-93b4-79b51bb06adb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913031670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1913031670
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1933989177
Short name T596
Test name
Test status
Simulation time 607345165701 ps
CPU time 388.76 seconds
Started Mar 14 12:36:34 PM PDT 24
Finished Mar 14 12:43:02 PM PDT 24
Peak memory 202108 kb
Host smart-3cc8d7d6-8e02-48cd-95dc-4a0d299fee28
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933989177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1933989177
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3817895140
Short name T209
Test name
Test status
Simulation time 143717093297 ps
CPU time 556.65 seconds
Started Mar 14 12:36:44 PM PDT 24
Finished Mar 14 12:46:01 PM PDT 24
Peak memory 202452 kb
Host smart-fa17d624-271a-4892-ae8a-b476ace953f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817895140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3817895140
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1514670639
Short name T626
Test name
Test status
Simulation time 43728644085 ps
CPU time 96.35 seconds
Started Mar 14 12:36:48 PM PDT 24
Finished Mar 14 12:38:24 PM PDT 24
Peak memory 201956 kb
Host smart-cd652a71-8fc3-4d92-98f6-4038373b6108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514670639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1514670639
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.665005522
Short name T546
Test name
Test status
Simulation time 3596860000 ps
CPU time 8.89 seconds
Started Mar 14 12:36:45 PM PDT 24
Finished Mar 14 12:36:54 PM PDT 24
Peak memory 201788 kb
Host smart-b13de88f-06e6-43a0-b53b-9d47f7b2099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665005522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.665005522
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1897340311
Short name T438
Test name
Test status
Simulation time 6034534562 ps
CPU time 13.84 seconds
Started Mar 14 12:36:36 PM PDT 24
Finished Mar 14 12:36:50 PM PDT 24
Peak memory 201948 kb
Host smart-56db43ac-3489-4f1b-a305-d51b9b3873fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897340311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1897340311
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1400537489
Short name T746
Test name
Test status
Simulation time 28197011416 ps
CPU time 63.65 seconds
Started Mar 14 12:36:46 PM PDT 24
Finished Mar 14 12:37:49 PM PDT 24
Peak memory 210780 kb
Host smart-bc70c32a-3439-48de-bd58-7db4c5f82263
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400537489 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1400537489
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2001126777
Short name T380
Test name
Test status
Simulation time 358557574 ps
CPU time 0.67 seconds
Started Mar 14 12:36:55 PM PDT 24
Finished Mar 14 12:36:56 PM PDT 24
Peak memory 201896 kb
Host smart-57c26232-513f-420b-b0f7-89a2a6ff15e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001126777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2001126777
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.823868059
Short name T266
Test name
Test status
Simulation time 504361334178 ps
CPU time 1207.86 seconds
Started Mar 14 12:36:45 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 202100 kb
Host smart-b848f614-78cc-4263-aed3-49b22ea49c7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823868059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.823868059
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4150737330
Short name T320
Test name
Test status
Simulation time 175941555396 ps
CPU time 99.74 seconds
Started Mar 14 12:36:49 PM PDT 24
Finished Mar 14 12:38:29 PM PDT 24
Peak memory 202008 kb
Host smart-26df068d-6e1b-408e-87d8-6b54eec423d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150737330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4150737330
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3474331670
Short name T149
Test name
Test status
Simulation time 487244946382 ps
CPU time 1134.52 seconds
Started Mar 14 12:36:48 PM PDT 24
Finished Mar 14 12:55:43 PM PDT 24
Peak memory 202052 kb
Host smart-f03419b4-061c-4214-81cb-d1f49816f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474331670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3474331670
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2209291907
Short name T373
Test name
Test status
Simulation time 499146061221 ps
CPU time 1198.51 seconds
Started Mar 14 12:36:46 PM PDT 24
Finished Mar 14 12:56:45 PM PDT 24
Peak memory 202000 kb
Host smart-b4059363-c43a-46f7-9e77-f2a2c41881a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209291907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2209291907
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.54834274
Short name T447
Test name
Test status
Simulation time 161236657593 ps
CPU time 112.45 seconds
Started Mar 14 12:36:47 PM PDT 24
Finished Mar 14 12:38:40 PM PDT 24
Peak memory 202048 kb
Host smart-f7093ffd-8242-4827-a7dc-bf317ea3b35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54834274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.54834274
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.609387144
Short name T787
Test name
Test status
Simulation time 489866565438 ps
CPU time 1211.24 seconds
Started Mar 14 12:36:47 PM PDT 24
Finished Mar 14 12:56:59 PM PDT 24
Peak memory 202188 kb
Host smart-73c1851a-a914-4596-9cd5-78567f4a22da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=609387144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.609387144
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3070632824
Short name T265
Test name
Test status
Simulation time 362040566414 ps
CPU time 794.02 seconds
Started Mar 14 12:36:46 PM PDT 24
Finished Mar 14 12:50:00 PM PDT 24
Peak memory 202160 kb
Host smart-edbd2fdc-4e62-4de4-b62e-7230ca014686
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070632824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3070632824
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.49645414
Short name T579
Test name
Test status
Simulation time 196915601572 ps
CPU time 221.73 seconds
Started Mar 14 12:36:47 PM PDT 24
Finished Mar 14 12:40:29 PM PDT 24
Peak memory 202068 kb
Host smart-40e5c191-326c-48f1-a36b-95df2eaae7aa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49645414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
dc_ctrl_filters_wakeup_fixed.49645414
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3354056148
Short name T663
Test name
Test status
Simulation time 110781800580 ps
CPU time 582.28 seconds
Started Mar 14 12:36:49 PM PDT 24
Finished Mar 14 12:46:31 PM PDT 24
Peak memory 202336 kb
Host smart-cf1ff8c0-c2b4-4919-99bc-9506ef4099a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354056148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3354056148
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2022463444
Short name T763
Test name
Test status
Simulation time 21040020501 ps
CPU time 13.52 seconds
Started Mar 14 12:36:47 PM PDT 24
Finished Mar 14 12:37:00 PM PDT 24
Peak memory 201880 kb
Host smart-9caafc03-a4ce-48e5-afcd-91af003818d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022463444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2022463444
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2680568522
Short name T185
Test name
Test status
Simulation time 4522358098 ps
CPU time 3.95 seconds
Started Mar 14 12:36:44 PM PDT 24
Finished Mar 14 12:36:49 PM PDT 24
Peak memory 201960 kb
Host smart-e6c259c9-87fa-43f4-acdf-a730ccf187f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680568522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2680568522
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3525908792
Short name T788
Test name
Test status
Simulation time 5976351141 ps
CPU time 14.27 seconds
Started Mar 14 12:36:53 PM PDT 24
Finished Mar 14 12:37:07 PM PDT 24
Peak memory 201808 kb
Host smart-a5856d33-bec8-41d7-b8d2-df61f5bcfc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525908792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3525908792
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2358929853
Short name T249
Test name
Test status
Simulation time 277422618631 ps
CPU time 283.76 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:41:40 PM PDT 24
Peak memory 202016 kb
Host smart-1894f993-bda2-4003-9505-6a972b6dca67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358929853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2358929853
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3920566010
Short name T42
Test name
Test status
Simulation time 357789826357 ps
CPU time 67.35 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:38:05 PM PDT 24
Peak memory 210424 kb
Host smart-0a8fa3d9-ccf6-413a-8fe1-efd0de01e7c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920566010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3920566010
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1045932956
Short name T182
Test name
Test status
Simulation time 524334995 ps
CPU time 1.21 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:34:01 PM PDT 24
Peak memory 201904 kb
Host smart-87bf88d5-85cf-484c-b3ed-ca4ae54ace0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045932956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1045932956
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2151719178
Short name T173
Test name
Test status
Simulation time 166269820771 ps
CPU time 374.36 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:40:36 PM PDT 24
Peak memory 202056 kb
Host smart-fdd744c9-d60f-4167-adf4-060758f33332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151719178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2151719178
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.519470889
Short name T148
Test name
Test status
Simulation time 325274650939 ps
CPU time 374.71 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:40:40 PM PDT 24
Peak memory 202152 kb
Host smart-f9062d94-0741-40a3-82b9-ae7ce9f3dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519470889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.519470889
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3903258608
Short name T634
Test name
Test status
Simulation time 327815083083 ps
CPU time 820.39 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:47:41 PM PDT 24
Peak memory 202072 kb
Host smart-4459ec4f-c93d-45d9-9328-f2fd0e99c7b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903258608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3903258608
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2477828601
Short name T180
Test name
Test status
Simulation time 327815594688 ps
CPU time 81.02 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:35:21 PM PDT 24
Peak memory 202116 kb
Host smart-8abc9ac8-e5a1-4cd0-9b38-0d6dfbf10430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477828601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2477828601
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1955186479
Short name T432
Test name
Test status
Simulation time 164701044719 ps
CPU time 94.06 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:35:39 PM PDT 24
Peak memory 201988 kb
Host smart-8b7e7a7b-a5ee-436b-ab7e-a4495744c2b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955186479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1955186479
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2339429771
Short name T110
Test name
Test status
Simulation time 406497755328 ps
CPU time 93.68 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:35:55 PM PDT 24
Peak memory 202076 kb
Host smart-5a3ae7ad-8a48-4f55-bc28-0199f8e1146f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339429771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2339429771
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1140917341
Short name T575
Test name
Test status
Simulation time 94694840913 ps
CPU time 389.53 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 202384 kb
Host smart-7e5323ed-972e-4963-99ac-d02552766517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140917341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1140917341
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1698969687
Short name T90
Test name
Test status
Simulation time 30680529892 ps
CPU time 24.85 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:34:47 PM PDT 24
Peak memory 201840 kb
Host smart-369bff46-a7f1-41ac-ad7d-30c904f362a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698969687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1698969687
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.750429079
Short name T750
Test name
Test status
Simulation time 5453533088 ps
CPU time 7.03 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:34:29 PM PDT 24
Peak memory 201704 kb
Host smart-7f693f89-5ba4-48c2-afc6-336e308cc17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750429079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.750429079
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.647630062
Short name T88
Test name
Test status
Simulation time 4521360239 ps
CPU time 10.27 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:34:36 PM PDT 24
Peak memory 217824 kb
Host smart-3b9a8d9c-25ff-4366-83f5-94825a7b0acf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647630062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.647630062
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2715049367
Short name T517
Test name
Test status
Simulation time 5722055274 ps
CPU time 2.3 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:34:02 PM PDT 24
Peak memory 201960 kb
Host smart-dedd1936-bfd0-43bd-b898-3b722e9ff0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715049367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2715049367
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.277766943
Short name T600
Test name
Test status
Simulation time 79847141479 ps
CPU time 176.48 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:36:59 PM PDT 24
Peak memory 210776 kb
Host smart-907ef826-2b8e-48a8-91ca-fd7c5017928c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277766943 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.277766943
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3671094308
Short name T79
Test name
Test status
Simulation time 332014853 ps
CPU time 0.95 seconds
Started Mar 14 12:36:58 PM PDT 24
Finished Mar 14 12:36:59 PM PDT 24
Peak memory 201868 kb
Host smart-786ef497-f693-4688-8994-42a8bbc5940b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671094308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3671094308
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3877913731
Short name T606
Test name
Test status
Simulation time 198950566384 ps
CPU time 221.83 seconds
Started Mar 14 12:37:00 PM PDT 24
Finished Mar 14 12:40:42 PM PDT 24
Peak memory 202148 kb
Host smart-e97fa5d1-8d8b-4a8a-b21b-a33acaed1783
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877913731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3877913731
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.355738301
Short name T29
Test name
Test status
Simulation time 181871736435 ps
CPU time 105.74 seconds
Started Mar 14 12:36:59 PM PDT 24
Finished Mar 14 12:38:45 PM PDT 24
Peak memory 202196 kb
Host smart-926d758c-d3a4-4041-81b5-ee2cd1fdf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355738301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.355738301
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.4266546915
Short name T167
Test name
Test status
Simulation time 499689454247 ps
CPU time 302.25 seconds
Started Mar 14 12:36:57 PM PDT 24
Finished Mar 14 12:42:00 PM PDT 24
Peak memory 202104 kb
Host smart-4ac44950-1ae2-4262-9df8-3e53cd13cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266546915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.4266546915
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.37677660
Short name T794
Test name
Test status
Simulation time 330228400238 ps
CPU time 63.39 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:38:01 PM PDT 24
Peak memory 202132 kb
Host smart-b97fb01d-085b-464b-b123-19165ead7d25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt
_fixed.37677660
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.316587792
Short name T518
Test name
Test status
Simulation time 163813317715 ps
CPU time 67.13 seconds
Started Mar 14 12:36:55 PM PDT 24
Finished Mar 14 12:38:03 PM PDT 24
Peak memory 202188 kb
Host smart-e4cfc6d1-57ca-4cb6-bb0b-240dfac61bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316587792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.316587792
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.374358227
Short name T624
Test name
Test status
Simulation time 488722884618 ps
CPU time 277.66 seconds
Started Mar 14 12:37:00 PM PDT 24
Finished Mar 14 12:41:37 PM PDT 24
Peak memory 202212 kb
Host smart-ab40a13b-6a0b-4a93-99e9-2022f206bba4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=374358227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.374358227
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3481212260
Short name T343
Test name
Test status
Simulation time 379046479106 ps
CPU time 927.37 seconds
Started Mar 14 12:36:54 PM PDT 24
Finished Mar 14 12:52:22 PM PDT 24
Peak memory 202152 kb
Host smart-53e9a23d-99ee-4c12-872a-a21f0f73c5cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481212260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3481212260
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1644133028
Short name T525
Test name
Test status
Simulation time 602675348918 ps
CPU time 327.46 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:42:26 PM PDT 24
Peak memory 202012 kb
Host smart-900ebb96-881a-41c7-8182-35bfba3ed0ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644133028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1644133028
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2025654358
Short name T508
Test name
Test status
Simulation time 92679494860 ps
CPU time 283.62 seconds
Started Mar 14 12:36:57 PM PDT 24
Finished Mar 14 12:41:42 PM PDT 24
Peak memory 202396 kb
Host smart-38f7327f-38d1-4f0e-91bd-07c3938e126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025654358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2025654358
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3237968978
Short name T780
Test name
Test status
Simulation time 43819881322 ps
CPU time 101.7 seconds
Started Mar 14 12:36:58 PM PDT 24
Finished Mar 14 12:38:40 PM PDT 24
Peak memory 201912 kb
Host smart-8168ac15-7949-4433-b60f-7a03363408eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237968978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3237968978
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2069012925
Short name T454
Test name
Test status
Simulation time 4058184552 ps
CPU time 2.97 seconds
Started Mar 14 12:37:01 PM PDT 24
Finished Mar 14 12:37:05 PM PDT 24
Peak memory 201924 kb
Host smart-b0681c03-53bd-4091-a3a7-0b56a86181dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069012925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2069012925
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1468116795
Short name T548
Test name
Test status
Simulation time 6056172314 ps
CPU time 5.58 seconds
Started Mar 14 12:36:57 PM PDT 24
Finished Mar 14 12:37:04 PM PDT 24
Peak memory 201916 kb
Host smart-6221a39e-e910-461e-b2fb-66fc15e4b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468116795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1468116795
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2379431023
Short name T616
Test name
Test status
Simulation time 230178352689 ps
CPU time 301.76 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:42:00 PM PDT 24
Peak memory 210760 kb
Host smart-9cddd717-3fd7-428a-8ec8-46c500bdf347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379431023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2379431023
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.626344894
Short name T444
Test name
Test status
Simulation time 322386642 ps
CPU time 1.43 seconds
Started Mar 14 12:37:05 PM PDT 24
Finished Mar 14 12:37:06 PM PDT 24
Peak memory 201820 kb
Host smart-aebee882-048e-4c59-a7e1-0fa9e4335751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626344894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.626344894
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.128094587
Short name T223
Test name
Test status
Simulation time 365902347677 ps
CPU time 191.47 seconds
Started Mar 14 12:36:57 PM PDT 24
Finished Mar 14 12:40:10 PM PDT 24
Peak memory 202128 kb
Host smart-91c465fe-7407-42a6-aa3b-aac800933ec3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128094587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.128094587
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2291777823
Short name T255
Test name
Test status
Simulation time 329828413741 ps
CPU time 770.05 seconds
Started Mar 14 12:37:00 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 202048 kb
Host smart-cbab3a84-cbeb-4e82-ba37-b2e1a11b3e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291777823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2291777823
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4229400893
Short name T232
Test name
Test status
Simulation time 167107244669 ps
CPU time 205.19 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:40:23 PM PDT 24
Peak memory 202104 kb
Host smart-a65a5845-4b47-4439-9f77-16f13b0ea654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229400893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4229400893
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.776917911
Short name T779
Test name
Test status
Simulation time 160638427906 ps
CPU time 91.87 seconds
Started Mar 14 12:36:57 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 202112 kb
Host smart-1c2babe4-d9b6-42e5-95ee-4f6c33b2801a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=776917911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.776917911
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.800026707
Short name T629
Test name
Test status
Simulation time 164523988085 ps
CPU time 377.44 seconds
Started Mar 14 12:36:56 PM PDT 24
Finished Mar 14 12:43:13 PM PDT 24
Peak memory 202084 kb
Host smart-ead6f804-9460-4ca9-bfb1-2b438974b8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800026707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.800026707
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3154927549
Short name T378
Test name
Test status
Simulation time 163342556775 ps
CPU time 400.52 seconds
Started Mar 14 12:36:55 PM PDT 24
Finished Mar 14 12:43:36 PM PDT 24
Peak memory 202360 kb
Host smart-3d82c911-5ccd-4bcf-a8c0-81f8b38fcad1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154927549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3154927549
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3191837531
Short name T247
Test name
Test status
Simulation time 184265573409 ps
CPU time 444.6 seconds
Started Mar 14 12:37:00 PM PDT 24
Finished Mar 14 12:44:25 PM PDT 24
Peak memory 202040 kb
Host smart-38018f4f-b990-4b84-9c7f-dec8013bfd23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191837531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3191837531
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.922254137
Short name T670
Test name
Test status
Simulation time 592026362329 ps
CPU time 260.59 seconds
Started Mar 14 12:36:58 PM PDT 24
Finished Mar 14 12:41:19 PM PDT 24
Peak memory 202060 kb
Host smart-e84838cd-487d-4713-9e2f-8058645b3e7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922254137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.922254137
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2445411295
Short name T206
Test name
Test status
Simulation time 111108714263 ps
CPU time 546.73 seconds
Started Mar 14 12:37:12 PM PDT 24
Finished Mar 14 12:46:19 PM PDT 24
Peak memory 202560 kb
Host smart-c4983e1b-edfb-420f-a78d-500b91522fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445411295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2445411295
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2538639555
Short name T489
Test name
Test status
Simulation time 39329738148 ps
CPU time 46.28 seconds
Started Mar 14 12:37:04 PM PDT 24
Finished Mar 14 12:37:50 PM PDT 24
Peak memory 201848 kb
Host smart-6035209a-526d-4be2-997e-b03dade9157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538639555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2538639555
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.175327404
Short name T572
Test name
Test status
Simulation time 3967354796 ps
CPU time 1.98 seconds
Started Mar 14 12:37:08 PM PDT 24
Finished Mar 14 12:37:11 PM PDT 24
Peak memory 201956 kb
Host smart-f09b6f1f-0e46-4bcf-b4fe-a656e113b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175327404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.175327404
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.754872758
Short name T46
Test name
Test status
Simulation time 6005131424 ps
CPU time 7.94 seconds
Started Mar 14 12:36:58 PM PDT 24
Finished Mar 14 12:37:06 PM PDT 24
Peak memory 201928 kb
Host smart-e4165b03-c6b7-49d9-9778-38794e155770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754872758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.754872758
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.613615174
Short name T679
Test name
Test status
Simulation time 205963967259 ps
CPU time 474.06 seconds
Started Mar 14 12:37:07 PM PDT 24
Finished Mar 14 12:45:03 PM PDT 24
Peak memory 202004 kb
Host smart-b8b24601-9ed3-477b-9e13-60bfee4dd4f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613615174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
613615174
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3641901223
Short name T44
Test name
Test status
Simulation time 192918019434 ps
CPU time 302.81 seconds
Started Mar 14 12:37:08 PM PDT 24
Finished Mar 14 12:42:12 PM PDT 24
Peak memory 210756 kb
Host smart-b2005153-89f6-4e23-a10c-8e25fb828267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641901223 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3641901223
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3788983187
Short name T512
Test name
Test status
Simulation time 373180552 ps
CPU time 0.68 seconds
Started Mar 14 12:37:04 PM PDT 24
Finished Mar 14 12:37:05 PM PDT 24
Peak memory 201836 kb
Host smart-d74ae36e-3066-4bd3-8a0a-7594f59296f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788983187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3788983187
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2909492836
Short name T284
Test name
Test status
Simulation time 169258425279 ps
CPU time 201.67 seconds
Started Mar 14 12:37:08 PM PDT 24
Finished Mar 14 12:40:31 PM PDT 24
Peak memory 201992 kb
Host smart-a4d73810-6e73-4841-84df-6c7a0c8a805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909492836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2909492836
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1012688373
Short name T751
Test name
Test status
Simulation time 162191684884 ps
CPU time 62.82 seconds
Started Mar 14 12:37:04 PM PDT 24
Finished Mar 14 12:38:07 PM PDT 24
Peak memory 202084 kb
Host smart-2434f789-b48c-4c5c-bb25-e0ba36ccd5e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012688373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1012688373
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1120978256
Short name T159
Test name
Test status
Simulation time 163935931822 ps
CPU time 37.25 seconds
Started Mar 14 12:37:05 PM PDT 24
Finished Mar 14 12:37:43 PM PDT 24
Peak memory 202144 kb
Host smart-4616bee2-6f0d-43ed-aa35-de31f3302e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120978256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1120978256
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1233621491
Short name T421
Test name
Test status
Simulation time 321584359273 ps
CPU time 388.84 seconds
Started Mar 14 12:37:06 PM PDT 24
Finished Mar 14 12:43:35 PM PDT 24
Peak memory 202088 kb
Host smart-7269597d-5a2e-4838-9346-7522b51ec744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233621491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1233621491
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.786254508
Short name T453
Test name
Test status
Simulation time 394915815047 ps
CPU time 239.75 seconds
Started Mar 14 12:37:08 PM PDT 24
Finished Mar 14 12:41:09 PM PDT 24
Peak memory 202024 kb
Host smart-64e0dc1d-f8d9-4d40-9d4a-2b5650d41efe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786254508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.786254508
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2108864768
Short name T723
Test name
Test status
Simulation time 79604832124 ps
CPU time 279.68 seconds
Started Mar 14 12:37:05 PM PDT 24
Finished Mar 14 12:41:46 PM PDT 24
Peak memory 202512 kb
Host smart-13c888da-ce75-41d7-9aae-11f7b9f15423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108864768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2108864768
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.212273010
Short name T554
Test name
Test status
Simulation time 35203915904 ps
CPU time 32.07 seconds
Started Mar 14 12:37:08 PM PDT 24
Finished Mar 14 12:37:41 PM PDT 24
Peak memory 201892 kb
Host smart-537398b4-c500-4267-ac32-4b0ce818d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212273010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.212273010
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.268763455
Short name T398
Test name
Test status
Simulation time 4884518875 ps
CPU time 2.04 seconds
Started Mar 14 12:37:07 PM PDT 24
Finished Mar 14 12:37:11 PM PDT 24
Peak memory 201880 kb
Host smart-1db3491e-a927-4283-b7a0-aa20a05d7650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268763455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.268763455
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1783680548
Short name T408
Test name
Test status
Simulation time 5820065547 ps
CPU time 15.55 seconds
Started Mar 14 12:37:09 PM PDT 24
Finished Mar 14 12:37:25 PM PDT 24
Peak memory 201860 kb
Host smart-627abe7d-a840-49db-bda4-7737d439e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783680548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1783680548
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1225141073
Short name T590
Test name
Test status
Simulation time 1155039892772 ps
CPU time 2625.19 seconds
Started Mar 14 12:37:12 PM PDT 24
Finished Mar 14 01:20:58 PM PDT 24
Peak memory 210700 kb
Host smart-5ec2b688-7f99-44e3-9281-0b6bdcb7d8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225141073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1225141073
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2267059840
Short name T507
Test name
Test status
Simulation time 330085397 ps
CPU time 0.74 seconds
Started Mar 14 12:37:13 PM PDT 24
Finished Mar 14 12:37:14 PM PDT 24
Peak memory 201916 kb
Host smart-a6eff556-1ab1-4b39-85ef-4d8b6218fbbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267059840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2267059840
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2768717979
Short name T339
Test name
Test status
Simulation time 171370427042 ps
CPU time 384.14 seconds
Started Mar 14 12:37:17 PM PDT 24
Finished Mar 14 12:43:42 PM PDT 24
Peak memory 202172 kb
Host smart-d72c232f-8aac-4afd-9af4-d4212d0ba2ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768717979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2768717979
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2622626121
Short name T695
Test name
Test status
Simulation time 353983545715 ps
CPU time 63.01 seconds
Started Mar 14 12:37:18 PM PDT 24
Finished Mar 14 12:38:22 PM PDT 24
Peak memory 202116 kb
Host smart-92b57cff-ba20-4cae-a3d5-7ed068e836db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622626121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2622626121
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2608191725
Short name T146
Test name
Test status
Simulation time 496086998715 ps
CPU time 291.14 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:42:07 PM PDT 24
Peak memory 201764 kb
Host smart-00fcf8bf-e23e-48a0-8f66-d7627cbe629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608191725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2608191725
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3317779591
Short name T504
Test name
Test status
Simulation time 488905893605 ps
CPU time 1207.68 seconds
Started Mar 14 12:37:17 PM PDT 24
Finished Mar 14 12:57:26 PM PDT 24
Peak memory 202088 kb
Host smart-f6eed40e-7bdc-4c6b-8255-02e67abe6e54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317779591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3317779591
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1119497767
Short name T105
Test name
Test status
Simulation time 493178879340 ps
CPU time 281.58 seconds
Started Mar 14 12:37:12 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 202104 kb
Host smart-e36b9d38-fb42-4bc5-983b-571bd92dbf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119497767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1119497767
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3701103774
Short name T733
Test name
Test status
Simulation time 493366751504 ps
CPU time 182.92 seconds
Started Mar 14 12:37:17 PM PDT 24
Finished Mar 14 12:40:21 PM PDT 24
Peak memory 202144 kb
Host smart-e5489033-975f-4a83-9d10-63bfc9c390ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701103774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3701103774
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3724282769
Short name T154
Test name
Test status
Simulation time 182161878638 ps
CPU time 218.93 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 202084 kb
Host smart-da7a8eb4-bd64-4f43-80c6-042d4f0a7818
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724282769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3724282769
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2243872520
Short name T405
Test name
Test status
Simulation time 416415175716 ps
CPU time 1001.76 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:53:57 PM PDT 24
Peak memory 202148 kb
Host smart-6eef5c7d-1244-43f3-88f8-862842e93547
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243872520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2243872520
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3915828571
Short name T391
Test name
Test status
Simulation time 69135514192 ps
CPU time 262.71 seconds
Started Mar 14 12:37:16 PM PDT 24
Finished Mar 14 12:41:39 PM PDT 24
Peak memory 202344 kb
Host smart-4cb1db47-b092-47e4-9de1-102f466c25db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915828571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3915828571
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4127683921
Short name T488
Test name
Test status
Simulation time 46266176827 ps
CPU time 53.98 seconds
Started Mar 14 12:37:16 PM PDT 24
Finished Mar 14 12:38:12 PM PDT 24
Peak memory 201932 kb
Host smart-cc2104bb-77c3-4cc6-aa9b-c7fadb9873a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127683921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4127683921
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2711326512
Short name T376
Test name
Test status
Simulation time 3906204339 ps
CPU time 4.32 seconds
Started Mar 14 12:37:17 PM PDT 24
Finished Mar 14 12:37:23 PM PDT 24
Peak memory 201868 kb
Host smart-71f4eb0e-e17f-4318-a2b2-5e4c3d108d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711326512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2711326512
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4124231647
Short name T614
Test name
Test status
Simulation time 6175311504 ps
CPU time 4.77 seconds
Started Mar 14 12:37:07 PM PDT 24
Finished Mar 14 12:37:12 PM PDT 24
Peak memory 201772 kb
Host smart-7e269ce5-0d4c-4e4e-9975-d7f6e306be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124231647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4124231647
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1344831021
Short name T19
Test name
Test status
Simulation time 45121115806 ps
CPU time 70.28 seconds
Started Mar 14 12:37:13 PM PDT 24
Finished Mar 14 12:38:24 PM PDT 24
Peak memory 218096 kb
Host smart-5bcc3186-f3ee-4a14-9297-3dd5a9d3c26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344831021 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1344831021
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1390574049
Short name T433
Test name
Test status
Simulation time 381849126 ps
CPU time 1.38 seconds
Started Mar 14 12:37:32 PM PDT 24
Finished Mar 14 12:37:34 PM PDT 24
Peak memory 201736 kb
Host smart-cd7c2446-2daf-44a5-8021-264f52294439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390574049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1390574049
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2763491998
Short name T251
Test name
Test status
Simulation time 336035489943 ps
CPU time 204.42 seconds
Started Mar 14 12:37:23 PM PDT 24
Finished Mar 14 12:40:48 PM PDT 24
Peak memory 202072 kb
Host smart-8df9dd20-f826-4ae7-be6a-2ebb9245bcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763491998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2763491998
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2103553431
Short name T296
Test name
Test status
Simulation time 333440334577 ps
CPU time 738.65 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:49:34 PM PDT 24
Peak memory 202148 kb
Host smart-2fae15d4-572e-4118-9883-57e4c914228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103553431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2103553431
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2831559036
Short name T406
Test name
Test status
Simulation time 328909916942 ps
CPU time 205.61 seconds
Started Mar 14 12:37:14 PM PDT 24
Finished Mar 14 12:40:40 PM PDT 24
Peak memory 202068 kb
Host smart-3549e6ec-f5d1-4272-9d76-65ffab9c64c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831559036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2831559036
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1187281163
Short name T291
Test name
Test status
Simulation time 487078467800 ps
CPU time 477.44 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:45:13 PM PDT 24
Peak memory 201700 kb
Host smart-d757c3ca-d615-4dd7-9492-759337b0c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187281163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1187281163
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3755607328
Short name T490
Test name
Test status
Simulation time 478201980746 ps
CPU time 574.63 seconds
Started Mar 14 12:37:16 PM PDT 24
Finished Mar 14 12:46:51 PM PDT 24
Peak memory 202036 kb
Host smart-e33a7b1c-c76e-40a2-9a21-4d719a7fbcc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755607328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3755607328
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.665023035
Short name T569
Test name
Test status
Simulation time 189568338543 ps
CPU time 124.39 seconds
Started Mar 14 12:37:26 PM PDT 24
Finished Mar 14 12:39:30 PM PDT 24
Peak memory 202096 kb
Host smart-e4bbaa8b-46ac-415b-8f19-edfc3b558b76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665023035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.665023035
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3571858115
Short name T457
Test name
Test status
Simulation time 206476923549 ps
CPU time 517.47 seconds
Started Mar 14 12:37:25 PM PDT 24
Finished Mar 14 12:46:02 PM PDT 24
Peak memory 202076 kb
Host smart-0eae1c9f-e4e9-4f5c-aca4-aacefcd23c4a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571858115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3571858115
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1662638030
Short name T473
Test name
Test status
Simulation time 74206330238 ps
CPU time 429.43 seconds
Started Mar 14 12:37:24 PM PDT 24
Finished Mar 14 12:44:34 PM PDT 24
Peak memory 202328 kb
Host smart-8678516a-3f93-4b5d-a5fd-b231d1278d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662638030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1662638030
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2351825176
Short name T485
Test name
Test status
Simulation time 25070738966 ps
CPU time 6.69 seconds
Started Mar 14 12:37:25 PM PDT 24
Finished Mar 14 12:37:32 PM PDT 24
Peak memory 201892 kb
Host smart-1164066f-fc82-4290-a0e2-8c7aa5acc02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351825176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2351825176
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.652258947
Short name T503
Test name
Test status
Simulation time 3200845542 ps
CPU time 7.49 seconds
Started Mar 14 12:37:24 PM PDT 24
Finished Mar 14 12:37:32 PM PDT 24
Peak memory 201952 kb
Host smart-0dd29a73-bd38-462e-b2ce-1b4223a21c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652258947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.652258947
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1746848654
Short name T357
Test name
Test status
Simulation time 6055733626 ps
CPU time 16.75 seconds
Started Mar 14 12:37:15 PM PDT 24
Finished Mar 14 12:37:32 PM PDT 24
Peak memory 201928 kb
Host smart-55e6e7fb-9cc7-4095-9403-928f353f09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746848654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1746848654
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2201707204
Short name T760
Test name
Test status
Simulation time 402392418305 ps
CPU time 1164.08 seconds
Started Mar 14 12:37:33 PM PDT 24
Finished Mar 14 12:56:57 PM PDT 24
Peak memory 210632 kb
Host smart-f509732a-c79a-4d37-842f-f6a92b38a7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201707204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2201707204
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3669184280
Short name T13
Test name
Test status
Simulation time 43216627736 ps
CPU time 116.07 seconds
Started Mar 14 12:37:23 PM PDT 24
Finished Mar 14 12:39:19 PM PDT 24
Peak memory 210848 kb
Host smart-fbcfa292-f57c-4fe4-bdf5-de5b7fc95b03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669184280 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3669184280
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.821634474
Short name T721
Test name
Test status
Simulation time 436627067 ps
CPU time 0.85 seconds
Started Mar 14 12:37:46 PM PDT 24
Finished Mar 14 12:37:47 PM PDT 24
Peak memory 201916 kb
Host smart-3eadc27a-c4f2-44f8-989b-cb7980af4b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821634474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.821634474
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1856506826
Short name T550
Test name
Test status
Simulation time 326554459087 ps
CPU time 795.61 seconds
Started Mar 14 12:37:36 PM PDT 24
Finished Mar 14 12:50:52 PM PDT 24
Peak memory 202192 kb
Host smart-2de95c53-0a80-465e-8ec6-351e3742e24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856506826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1856506826
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.773127302
Short name T696
Test name
Test status
Simulation time 493771690055 ps
CPU time 1113.61 seconds
Started Mar 14 12:37:33 PM PDT 24
Finished Mar 14 12:56:07 PM PDT 24
Peak memory 202080 kb
Host smart-e47ddba2-5e4f-46ef-b62b-8fed80f07366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773127302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.773127302
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1734083529
Short name T535
Test name
Test status
Simulation time 162180052698 ps
CPU time 98.76 seconds
Started Mar 14 12:37:32 PM PDT 24
Finished Mar 14 12:39:11 PM PDT 24
Peak memory 202092 kb
Host smart-5803b9a6-b8e7-4bd7-a585-c6a1325514fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734083529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1734083529
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2244190511
Short name T766
Test name
Test status
Simulation time 167782668242 ps
CPU time 101.98 seconds
Started Mar 14 12:37:34 PM PDT 24
Finished Mar 14 12:39:16 PM PDT 24
Peak memory 202164 kb
Host smart-2e41606c-5e9a-494a-afc6-df608bd55c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244190511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2244190511
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3530845778
Short name T50
Test name
Test status
Simulation time 323046601197 ps
CPU time 282.23 seconds
Started Mar 14 12:37:32 PM PDT 24
Finished Mar 14 12:42:15 PM PDT 24
Peak memory 202040 kb
Host smart-31907177-5fd7-4a59-abf5-421fd923237f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530845778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3530845778
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1091782682
Short name T293
Test name
Test status
Simulation time 179431027129 ps
CPU time 393.09 seconds
Started Mar 14 12:37:34 PM PDT 24
Finished Mar 14 12:44:07 PM PDT 24
Peak memory 202020 kb
Host smart-23fe450f-1ce8-4304-81dc-f8a290b05fc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091782682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1091782682
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2492908189
Short name T775
Test name
Test status
Simulation time 610193576005 ps
CPU time 164.15 seconds
Started Mar 14 12:37:34 PM PDT 24
Finished Mar 14 12:40:18 PM PDT 24
Peak memory 202080 kb
Host smart-856befb0-7270-44d9-b38b-7656efb3851b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492908189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2492908189
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2883542847
Short name T437
Test name
Test status
Simulation time 122203591865 ps
CPU time 391.25 seconds
Started Mar 14 12:37:37 PM PDT 24
Finished Mar 14 12:44:08 PM PDT 24
Peak memory 202420 kb
Host smart-9e17d95b-cbe1-4b3b-bd66-39c7fb90b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883542847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2883542847
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3387261417
Short name T610
Test name
Test status
Simulation time 43740141947 ps
CPU time 54.97 seconds
Started Mar 14 12:37:35 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 201904 kb
Host smart-ef5419d3-7bdf-49c7-8423-20e6ac0dd1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387261417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3387261417
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3284230602
Short name T493
Test name
Test status
Simulation time 4174550155 ps
CPU time 2.02 seconds
Started Mar 14 12:37:36 PM PDT 24
Finished Mar 14 12:37:39 PM PDT 24
Peak memory 202040 kb
Host smart-0765beac-c41b-4364-ac82-9fe865e3cf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284230602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3284230602
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.885840512
Short name T480
Test name
Test status
Simulation time 5827537052 ps
CPU time 14.24 seconds
Started Mar 14 12:37:34 PM PDT 24
Finished Mar 14 12:37:49 PM PDT 24
Peak memory 201960 kb
Host smart-0c2d8bd0-8f92-4ca9-a1c8-ec7a5ba9d497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885840512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.885840512
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3358077547
Short name T621
Test name
Test status
Simulation time 355348683178 ps
CPU time 222.93 seconds
Started Mar 14 12:37:34 PM PDT 24
Finished Mar 14 12:41:17 PM PDT 24
Peak memory 202208 kb
Host smart-7cfe004f-f039-4c57-abe8-d4843ff35eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358077547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3358077547
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2728248775
Short name T468
Test name
Test status
Simulation time 343124700 ps
CPU time 1.37 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:37:50 PM PDT 24
Peak memory 201856 kb
Host smart-c3d363ab-4875-443d-84be-8c93ea1f5e68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728248775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2728248775
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.145206888
Short name T276
Test name
Test status
Simulation time 164356364482 ps
CPU time 371.32 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:43:59 PM PDT 24
Peak memory 202104 kb
Host smart-bb1dcf88-6825-4232-9f34-0222c10346a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145206888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.145206888
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3646820136
Short name T715
Test name
Test status
Simulation time 329043585755 ps
CPU time 405.82 seconds
Started Mar 14 12:37:45 PM PDT 24
Finished Mar 14 12:44:31 PM PDT 24
Peak memory 202032 kb
Host smart-a6c5b665-a67b-43e1-b76f-88820e8ee62b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646820136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3646820136
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.624748764
Short name T147
Test name
Test status
Simulation time 326311730834 ps
CPU time 401.69 seconds
Started Mar 14 12:37:49 PM PDT 24
Finished Mar 14 12:44:31 PM PDT 24
Peak memory 202224 kb
Host smart-8d560942-d207-4739-9f41-379742296c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624748764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.624748764
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.138743380
Short name T577
Test name
Test status
Simulation time 165318699787 ps
CPU time 389.3 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:44:18 PM PDT 24
Peak memory 202088 kb
Host smart-ce764208-1193-4248-a35d-0267b757c0dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=138743380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.138743380
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4290576026
Short name T314
Test name
Test status
Simulation time 660120913990 ps
CPU time 375.75 seconds
Started Mar 14 12:37:45 PM PDT 24
Finished Mar 14 12:44:01 PM PDT 24
Peak memory 202092 kb
Host smart-851e10d1-0868-4a21-aaad-04ccc701d7c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290576026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4290576026
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2186501876
Short name T672
Test name
Test status
Simulation time 606307452751 ps
CPU time 370.54 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:43:59 PM PDT 24
Peak memory 202208 kb
Host smart-bfdc742d-db20-4db0-bb01-b9504b46ed7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186501876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2186501876
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.175901698
Short name T56
Test name
Test status
Simulation time 115775897146 ps
CPU time 387.63 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:44:15 PM PDT 24
Peak memory 202252 kb
Host smart-62ce9de2-a0cb-4d35-b459-9b595297105a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175901698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.175901698
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1715674120
Short name T603
Test name
Test status
Simulation time 42352277099 ps
CPU time 96.6 seconds
Started Mar 14 12:37:46 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 201916 kb
Host smart-0c5ac6e0-fd21-47c2-9172-f9df9dc7d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715674120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1715674120
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2208615648
Short name T619
Test name
Test status
Simulation time 5627922809 ps
CPU time 3.8 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:37:51 PM PDT 24
Peak memory 201880 kb
Host smart-05d46755-9c41-4f19-ba79-8f891dad5382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208615648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2208615648
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2441803101
Short name T565
Test name
Test status
Simulation time 5946057537 ps
CPU time 6.35 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:37:55 PM PDT 24
Peak memory 201948 kb
Host smart-82a588f7-8d4e-4ae7-b665-50e1992e87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441803101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2441803101
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.29706007
Short name T172
Test name
Test status
Simulation time 367775022455 ps
CPU time 200.64 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:41:09 PM PDT 24
Peak memory 202160 kb
Host smart-79e7ce6a-8c27-45f0-973c-03f22ccab0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.29706007
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2886665328
Short name T41
Test name
Test status
Simulation time 265135317247 ps
CPU time 65.99 seconds
Started Mar 14 12:37:46 PM PDT 24
Finished Mar 14 12:38:52 PM PDT 24
Peak memory 210424 kb
Host smart-26fcc531-6722-4beb-99ea-8ed5bd324031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886665328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2886665328
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3598715260
Short name T113
Test name
Test status
Simulation time 325012710 ps
CPU time 1.38 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:37:58 PM PDT 24
Peak memory 201836 kb
Host smart-f606af65-aefa-4b10-a5c3-c66a117eb716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598715260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3598715260
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3268388380
Short name T539
Test name
Test status
Simulation time 173077421623 ps
CPU time 64.13 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:38:51 PM PDT 24
Peak memory 202204 kb
Host smart-15132a6e-bf8e-4a02-8e05-c90a402cf0d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268388380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3268388380
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.63953094
Short name T396
Test name
Test status
Simulation time 173743616031 ps
CPU time 90.03 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:39:29 PM PDT 24
Peak memory 202060 kb
Host smart-0d52ed34-1f72-4cd9-95a7-56cc5e756af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63953094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.63953094
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1788784393
Short name T104
Test name
Test status
Simulation time 159264434784 ps
CPU time 96.08 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:39:24 PM PDT 24
Peak memory 202032 kb
Host smart-12d5c8e6-50ed-4178-aa04-5ef7b9f07d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788784393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1788784393
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.514617675
Short name T537
Test name
Test status
Simulation time 164652345840 ps
CPU time 203.13 seconds
Started Mar 14 12:37:47 PM PDT 24
Finished Mar 14 12:41:10 PM PDT 24
Peak memory 202156 kb
Host smart-12cad58e-6ff5-487c-849d-5303cd643494
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=514617675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.514617675
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.4213766898
Short name T772
Test name
Test status
Simulation time 159155708923 ps
CPU time 353.16 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:43:42 PM PDT 24
Peak memory 202164 kb
Host smart-2598e058-974a-49ba-9685-ce4d87abf6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213766898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.4213766898
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3901976672
Short name T414
Test name
Test status
Simulation time 162257308086 ps
CPU time 178.06 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:40:47 PM PDT 24
Peak memory 202180 kb
Host smart-5e47bedf-398c-4617-98a7-5894b04c39c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901976672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3901976672
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3308813235
Short name T279
Test name
Test status
Simulation time 383361750212 ps
CPU time 450.96 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:45:19 PM PDT 24
Peak memory 202124 kb
Host smart-7747ed9d-c371-4d4c-adcc-ca97ed733bfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308813235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3308813235
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2192129095
Short name T667
Test name
Test status
Simulation time 604014900069 ps
CPU time 702.1 seconds
Started Mar 14 12:37:48 PM PDT 24
Finished Mar 14 12:49:31 PM PDT 24
Peak memory 202208 kb
Host smart-b53c22aa-cd0e-48cb-9830-304ac30d1e45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192129095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2192129095
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3288126588
Short name T719
Test name
Test status
Simulation time 90926760225 ps
CPU time 510.33 seconds
Started Mar 14 12:38:00 PM PDT 24
Finished Mar 14 12:46:31 PM PDT 24
Peak memory 202480 kb
Host smart-088e83d9-3784-41a7-90b3-5302a3de1c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288126588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3288126588
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2389884537
Short name T533
Test name
Test status
Simulation time 32922015123 ps
CPU time 42.1 seconds
Started Mar 14 12:37:58 PM PDT 24
Finished Mar 14 12:38:40 PM PDT 24
Peak memory 201876 kb
Host smart-cda14fbb-eafd-4c72-b199-f3f893560e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389884537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2389884537
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2892589637
Short name T712
Test name
Test status
Simulation time 3777755996 ps
CPU time 3.08 seconds
Started Mar 14 12:37:55 PM PDT 24
Finished Mar 14 12:37:59 PM PDT 24
Peak memory 201828 kb
Host smart-f58bfd2d-b04b-426a-be2b-11a396dfb574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892589637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2892589637
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1010626037
Short name T700
Test name
Test status
Simulation time 5889075138 ps
CPU time 4.39 seconds
Started Mar 14 12:37:49 PM PDT 24
Finished Mar 14 12:37:54 PM PDT 24
Peak memory 201920 kb
Host smart-fadb9d51-687d-46e7-97d7-d81f43499b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010626037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1010626037
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.894098646
Short name T212
Test name
Test status
Simulation time 459241243392 ps
CPU time 945.05 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:53:44 PM PDT 24
Peak memory 202448 kb
Host smart-7e5433fe-469a-4247-a70c-1382debc6336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894098646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
894098646
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.102751408
Short name T323
Test name
Test status
Simulation time 194963886252 ps
CPU time 148.47 seconds
Started Mar 14 12:37:58 PM PDT 24
Finished Mar 14 12:40:27 PM PDT 24
Peak memory 210500 kb
Host smart-039f397a-181d-4445-a039-b43a812599e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102751408 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.102751408
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2341144225
Short name T445
Test name
Test status
Simulation time 356432997 ps
CPU time 1 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:38:00 PM PDT 24
Peak memory 201856 kb
Host smart-e4f777c2-e10f-41af-8fbc-47edf2bd6916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341144225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2341144225
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2640103400
Short name T257
Test name
Test status
Simulation time 359201033216 ps
CPU time 128.67 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:40:06 PM PDT 24
Peak memory 202152 kb
Host smart-afdefd8e-fdac-4b61-b0cc-629fcb0be567
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640103400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2640103400
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1923511107
Short name T258
Test name
Test status
Simulation time 492517272694 ps
CPU time 366.15 seconds
Started Mar 14 12:38:00 PM PDT 24
Finished Mar 14 12:44:06 PM PDT 24
Peak memory 202112 kb
Host smart-ae3cef98-7e80-4375-8a5b-433b281c386d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923511107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1923511107
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3209262609
Short name T98
Test name
Test status
Simulation time 494045632035 ps
CPU time 611.45 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:48:11 PM PDT 24
Peak memory 202036 kb
Host smart-9e679d23-c00a-4613-a271-abe29932297f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209262609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3209262609
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.963728671
Short name T151
Test name
Test status
Simulation time 163416704553 ps
CPU time 51.52 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:38:50 PM PDT 24
Peak memory 202124 kb
Host smart-c2e0e7cf-4cef-4540-8683-8e3d26f19ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963728671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.963728671
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3551707345
Short name T605
Test name
Test status
Simulation time 321420317134 ps
CPU time 179.53 seconds
Started Mar 14 12:38:02 PM PDT 24
Finished Mar 14 12:41:02 PM PDT 24
Peak memory 202032 kb
Host smart-5be1364d-a7c3-4522-b75f-3e4d68f81bfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551707345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3551707345
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.73382223
Short name T443
Test name
Test status
Simulation time 401038728167 ps
CPU time 886.87 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:52:44 PM PDT 24
Peak memory 202136 kb
Host smart-0d876b0f-66d5-4b43-966c-5bacf79927d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73382223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_w
akeup.73382223
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1240702898
Short name T578
Test name
Test status
Simulation time 399507143480 ps
CPU time 185.96 seconds
Started Mar 14 12:38:00 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 202176 kb
Host smart-31b8d271-bcba-40e9-ba42-67ef2a8993e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240702898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1240702898
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1994030052
Short name T211
Test name
Test status
Simulation time 131084811123 ps
CPU time 425.75 seconds
Started Mar 14 12:37:58 PM PDT 24
Finished Mar 14 12:45:04 PM PDT 24
Peak memory 202324 kb
Host smart-a4c5c5d9-1c66-4be9-b791-d27640fbc90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994030052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1994030052
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2439366184
Short name T359
Test name
Test status
Simulation time 31851496333 ps
CPU time 78.83 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:39:16 PM PDT 24
Peak memory 201912 kb
Host smart-22fa76cc-dfbc-4f86-b0f6-0d3f039b3e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439366184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2439366184
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3580475984
Short name T642
Test name
Test status
Simulation time 4109401190 ps
CPU time 3.1 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:38:00 PM PDT 24
Peak memory 201832 kb
Host smart-a4dffa4c-3fcb-4eb1-a466-81eb3a2f1e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580475984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3580475984
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3436683108
Short name T699
Test name
Test status
Simulation time 5538243418 ps
CPU time 8.06 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:38:05 PM PDT 24
Peak memory 201908 kb
Host smart-3aad2f81-098c-4bc3-a20f-0d69ee3aeb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436683108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3436683108
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2429062693
Short name T214
Test name
Test status
Simulation time 529137880764 ps
CPU time 496.77 seconds
Started Mar 14 12:37:58 PM PDT 24
Finished Mar 14 12:46:15 PM PDT 24
Peak memory 210736 kb
Host smart-09976d40-95b4-475e-a111-614facb0662e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429062693 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2429062693
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.4084222115
Short name T758
Test name
Test status
Simulation time 416991701 ps
CPU time 1.59 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:38:09 PM PDT 24
Peak memory 201848 kb
Host smart-86dee003-8964-4242-a386-ed2e509e2076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084222115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.4084222115
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.339719165
Short name T171
Test name
Test status
Simulation time 535312091297 ps
CPU time 308.34 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:43:16 PM PDT 24
Peak memory 202144 kb
Host smart-1d24faa3-9c63-4e4b-95d5-fddb33806f81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339719165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.339719165
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.722261712
Short name T290
Test name
Test status
Simulation time 562432657903 ps
CPU time 347.68 seconds
Started Mar 14 12:38:08 PM PDT 24
Finished Mar 14 12:43:56 PM PDT 24
Peak memory 202040 kb
Host smart-9bb0adb8-eb16-4077-991e-84492912e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722261712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.722261712
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3013498440
Short name T324
Test name
Test status
Simulation time 328340892249 ps
CPU time 828.8 seconds
Started Mar 14 12:37:58 PM PDT 24
Finished Mar 14 12:51:47 PM PDT 24
Peak memory 202132 kb
Host smart-55f087e6-180a-429a-af41-87f82482c5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013498440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3013498440
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1043286134
Short name T623
Test name
Test status
Simulation time 495749910531 ps
CPU time 960.37 seconds
Started Mar 14 12:38:04 PM PDT 24
Finished Mar 14 12:54:05 PM PDT 24
Peak memory 202140 kb
Host smart-74e49b13-3e0f-4086-a2b0-407ec0029208
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043286134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1043286134
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3987620189
Short name T426
Test name
Test status
Simulation time 325708756064 ps
CPU time 192.5 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:41:10 PM PDT 24
Peak memory 202132 kb
Host smart-67eb605f-5207-4c84-b6db-6b08e8d7988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987620189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3987620189
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2455791500
Short name T638
Test name
Test status
Simulation time 162517928143 ps
CPU time 39.75 seconds
Started Mar 14 12:37:57 PM PDT 24
Finished Mar 14 12:38:37 PM PDT 24
Peak memory 201988 kb
Host smart-eadb6795-51e1-42ef-a68c-b4d591df821d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455791500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2455791500
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2535829006
Short name T198
Test name
Test status
Simulation time 568449809973 ps
CPU time 324.16 seconds
Started Mar 14 12:38:06 PM PDT 24
Finished Mar 14 12:43:30 PM PDT 24
Peak memory 202064 kb
Host smart-d56581dc-54eb-44b4-aa56-3509fc94692d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535829006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2535829006
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.540541782
Short name T515
Test name
Test status
Simulation time 592749237759 ps
CPU time 1457.72 seconds
Started Mar 14 12:38:06 PM PDT 24
Finished Mar 14 01:02:24 PM PDT 24
Peak memory 202096 kb
Host smart-9af3ef60-0f4f-4633-ac17-9a45e8a465a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540541782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.540541782
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3969727907
Short name T204
Test name
Test status
Simulation time 114026792351 ps
CPU time 449.52 seconds
Started Mar 14 12:38:06 PM PDT 24
Finished Mar 14 12:45:36 PM PDT 24
Peak memory 202420 kb
Host smart-08d895dd-ab50-446b-a366-036482b821cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969727907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3969727907
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3316357266
Short name T701
Test name
Test status
Simulation time 37371544861 ps
CPU time 22.69 seconds
Started Mar 14 12:38:05 PM PDT 24
Finished Mar 14 12:38:28 PM PDT 24
Peak memory 201924 kb
Host smart-0bda0696-b3e2-489c-9f8c-85c319b44df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316357266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3316357266
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2850941865
Short name T661
Test name
Test status
Simulation time 3314441087 ps
CPU time 2.48 seconds
Started Mar 14 12:38:05 PM PDT 24
Finished Mar 14 12:38:08 PM PDT 24
Peak memory 201884 kb
Host smart-cc24bc5a-b7ed-494d-9a5c-778ac68e8abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850941865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2850941865
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1007994580
Short name T45
Test name
Test status
Simulation time 6112570124 ps
CPU time 8.37 seconds
Started Mar 14 12:37:59 PM PDT 24
Finished Mar 14 12:38:07 PM PDT 24
Peak memory 201908 kb
Host smart-85ab24a1-3639-445b-9811-64ecd6ebef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007994580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1007994580
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.114800045
Short name T423
Test name
Test status
Simulation time 12645761981 ps
CPU time 3.15 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:38:10 PM PDT 24
Peak memory 202188 kb
Host smart-41f3059f-b841-4cf5-90bf-4a16cf8a89c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114800045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all.
114800045
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.631413753
Short name T786
Test name
Test status
Simulation time 139840193218 ps
CPU time 91.03 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:39:38 PM PDT 24
Peak memory 218280 kb
Host smart-57573950-c813-4f7b-b59c-03697f96d4a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631413753 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.631413753
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3848544019
Short name T705
Test name
Test status
Simulation time 369377782 ps
CPU time 0.76 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:34:02 PM PDT 24
Peak memory 201816 kb
Host smart-56334c12-272e-4f04-8620-e8385082a1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848544019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3848544019
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1297792715
Short name T744
Test name
Test status
Simulation time 170722640929 ps
CPU time 407.17 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:40:47 PM PDT 24
Peak memory 202012 kb
Host smart-ff5efbd1-1e8e-4a08-b390-d66ffd070622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297792715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1297792715
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1320251426
Short name T765
Test name
Test status
Simulation time 325495625257 ps
CPU time 236.32 seconds
Started Mar 14 12:34:12 PM PDT 24
Finished Mar 14 12:38:08 PM PDT 24
Peak memory 202168 kb
Host smart-de112007-f018-469c-8632-8823722c5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320251426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1320251426
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1588327932
Short name T174
Test name
Test status
Simulation time 328017162891 ps
CPU time 144.04 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:36:26 PM PDT 24
Peak memory 202112 kb
Host smart-1ca3a13e-5526-4dd0-95c6-3cb1f3d5f628
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588327932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1588327932
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2819102398
Short name T288
Test name
Test status
Simulation time 329836731964 ps
CPU time 190.54 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:37:19 PM PDT 24
Peak memory 201940 kb
Host smart-9fc9e37e-ee09-4447-b7af-811a5c19f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819102398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2819102398
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2347538880
Short name T684
Test name
Test status
Simulation time 499450941432 ps
CPU time 1153.68 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:53:22 PM PDT 24
Peak memory 202108 kb
Host smart-03f8084b-77d2-4e47-b659-ab15ef9384ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347538880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2347538880
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2158435143
Short name T256
Test name
Test status
Simulation time 366782326213 ps
CPU time 786.19 seconds
Started Mar 14 12:34:11 PM PDT 24
Finished Mar 14 12:47:18 PM PDT 24
Peak memory 201972 kb
Host smart-34c828a2-01ec-470c-a61e-b4d88ef69882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158435143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2158435143
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2681284524
Short name T592
Test name
Test status
Simulation time 398323394001 ps
CPU time 196.01 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:37:42 PM PDT 24
Peak memory 202088 kb
Host smart-7745545b-1f19-48f6-9002-b64ee2f16433
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681284524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2681284524
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2424968109
Short name T527
Test name
Test status
Simulation time 39482382444 ps
CPU time 89.26 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:35:30 PM PDT 24
Peak memory 201900 kb
Host smart-d51e41c9-103d-49c8-bf4a-ff36bb551ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424968109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2424968109
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1394935767
Short name T377
Test name
Test status
Simulation time 3935981735 ps
CPU time 2.12 seconds
Started Mar 14 12:34:13 PM PDT 24
Finished Mar 14 12:34:16 PM PDT 24
Peak memory 201932 kb
Host smart-20e48515-ca9b-4c6f-b851-207872f39df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394935767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1394935767
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1455457636
Short name T73
Test name
Test status
Simulation time 7840293077 ps
CPU time 3.24 seconds
Started Mar 14 12:34:20 PM PDT 24
Finished Mar 14 12:34:23 PM PDT 24
Peak memory 218784 kb
Host smart-76ef0aff-37f0-4f13-a62c-18d4ae9eacc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455457636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1455457636
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1987020187
Short name T427
Test name
Test status
Simulation time 5589746337 ps
CPU time 4.28 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:34:05 PM PDT 24
Peak memory 201948 kb
Host smart-13ab63db-9197-41b2-9a72-c3f310aa6f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987020187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1987020187
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1154353185
Short name T476
Test name
Test status
Simulation time 328051149733 ps
CPU time 1072.63 seconds
Started Mar 14 12:34:06 PM PDT 24
Finished Mar 14 12:51:58 PM PDT 24
Peak memory 202444 kb
Host smart-4507c731-0d7f-4535-a8d3-e03b2154c6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154353185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1154353185
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2712048669
Short name T461
Test name
Test status
Simulation time 322679942 ps
CPU time 0.81 seconds
Started Mar 14 12:38:16 PM PDT 24
Finished Mar 14 12:38:17 PM PDT 24
Peak memory 201796 kb
Host smart-3d8e1c99-64b7-4308-8b4a-ea135cbebc8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712048669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2712048669
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2368526596
Short name T313
Test name
Test status
Simulation time 389348482537 ps
CPU time 104.52 seconds
Started Mar 14 12:38:14 PM PDT 24
Finished Mar 14 12:39:59 PM PDT 24
Peak memory 202164 kb
Host smart-06af5a30-4678-4069-ab4d-41c67988ccd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368526596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2368526596
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.479013543
Short name T307
Test name
Test status
Simulation time 164646742658 ps
CPU time 36.07 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:38:44 PM PDT 24
Peak memory 202032 kb
Host smart-070e6bf9-0217-4f1b-8d62-770513d6198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479013543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.479013543
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.569234729
Short name T526
Test name
Test status
Simulation time 324443410646 ps
CPU time 308.6 seconds
Started Mar 14 12:38:07 PM PDT 24
Finished Mar 14 12:43:16 PM PDT 24
Peak memory 202128 kb
Host smart-428103b0-c685-47b9-a5ff-55e78d14f618
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=569234729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.569234729
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.48019301
Short name T451
Test name
Test status
Simulation time 163583855927 ps
CPU time 212.85 seconds
Started Mar 14 12:38:08 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 202128 kb
Host smart-0bf0aa32-daba-497d-b553-3c03b7334633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48019301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.48019301
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3786674626
Short name T655
Test name
Test status
Simulation time 490261394395 ps
CPU time 312.09 seconds
Started Mar 14 12:38:06 PM PDT 24
Finished Mar 14 12:43:18 PM PDT 24
Peak memory 202048 kb
Host smart-dd8da568-cfa4-4665-aeec-a9c525945305
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786674626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3786674626
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3475971005
Short name T52
Test name
Test status
Simulation time 91146763088 ps
CPU time 499.24 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:46:38 PM PDT 24
Peak memory 202436 kb
Host smart-e991dd75-407d-4f75-8d25-c661c3d2325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475971005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3475971005
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3865967888
Short name T388
Test name
Test status
Simulation time 35812476831 ps
CPU time 43.07 seconds
Started Mar 14 12:38:16 PM PDT 24
Finished Mar 14 12:38:59 PM PDT 24
Peak memory 201956 kb
Host smart-b5584884-d315-4aec-921a-ee5ea806e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865967888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3865967888
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3619085320
Short name T511
Test name
Test status
Simulation time 4625183312 ps
CPU time 5.07 seconds
Started Mar 14 12:38:15 PM PDT 24
Finished Mar 14 12:38:20 PM PDT 24
Peak memory 201972 kb
Host smart-d71ec89d-0a05-4d27-bf66-70106fb77c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619085320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3619085320
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.574711233
Short name T585
Test name
Test status
Simulation time 5580749122 ps
CPU time 2.4 seconds
Started Mar 14 12:38:08 PM PDT 24
Finished Mar 14 12:38:11 PM PDT 24
Peak memory 201972 kb
Host smart-563973a2-cdd1-407e-bf28-b467425c92aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574711233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.574711233
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3219733541
Short name T598
Test name
Test status
Simulation time 248862327595 ps
CPU time 331.37 seconds
Started Mar 14 12:38:16 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 212444 kb
Host smart-4da0281d-5e20-4d70-aa36-1408adcec863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219733541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3219733541
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3344728692
Short name T261
Test name
Test status
Simulation time 49971697541 ps
CPU time 107.58 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:40:07 PM PDT 24
Peak memory 210952 kb
Host smart-7b1b758b-c605-48ae-b595-953dd84065f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344728692 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3344728692
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3951633362
Short name T668
Test name
Test status
Simulation time 300818064 ps
CPU time 1.32 seconds
Started Mar 14 12:38:24 PM PDT 24
Finished Mar 14 12:38:25 PM PDT 24
Peak memory 201900 kb
Host smart-9bde9f0e-e1a2-4cb6-b89f-51e869b33374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951633362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3951633362
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2156305673
Short name T298
Test name
Test status
Simulation time 374846853509 ps
CPU time 60.66 seconds
Started Mar 14 12:38:16 PM PDT 24
Finished Mar 14 12:39:17 PM PDT 24
Peak memory 202180 kb
Host smart-c58b9c9d-f2f7-4fc9-8d42-e5ae2bbf7e01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156305673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2156305673
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1415607339
Short name T238
Test name
Test status
Simulation time 171627044407 ps
CPU time 106.61 seconds
Started Mar 14 12:38:15 PM PDT 24
Finished Mar 14 12:40:02 PM PDT 24
Peak memory 202048 kb
Host smart-11e62a4d-5e97-46eb-85f3-bb3b6d2fc596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415607339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1415607339
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1891673345
Short name T277
Test name
Test status
Simulation time 160528384253 ps
CPU time 368.19 seconds
Started Mar 14 12:38:17 PM PDT 24
Finished Mar 14 12:44:25 PM PDT 24
Peak memory 202068 kb
Host smart-4778fa54-7f5c-4b92-a597-a402921cf53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891673345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1891673345
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1885793733
Short name T449
Test name
Test status
Simulation time 494504369697 ps
CPU time 294.09 seconds
Started Mar 14 12:38:16 PM PDT 24
Finished Mar 14 12:43:10 PM PDT 24
Peak memory 202100 kb
Host smart-65347b90-5287-4e97-a3f6-e0cf203149fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885793733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1885793733
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.719184032
Short name T308
Test name
Test status
Simulation time 168011197437 ps
CPU time 101.1 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:40:00 PM PDT 24
Peak memory 202132 kb
Host smart-156bbd12-85cd-42c6-b051-a47c9cac9c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719184032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.719184032
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.4126862233
Short name T401
Test name
Test status
Simulation time 163313843220 ps
CPU time 93.6 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:39:53 PM PDT 24
Peak memory 202112 kb
Host smart-dcd8de7e-a797-4faf-b8ea-35e614dc846b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126862233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.4126862233
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.540875816
Short name T195
Test name
Test status
Simulation time 533708465625 ps
CPU time 111.02 seconds
Started Mar 14 12:38:17 PM PDT 24
Finished Mar 14 12:40:08 PM PDT 24
Peak memory 202140 kb
Host smart-dab6372c-2563-444f-88e2-2858dcb33768
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540875816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.540875816
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.580120753
Short name T770
Test name
Test status
Simulation time 428995247387 ps
CPU time 282.14 seconds
Started Mar 14 12:38:19 PM PDT 24
Finished Mar 14 12:43:01 PM PDT 24
Peak memory 202176 kb
Host smart-846aecda-45bb-4855-83dc-970ca082b6b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580120753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.580120753
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2644373264
Short name T352
Test name
Test status
Simulation time 136203638408 ps
CPU time 684.22 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:49:49 PM PDT 24
Peak memory 202324 kb
Host smart-e8d803f0-6282-4157-8fe9-57abb9e84c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644373264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2644373264
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.119248961
Short name T513
Test name
Test status
Simulation time 29427054172 ps
CPU time 18.2 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:38:43 PM PDT 24
Peak memory 201960 kb
Host smart-e9a15daa-eb28-4b21-a7c6-ebc1f2853e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119248961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.119248961
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1836414632
Short name T727
Test name
Test status
Simulation time 4382788814 ps
CPU time 3.43 seconds
Started Mar 14 12:38:14 PM PDT 24
Finished Mar 14 12:38:18 PM PDT 24
Peak memory 202028 kb
Host smart-6c795376-73a6-49eb-976b-be8b2e841e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836414632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1836414632
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3430943227
Short name T505
Test name
Test status
Simulation time 6012950411 ps
CPU time 2.41 seconds
Started Mar 14 12:38:20 PM PDT 24
Finished Mar 14 12:38:22 PM PDT 24
Peak memory 201876 kb
Host smart-4f6e8997-0179-4794-b2c0-c91ca14c2168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430943227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3430943227
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.177057896
Short name T112
Test name
Test status
Simulation time 445936537 ps
CPU time 0.87 seconds
Started Mar 14 12:38:31 PM PDT 24
Finished Mar 14 12:38:32 PM PDT 24
Peak memory 201868 kb
Host smart-464dea23-6fc9-421d-b386-f0426f6d1913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177057896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.177057896
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2192981977
Short name T783
Test name
Test status
Simulation time 534049997711 ps
CPU time 622.79 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:48:48 PM PDT 24
Peak memory 202212 kb
Host smart-1f5da8f9-20fc-435d-afd2-47b2da4cf236
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192981977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2192981977
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2899359344
Short name T183
Test name
Test status
Simulation time 162586485262 ps
CPU time 106.47 seconds
Started Mar 14 12:38:23 PM PDT 24
Finished Mar 14 12:40:10 PM PDT 24
Peak memory 201960 kb
Host smart-c4d6d507-7ee2-40b5-b87d-d822d3473b72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899359344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2899359344
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3470149132
Short name T742
Test name
Test status
Simulation time 158831859282 ps
CPU time 97 seconds
Started Mar 14 12:38:24 PM PDT 24
Finished Mar 14 12:40:01 PM PDT 24
Peak memory 202112 kb
Host smart-015e11d7-699d-46fc-82fb-97d3350f3ebe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470149132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3470149132
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4129023918
Short name T248
Test name
Test status
Simulation time 537915639429 ps
CPU time 331.88 seconds
Started Mar 14 12:38:32 PM PDT 24
Finished Mar 14 12:44:04 PM PDT 24
Peak memory 202120 kb
Host smart-b6508bed-8ce6-496c-808c-5a89e31b56f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129023918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4129023918
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1497448750
Short name T711
Test name
Test status
Simulation time 411319185455 ps
CPU time 202.77 seconds
Started Mar 14 12:38:31 PM PDT 24
Finished Mar 14 12:41:54 PM PDT 24
Peak memory 202124 kb
Host smart-bd683546-8946-4041-82b1-496317a8b6e6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497448750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1497448750
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3928455314
Short name T607
Test name
Test status
Simulation time 104013081041 ps
CPU time 446.54 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:45:52 PM PDT 24
Peak memory 202488 kb
Host smart-e64effcf-d41e-4af4-bf24-b95ac7ac7c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928455314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3928455314
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1442488595
Short name T467
Test name
Test status
Simulation time 37883203515 ps
CPU time 21.53 seconds
Started Mar 14 12:38:32 PM PDT 24
Finished Mar 14 12:38:53 PM PDT 24
Peak memory 201912 kb
Host smart-a7b2302b-9b1e-4ce1-9de5-d51492f30042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442488595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1442488595
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2969311365
Short name T487
Test name
Test status
Simulation time 4051149580 ps
CPU time 9.59 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:38:34 PM PDT 24
Peak memory 201988 kb
Host smart-c4b993f9-f8bd-4a8e-901a-5155d00196ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969311365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2969311365
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3599802089
Short name T361
Test name
Test status
Simulation time 6064129390 ps
CPU time 4.71 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 201948 kb
Host smart-326e8498-c980-4027-b181-da753ec025bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599802089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3599802089
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3538021733
Short name T37
Test name
Test status
Simulation time 488125197219 ps
CPU time 1544.59 seconds
Started Mar 14 12:38:26 PM PDT 24
Finished Mar 14 01:04:11 PM PDT 24
Peak memory 210652 kb
Host smart-08b98315-c653-4334-a95d-215e5b8273dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538021733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3538021733
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.4012753680
Short name T18
Test name
Test status
Simulation time 112303854939 ps
CPU time 90.87 seconds
Started Mar 14 12:38:25 PM PDT 24
Finished Mar 14 12:39:56 PM PDT 24
Peak memory 211024 kb
Host smart-6e8e1226-84fb-479a-8dc0-85ef75e6b854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012753680 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.4012753680
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1258998795
Short name T547
Test name
Test status
Simulation time 352892004 ps
CPU time 0.81 seconds
Started Mar 14 12:38:44 PM PDT 24
Finished Mar 14 12:38:45 PM PDT 24
Peak memory 201916 kb
Host smart-60ceed03-de8a-464f-ba0e-662eb5e2bb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258998795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1258998795
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3208501430
Short name T229
Test name
Test status
Simulation time 320053670086 ps
CPU time 677.68 seconds
Started Mar 14 12:38:33 PM PDT 24
Finished Mar 14 12:49:50 PM PDT 24
Peak memory 202156 kb
Host smart-b62af6ba-7719-4a46-8bcc-39b5761f1eee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208501430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3208501430
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.359485239
Short name T322
Test name
Test status
Simulation time 520820735393 ps
CPU time 807.28 seconds
Started Mar 14 12:38:34 PM PDT 24
Finished Mar 14 12:52:02 PM PDT 24
Peak memory 202012 kb
Host smart-ff19b998-d9c6-4d4d-a154-42aa0e5e29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359485239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.359485239
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3267141721
Short name T436
Test name
Test status
Simulation time 169167214521 ps
CPU time 45.42 seconds
Started Mar 14 12:38:34 PM PDT 24
Finished Mar 14 12:39:20 PM PDT 24
Peak memory 202068 kb
Host smart-575f77d5-5425-41f2-93c8-c7ea970967c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267141721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3267141721
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3145074164
Short name T363
Test name
Test status
Simulation time 160124696759 ps
CPU time 161.25 seconds
Started Mar 14 12:38:35 PM PDT 24
Finished Mar 14 12:41:17 PM PDT 24
Peak memory 202196 kb
Host smart-ca1a9653-9102-494d-937b-481326740b38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145074164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3145074164
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4225998174
Short name T469
Test name
Test status
Simulation time 158515502923 ps
CPU time 198.3 seconds
Started Mar 14 12:38:26 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 202088 kb
Host smart-57ae3805-0921-4152-b760-6ca6b4a86970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225998174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4225998174
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.726818222
Short name T707
Test name
Test status
Simulation time 339335525640 ps
CPU time 839.52 seconds
Started Mar 14 12:38:29 PM PDT 24
Finished Mar 14 12:52:29 PM PDT 24
Peak memory 202080 kb
Host smart-2d5fe842-e0d7-4a1b-9de8-23ed28c3338b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726818222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.726818222
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2570570943
Short name T101
Test name
Test status
Simulation time 176389783729 ps
CPU time 294 seconds
Started Mar 14 12:38:34 PM PDT 24
Finished Mar 14 12:43:29 PM PDT 24
Peak memory 202176 kb
Host smart-6f03fde9-4320-4aa3-93fc-7edd1315fb89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570570943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2570570943
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3738786680
Short name T494
Test name
Test status
Simulation time 410399572916 ps
CPU time 340.68 seconds
Started Mar 14 12:38:33 PM PDT 24
Finished Mar 14 12:44:16 PM PDT 24
Peak memory 202144 kb
Host smart-883a40c3-9f02-4f9a-b937-5ed45d293c53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738786680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3738786680
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.841221345
Short name T219
Test name
Test status
Simulation time 108403447393 ps
CPU time 431.42 seconds
Started Mar 14 12:38:34 PM PDT 24
Finished Mar 14 12:45:46 PM PDT 24
Peak memory 202436 kb
Host smart-41354afc-e8cd-403b-afee-19320dbd19be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841221345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.841221345
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.876696611
Short name T523
Test name
Test status
Simulation time 42734782192 ps
CPU time 51.06 seconds
Started Mar 14 12:38:33 PM PDT 24
Finished Mar 14 12:39:24 PM PDT 24
Peak memory 201900 kb
Host smart-0133cfde-9108-4795-ad2a-51437b9d8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876696611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.876696611
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.236035288
Short name T375
Test name
Test status
Simulation time 4216584845 ps
CPU time 1.27 seconds
Started Mar 14 12:38:34 PM PDT 24
Finished Mar 14 12:38:36 PM PDT 24
Peak memory 201944 kb
Host smart-850e8e25-4035-4ff8-8e56-7d3443952eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236035288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.236035288
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1616472902
Short name T551
Test name
Test status
Simulation time 5809364670 ps
CPU time 14.91 seconds
Started Mar 14 12:38:24 PM PDT 24
Finished Mar 14 12:38:39 PM PDT 24
Peak memory 201888 kb
Host smart-6ccbb677-3768-4983-84ad-2f076f967cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616472902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1616472902
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1025506201
Short name T35
Test name
Test status
Simulation time 190316491976 ps
CPU time 220.81 seconds
Started Mar 14 12:38:44 PM PDT 24
Finished Mar 14 12:42:25 PM PDT 24
Peak memory 202136 kb
Host smart-f49e8c72-5ce9-433c-b267-29721ab14487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025506201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1025506201
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2327444406
Short name T202
Test name
Test status
Simulation time 266372931136 ps
CPU time 145.96 seconds
Started Mar 14 12:38:46 PM PDT 24
Finished Mar 14 12:41:12 PM PDT 24
Peak memory 210344 kb
Host smart-671a60b1-0a08-4cbd-820c-d9d58a32d08d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327444406 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2327444406
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3982492395
Short name T777
Test name
Test status
Simulation time 317814805 ps
CPU time 1.27 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:38:45 PM PDT 24
Peak memory 201900 kb
Host smart-313be163-62f4-4485-88f5-b8d25829ced5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982492395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3982492395
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1133326962
Short name T328
Test name
Test status
Simulation time 349755898204 ps
CPU time 460.91 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:46:24 PM PDT 24
Peak memory 202036 kb
Host smart-1d43985e-74fb-4077-836a-e959b357a3b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133326962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1133326962
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1918967633
Short name T694
Test name
Test status
Simulation time 178236589399 ps
CPU time 110.17 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:40:33 PM PDT 24
Peak memory 202064 kb
Host smart-deec7326-8bf7-4a7f-8076-02b39f8bcf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918967633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1918967633
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.270658936
Short name T584
Test name
Test status
Simulation time 323295356831 ps
CPU time 745.07 seconds
Started Mar 14 12:38:44 PM PDT 24
Finished Mar 14 12:51:10 PM PDT 24
Peak memory 202080 kb
Host smart-0146b468-ac36-400c-b580-b6647b82c7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270658936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.270658936
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.4014235585
Short name T536
Test name
Test status
Simulation time 162598228172 ps
CPU time 105.23 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:40:28 PM PDT 24
Peak memory 202112 kb
Host smart-63981975-f8d6-4514-abfc-7dc472a7740b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014235585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.4014235585
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3027905242
Short name T175
Test name
Test status
Simulation time 490052183691 ps
CPU time 282.01 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:43:25 PM PDT 24
Peak memory 202096 kb
Host smart-103c29d8-899f-4dea-84dc-be9aa8a143e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027905242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3027905242
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.848579011
Short name T593
Test name
Test status
Simulation time 161198217379 ps
CPU time 380.46 seconds
Started Mar 14 12:38:44 PM PDT 24
Finished Mar 14 12:45:04 PM PDT 24
Peak memory 202132 kb
Host smart-378f9519-35c7-4a16-9c9a-e188b7a83f9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=848579011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.848579011
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2089221603
Short name T168
Test name
Test status
Simulation time 619815035496 ps
CPU time 149.47 seconds
Started Mar 14 12:38:47 PM PDT 24
Finished Mar 14 12:41:16 PM PDT 24
Peak memory 202176 kb
Host smart-8685788a-db16-478d-81a8-c252f79e8777
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089221603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2089221603
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4249635318
Short name T434
Test name
Test status
Simulation time 195611594243 ps
CPU time 457.97 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:46:24 PM PDT 24
Peak memory 202032 kb
Host smart-85213808-4333-49c2-b4ce-42b8e09f7d2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249635318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4249635318
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1011674280
Short name T431
Test name
Test status
Simulation time 99294979668 ps
CPU time 566.05 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:48:11 PM PDT 24
Peak memory 202432 kb
Host smart-d15c8af6-af48-48cf-8b9b-ff61ff5dd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011674280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1011674280
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3790113308
Short name T648
Test name
Test status
Simulation time 41578890521 ps
CPU time 10.08 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:38:55 PM PDT 24
Peak memory 201848 kb
Host smart-44610a6f-0bfd-4d4d-8b23-febee1cc5c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790113308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3790113308
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4120358302
Short name T356
Test name
Test status
Simulation time 4596995870 ps
CPU time 11.81 seconds
Started Mar 14 12:38:44 PM PDT 24
Finished Mar 14 12:38:56 PM PDT 24
Peak memory 201936 kb
Host smart-793479c7-0fab-4350-b127-83e302808b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120358302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4120358302
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4034978129
Short name T762
Test name
Test status
Simulation time 5726228531 ps
CPU time 15.71 seconds
Started Mar 14 12:38:47 PM PDT 24
Finished Mar 14 12:39:02 PM PDT 24
Peak memory 202040 kb
Host smart-902ba1a0-8229-4e99-a999-8322897a3648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034978129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4034978129
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4216403225
Short name T246
Test name
Test status
Simulation time 39524810964 ps
CPU time 49.49 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:39:34 PM PDT 24
Peak memory 210444 kb
Host smart-dd990d6e-e945-4d4f-aeec-a0e8131956c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216403225 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4216403225
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3721048904
Short name T759
Test name
Test status
Simulation time 285906730 ps
CPU time 1.32 seconds
Started Mar 14 12:38:52 PM PDT 24
Finished Mar 14 12:38:54 PM PDT 24
Peak memory 201832 kb
Host smart-d92854fd-1461-43cd-be33-10032dca2e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721048904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3721048904
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3498332781
Short name T49
Test name
Test status
Simulation time 175792958238 ps
CPU time 201.55 seconds
Started Mar 14 12:38:58 PM PDT 24
Finished Mar 14 12:42:20 PM PDT 24
Peak memory 202040 kb
Host smart-135385c6-9c0c-43d9-b712-6a3d9ac30216
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498332781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3498332781
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2259501233
Short name T234
Test name
Test status
Simulation time 167050568019 ps
CPU time 124.3 seconds
Started Mar 14 12:38:57 PM PDT 24
Finished Mar 14 12:41:01 PM PDT 24
Peak memory 202200 kb
Host smart-e51ed649-3c47-4d2f-ba02-558681ed0277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259501233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2259501233
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3422315315
Short name T225
Test name
Test status
Simulation time 492638175163 ps
CPU time 297.26 seconds
Started Mar 14 12:39:01 PM PDT 24
Finished Mar 14 12:43:58 PM PDT 24
Peak memory 202032 kb
Host smart-203c52d5-2fe4-4fa0-80fb-f8f7c3325162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422315315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3422315315
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3115895703
Short name T660
Test name
Test status
Simulation time 165359056221 ps
CPU time 405.89 seconds
Started Mar 14 12:38:55 PM PDT 24
Finished Mar 14 12:45:41 PM PDT 24
Peak memory 202124 kb
Host smart-8d68c249-4c1b-497b-85bc-48e6c46bd1c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115895703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3115895703
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4220462551
Short name T692
Test name
Test status
Simulation time 336454300960 ps
CPU time 807.77 seconds
Started Mar 14 12:38:45 PM PDT 24
Finished Mar 14 12:52:13 PM PDT 24
Peak memory 202088 kb
Host smart-5b6d7089-27f1-4cf5-ba9b-24cb70480a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220462551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4220462551
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1861915472
Short name T478
Test name
Test status
Simulation time 166516306632 ps
CPU time 406.37 seconds
Started Mar 14 12:39:02 PM PDT 24
Finished Mar 14 12:45:49 PM PDT 24
Peak memory 202136 kb
Host smart-001e4543-7bf5-42b6-a2df-8a553265d704
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861915472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1861915472
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3757141392
Short name T281
Test name
Test status
Simulation time 178430867271 ps
CPU time 407.65 seconds
Started Mar 14 12:38:57 PM PDT 24
Finished Mar 14 12:45:45 PM PDT 24
Peak memory 201964 kb
Host smart-86b929dc-e416-4ad6-8d3b-26835728fde0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757141392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3757141392
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2674326372
Short name T402
Test name
Test status
Simulation time 392354094857 ps
CPU time 485.06 seconds
Started Mar 14 12:38:56 PM PDT 24
Finished Mar 14 12:47:01 PM PDT 24
Peak memory 202128 kb
Host smart-39c86b2a-1dab-4d9b-864b-edc8afdb97f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674326372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2674326372
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.221083780
Short name T94
Test name
Test status
Simulation time 99460718070 ps
CPU time 330.5 seconds
Started Mar 14 12:38:58 PM PDT 24
Finished Mar 14 12:44:28 PM PDT 24
Peak memory 202352 kb
Host smart-b103f61a-89cd-4ddd-b32a-41259fdb30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221083780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.221083780
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1393267680
Short name T768
Test name
Test status
Simulation time 31716095147 ps
CPU time 39.49 seconds
Started Mar 14 12:38:55 PM PDT 24
Finished Mar 14 12:39:35 PM PDT 24
Peak memory 201952 kb
Host smart-8f288b4f-b31d-4079-ac7e-be5ba057617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393267680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1393267680
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3819124991
Short name T654
Test name
Test status
Simulation time 4426059210 ps
CPU time 10.91 seconds
Started Mar 14 12:38:56 PM PDT 24
Finished Mar 14 12:39:07 PM PDT 24
Peak memory 201952 kb
Host smart-67f16ad7-5b66-43b7-b6ab-33e0413c2840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819124991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3819124991
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2339953552
Short name T390
Test name
Test status
Simulation time 5868600342 ps
CPU time 4.23 seconds
Started Mar 14 12:38:43 PM PDT 24
Finished Mar 14 12:38:48 PM PDT 24
Peak memory 201916 kb
Host smart-f64376c5-7b1d-45a6-9cf9-7669a369d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339953552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2339953552
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1388941773
Short name T36
Test name
Test status
Simulation time 169207731562 ps
CPU time 366.81 seconds
Started Mar 14 12:38:55 PM PDT 24
Finished Mar 14 12:45:02 PM PDT 24
Peak memory 202092 kb
Host smart-9aee3add-7c62-43e0-bd36-70d7cbc09798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388941773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1388941773
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1285288545
Short name T20
Test name
Test status
Simulation time 10706960544 ps
CPU time 27.53 seconds
Started Mar 14 12:38:55 PM PDT 24
Finished Mar 14 12:39:22 PM PDT 24
Peak memory 210572 kb
Host smart-d648f4ce-0e17-4a3d-a0c0-14ba654291d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285288545 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1285288545
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3560108949
Short name T108
Test name
Test status
Simulation time 536760595 ps
CPU time 0.93 seconds
Started Mar 14 12:39:04 PM PDT 24
Finished Mar 14 12:39:06 PM PDT 24
Peak memory 201836 kb
Host smart-9e952f1c-fff2-4460-930b-1f3684e3a7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560108949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3560108949
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3764214588
Short name T316
Test name
Test status
Simulation time 502236146631 ps
CPU time 926.18 seconds
Started Mar 14 12:38:53 PM PDT 24
Finished Mar 14 12:54:20 PM PDT 24
Peak memory 202016 kb
Host smart-cba9aa37-4e0a-4a9d-96b7-caab5b0421f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764214588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3764214588
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3150793816
Short name T275
Test name
Test status
Simulation time 173383287668 ps
CPU time 397.31 seconds
Started Mar 14 12:39:08 PM PDT 24
Finished Mar 14 12:45:46 PM PDT 24
Peak memory 202052 kb
Host smart-a55302ec-7a09-4b82-b57b-e977657da377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150793816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3150793816
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2175108660
Short name T235
Test name
Test status
Simulation time 498651190638 ps
CPU time 1124.35 seconds
Started Mar 14 12:39:02 PM PDT 24
Finished Mar 14 12:57:47 PM PDT 24
Peak memory 202188 kb
Host smart-7305668d-b4a9-4e4d-b4f9-a5c7bae3e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175108660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2175108660
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.434466972
Short name T538
Test name
Test status
Simulation time 166654438864 ps
CPU time 404.12 seconds
Started Mar 14 12:38:56 PM PDT 24
Finished Mar 14 12:45:41 PM PDT 24
Peak memory 202120 kb
Host smart-d632e253-cb17-4ff0-a53a-9cf098eff735
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=434466972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.434466972
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2029251910
Short name T6
Test name
Test status
Simulation time 494964637939 ps
CPU time 296.57 seconds
Started Mar 14 12:39:02 PM PDT 24
Finished Mar 14 12:44:00 PM PDT 24
Peak memory 202108 kb
Host smart-02789e3e-f677-4b8d-994c-1d0b19476545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029251910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2029251910
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3729367429
Short name T496
Test name
Test status
Simulation time 163350691911 ps
CPU time 388.96 seconds
Started Mar 14 12:38:55 PM PDT 24
Finished Mar 14 12:45:24 PM PDT 24
Peak memory 202136 kb
Host smart-f7f2be90-4e7b-44c3-b826-f94c24851772
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729367429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3729367429
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2667201667
Short name T595
Test name
Test status
Simulation time 172831833300 ps
CPU time 218.49 seconds
Started Mar 14 12:38:54 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 202112 kb
Host smart-57ad4a19-ba50-40dc-a6f8-f5f97be52183
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667201667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2667201667
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.390831290
Short name T31
Test name
Test status
Simulation time 388331563991 ps
CPU time 937.56 seconds
Started Mar 14 12:38:54 PM PDT 24
Finished Mar 14 12:54:32 PM PDT 24
Peak memory 202124 kb
Host smart-b08811c2-5d11-48d0-bfdc-0ce9ebf91d0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390831290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.390831290
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3422579366
Short name T222
Test name
Test status
Simulation time 93802946496 ps
CPU time 283.89 seconds
Started Mar 14 12:39:04 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 202408 kb
Host smart-772b5f64-ef57-4392-97f3-7060c5c1ed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422579366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3422579366
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.705368446
Short name T502
Test name
Test status
Simulation time 44318882033 ps
CPU time 24.66 seconds
Started Mar 14 12:39:08 PM PDT 24
Finished Mar 14 12:39:34 PM PDT 24
Peak memory 201956 kb
Host smart-9608fb0d-d795-492b-be71-b414ca726387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705368446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.705368446
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1761729830
Short name T382
Test name
Test status
Simulation time 4409669388 ps
CPU time 6.59 seconds
Started Mar 14 12:39:05 PM PDT 24
Finished Mar 14 12:39:12 PM PDT 24
Peak memory 201872 kb
Host smart-dc575897-17c1-4c8a-8673-0e6b1ffaa498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761729830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1761729830
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3520546361
Short name T430
Test name
Test status
Simulation time 6010680151 ps
CPU time 7.68 seconds
Started Mar 14 12:38:58 PM PDT 24
Finished Mar 14 12:39:06 PM PDT 24
Peak memory 201788 kb
Host smart-8227c7e8-626c-439a-8bfb-9ce1a1e02a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520546361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3520546361
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3394122255
Short name T342
Test name
Test status
Simulation time 720929497968 ps
CPU time 241.52 seconds
Started Mar 14 12:39:05 PM PDT 24
Finished Mar 14 12:43:07 PM PDT 24
Peak memory 202192 kb
Host smart-f113e6c9-7c41-463e-b8a2-a3bdec54bc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394122255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3394122255
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.891624332
Short name T16
Test name
Test status
Simulation time 258576195680 ps
CPU time 306.04 seconds
Started Mar 14 12:39:06 PM PDT 24
Finished Mar 14 12:44:13 PM PDT 24
Peak memory 218284 kb
Host smart-563b33b2-fb24-45a8-bc81-09235ffd49dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891624332 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.891624332
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2430729693
Short name T563
Test name
Test status
Simulation time 455133088 ps
CPU time 1.11 seconds
Started Mar 14 12:39:13 PM PDT 24
Finished Mar 14 12:39:14 PM PDT 24
Peak memory 201868 kb
Host smart-cc645657-93fc-4478-a81e-13892cb31cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430729693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2430729693
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1167484944
Short name T163
Test name
Test status
Simulation time 532573506120 ps
CPU time 512.85 seconds
Started Mar 14 12:39:04 PM PDT 24
Finished Mar 14 12:47:37 PM PDT 24
Peak memory 202076 kb
Host smart-751ff2ee-3e22-4b0e-91fd-c647f3ffb012
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167484944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1167484944
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.487256104
Short name T188
Test name
Test status
Simulation time 482850561092 ps
CPU time 320.41 seconds
Started Mar 14 12:39:07 PM PDT 24
Finished Mar 14 12:44:28 PM PDT 24
Peak memory 202180 kb
Host smart-2bdc7678-1e63-4a21-838a-13a633c69335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487256104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.487256104
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2567005595
Short name T32
Test name
Test status
Simulation time 164461092660 ps
CPU time 203.02 seconds
Started Mar 14 12:39:09 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 202060 kb
Host smart-f6056a47-4aae-4c5e-906a-b8877a9b9167
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567005595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2567005595
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2521757809
Short name T166
Test name
Test status
Simulation time 327681068743 ps
CPU time 147.95 seconds
Started Mar 14 12:39:08 PM PDT 24
Finished Mar 14 12:41:37 PM PDT 24
Peak memory 202064 kb
Host smart-fc88e0c1-6e30-4507-a527-2a3e76272aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521757809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2521757809
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.257151134
Short name T704
Test name
Test status
Simulation time 493837403380 ps
CPU time 695.03 seconds
Started Mar 14 12:39:07 PM PDT 24
Finished Mar 14 12:50:42 PM PDT 24
Peak memory 202112 kb
Host smart-98548922-d5a1-46e3-960b-f8175ec9327d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=257151134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.257151134
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2700064463
Short name T622
Test name
Test status
Simulation time 167504233307 ps
CPU time 38.81 seconds
Started Mar 14 12:39:06 PM PDT 24
Finished Mar 14 12:39:46 PM PDT 24
Peak memory 202152 kb
Host smart-342b5a10-a02d-442a-89d5-1b8477da2d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700064463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2700064463
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1000381088
Short name T714
Test name
Test status
Simulation time 202086925138 ps
CPU time 107.73 seconds
Started Mar 14 12:39:06 PM PDT 24
Finished Mar 14 12:40:55 PM PDT 24
Peak memory 202120 kb
Host smart-0ddc1a1f-d7e5-4289-a0a8-9e95871d8e4c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000381088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1000381088
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.480271678
Short name T186
Test name
Test status
Simulation time 92526308594 ps
CPU time 486.34 seconds
Started Mar 14 12:39:13 PM PDT 24
Finished Mar 14 12:47:20 PM PDT 24
Peak memory 202452 kb
Host smart-bde9fd2f-cc18-45c8-a1e4-302081bb57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480271678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.480271678
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.277438427
Short name T735
Test name
Test status
Simulation time 38572806988 ps
CPU time 89.25 seconds
Started Mar 14 12:39:03 PM PDT 24
Finished Mar 14 12:40:33 PM PDT 24
Peak memory 201952 kb
Host smart-4432d9e7-e708-46c7-bd40-fd41f93c0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277438427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.277438427
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1019507009
Short name T568
Test name
Test status
Simulation time 3764718602 ps
CPU time 2.47 seconds
Started Mar 14 12:39:05 PM PDT 24
Finished Mar 14 12:39:07 PM PDT 24
Peak memory 201892 kb
Host smart-94e6b5ec-990a-4cf4-8364-8f9118b54458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019507009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1019507009
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2116919497
Short name T637
Test name
Test status
Simulation time 6108514901 ps
CPU time 4.37 seconds
Started Mar 14 12:39:05 PM PDT 24
Finished Mar 14 12:39:10 PM PDT 24
Peak memory 201928 kb
Host smart-c278b61a-9f35-4e7a-a9af-8ec290f3e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116919497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2116919497
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1650843213
Short name T338
Test name
Test status
Simulation time 334464468731 ps
CPU time 822.95 seconds
Started Mar 14 12:39:13 PM PDT 24
Finished Mar 14 12:52:56 PM PDT 24
Peak memory 202172 kb
Host smart-408028ef-c3f1-4aaf-8fec-d753d71e8e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650843213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1650843213
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3432930007
Short name T574
Test name
Test status
Simulation time 468041691 ps
CPU time 0.89 seconds
Started Mar 14 12:39:12 PM PDT 24
Finished Mar 14 12:39:13 PM PDT 24
Peak memory 201900 kb
Host smart-1a7137cb-177c-4160-9e73-3ddae876d0f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432930007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3432930007
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2081449420
Short name T756
Test name
Test status
Simulation time 437152294078 ps
CPU time 204.99 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:42:40 PM PDT 24
Peak memory 202136 kb
Host smart-15adfcee-8be7-4e59-9a97-d93e229a569a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081449420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2081449420
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2328518546
Short name T340
Test name
Test status
Simulation time 333653320609 ps
CPU time 198.28 seconds
Started Mar 14 12:39:13 PM PDT 24
Finished Mar 14 12:42:31 PM PDT 24
Peak memory 202160 kb
Host smart-19a38e7e-f995-4e93-96c8-390157ad56c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328518546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2328518546
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2487649179
Short name T392
Test name
Test status
Simulation time 325995136216 ps
CPU time 773.85 seconds
Started Mar 14 12:39:12 PM PDT 24
Finished Mar 14 12:52:06 PM PDT 24
Peak memory 201996 kb
Host smart-df64605d-321e-4e02-8977-b826cdbd049a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487649179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2487649179
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1911254094
Short name T767
Test name
Test status
Simulation time 493658084989 ps
CPU time 298.38 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:44:14 PM PDT 24
Peak memory 202028 kb
Host smart-21a114f1-ab27-48f2-8fa2-e91c5994e380
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911254094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1911254094
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2501634408
Short name T302
Test name
Test status
Simulation time 180517716179 ps
CPU time 222.06 seconds
Started Mar 14 12:39:16 PM PDT 24
Finished Mar 14 12:42:58 PM PDT 24
Peak memory 202128 kb
Host smart-f99e238c-6cc3-412e-a605-162777499cc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501634408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2501634408
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.369905578
Short name T192
Test name
Test status
Simulation time 201492882728 ps
CPU time 120.88 seconds
Started Mar 14 12:39:13 PM PDT 24
Finished Mar 14 12:41:14 PM PDT 24
Peak memory 202112 kb
Host smart-a8b16f65-42ca-4c1f-9862-ea87f8765630
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369905578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.369905578
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.62823112
Short name T203
Test name
Test status
Simulation time 75610944819 ps
CPU time 272.43 seconds
Started Mar 14 12:39:16 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 202484 kb
Host smart-06007604-5a23-4aa0-ace6-83ee139ae5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62823112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.62823112
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.248989921
Short name T633
Test name
Test status
Simulation time 33048910307 ps
CPU time 8.33 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 201760 kb
Host smart-3e89e312-620a-46f9-9773-8071d928485e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248989921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.248989921
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3956950057
Short name T645
Test name
Test status
Simulation time 4494002137 ps
CPU time 3.43 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:39:19 PM PDT 24
Peak memory 201952 kb
Host smart-f812a7ca-6fc4-40d2-872b-bedeb0c25cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956950057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3956950057
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.145227363
Short name T690
Test name
Test status
Simulation time 5705542698 ps
CPU time 11.95 seconds
Started Mar 14 12:39:14 PM PDT 24
Finished Mar 14 12:39:26 PM PDT 24
Peak memory 201896 kb
Host smart-674d7143-bd2c-4658-ad36-5db9bd6045b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145227363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.145227363
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2185406908
Short name T91
Test name
Test status
Simulation time 215486792415 ps
CPU time 127.46 seconds
Started Mar 14 12:39:11 PM PDT 24
Finished Mar 14 12:41:19 PM PDT 24
Peak memory 202060 kb
Host smart-377b80a2-d882-4074-b1e7-40ed8b21128d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185406908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2185406908
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1016511335
Short name T544
Test name
Test status
Simulation time 491487883 ps
CPU time 0.84 seconds
Started Mar 14 12:39:20 PM PDT 24
Finished Mar 14 12:39:22 PM PDT 24
Peak memory 201808 kb
Host smart-fb6b82c4-ec5c-44f6-91fe-46560eeb3578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016511335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1016511335
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3081619849
Short name T176
Test name
Test status
Simulation time 267104044082 ps
CPU time 617.29 seconds
Started Mar 14 12:39:21 PM PDT 24
Finished Mar 14 12:49:39 PM PDT 24
Peak memory 202172 kb
Host smart-8265a958-cd3f-458c-b136-ac395efe7558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081619849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3081619849
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2520324695
Short name T602
Test name
Test status
Simulation time 329507978882 ps
CPU time 844.56 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:53:28 PM PDT 24
Peak memory 201984 kb
Host smart-d8fe960f-b653-4a0c-af10-53aeb2ba68b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520324695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2520324695
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1791114114
Short name T365
Test name
Test status
Simulation time 166696576461 ps
CPU time 106.29 seconds
Started Mar 14 12:39:20 PM PDT 24
Finished Mar 14 12:41:07 PM PDT 24
Peak memory 202104 kb
Host smart-e075711c-fb12-453e-b4d9-1aca42d0234e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791114114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1791114114
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.341693163
Short name T500
Test name
Test status
Simulation time 161925962218 ps
CPU time 337.49 seconds
Started Mar 14 12:39:14 PM PDT 24
Finished Mar 14 12:44:51 PM PDT 24
Peak memory 202224 kb
Host smart-8ebdb121-4e0d-4099-b550-00f75d0a7438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341693163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.341693163
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2732220951
Short name T404
Test name
Test status
Simulation time 161041241766 ps
CPU time 329.33 seconds
Started Mar 14 12:39:15 PM PDT 24
Finished Mar 14 12:44:44 PM PDT 24
Peak memory 202072 kb
Host smart-336e8234-234c-40a9-b761-b3576a797103
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732220951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2732220951
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.627861887
Short name T30
Test name
Test status
Simulation time 386633284322 ps
CPU time 903.27 seconds
Started Mar 14 12:39:22 PM PDT 24
Finished Mar 14 12:54:26 PM PDT 24
Peak memory 202220 kb
Host smart-8665aebd-01ca-4a1a-9088-fd7d3cad6175
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627861887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.627861887
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.945672343
Short name T191
Test name
Test status
Simulation time 215612455598 ps
CPU time 126.52 seconds
Started Mar 14 12:39:20 PM PDT 24
Finished Mar 14 12:41:28 PM PDT 24
Peak memory 202076 kb
Host smart-5e21187b-7043-480c-9fe2-421f87744d19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945672343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.945672343
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.523877829
Short name T393
Test name
Test status
Simulation time 76322039183 ps
CPU time 404.6 seconds
Started Mar 14 12:39:20 PM PDT 24
Finished Mar 14 12:46:06 PM PDT 24
Peak memory 202448 kb
Host smart-e13667ff-43e3-4060-b673-f0a08e14c8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523877829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.523877829
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2526793836
Short name T358
Test name
Test status
Simulation time 45461760379 ps
CPU time 8.65 seconds
Started Mar 14 12:39:21 PM PDT 24
Finished Mar 14 12:39:30 PM PDT 24
Peak memory 201960 kb
Host smart-39979fc9-80d1-46c8-8368-a49abbfd7b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526793836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2526793836
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3711325723
Short name T748
Test name
Test status
Simulation time 3726090795 ps
CPU time 2.03 seconds
Started Mar 14 12:39:23 PM PDT 24
Finished Mar 14 12:39:25 PM PDT 24
Peak memory 201896 kb
Host smart-f6a8ee80-d2fd-4018-b32e-fc274fea114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711325723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3711325723
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2954731736
Short name T754
Test name
Test status
Simulation time 5971069459 ps
CPU time 7.42 seconds
Started Mar 14 12:39:12 PM PDT 24
Finished Mar 14 12:39:20 PM PDT 24
Peak memory 201932 kb
Host smart-631419c3-f148-4dd1-a9bb-38c0e5b3a2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954731736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2954731736
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1460110817
Short name T573
Test name
Test status
Simulation time 459987080780 ps
CPU time 887.1 seconds
Started Mar 14 12:39:19 PM PDT 24
Finished Mar 14 12:54:08 PM PDT 24
Peak memory 210692 kb
Host smart-6bd96d54-e871-4f89-bcb5-7ce1db478a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460110817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1460110817
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.441740676
Short name T102
Test name
Test status
Simulation time 534457050 ps
CPU time 0.92 seconds
Started Mar 14 12:34:27 PM PDT 24
Finished Mar 14 12:34:28 PM PDT 24
Peak memory 201848 kb
Host smart-8a201b2d-1aff-429f-b3d9-3df361439453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441740676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.441740676
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1139461846
Short name T197
Test name
Test status
Simulation time 527482797038 ps
CPU time 267.7 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:38:42 PM PDT 24
Peak memory 202052 kb
Host smart-c70d274e-679e-4759-8176-6f364cd9ff9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139461846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1139461846
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1089614241
Short name T785
Test name
Test status
Simulation time 170141571726 ps
CPU time 103.96 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:36:09 PM PDT 24
Peak memory 202200 kb
Host smart-eaa1ed25-64e9-4587-937a-86a065af2efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089614241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1089614241
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2373184606
Short name T341
Test name
Test status
Simulation time 323611330530 ps
CPU time 386.75 seconds
Started Mar 14 12:34:31 PM PDT 24
Finished Mar 14 12:40:58 PM PDT 24
Peak memory 202056 kb
Host smart-e39454fc-5076-4cef-914a-60fa828c1dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373184606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2373184606
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1329462338
Short name T510
Test name
Test status
Simulation time 160024761032 ps
CPU time 389.35 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:40:55 PM PDT 24
Peak memory 202276 kb
Host smart-2b505899-3384-4695-b211-daabcc79aedd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329462338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1329462338
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1410797675
Short name T33
Test name
Test status
Simulation time 320248933469 ps
CPU time 700.8 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:45:50 PM PDT 24
Peak memory 202080 kb
Host smart-69a296c7-a249-4b82-8824-91d500ef993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410797675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1410797675
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.335579337
Short name T740
Test name
Test status
Simulation time 164852294527 ps
CPU time 197.44 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:37:18 PM PDT 24
Peak memory 202080 kb
Host smart-a7d12d80-c9d5-4d73-818c-b2bc6635d394
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=335579337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.335579337
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3160038667
Short name T347
Test name
Test status
Simulation time 588557447686 ps
CPU time 185.91 seconds
Started Mar 14 12:34:24 PM PDT 24
Finished Mar 14 12:37:30 PM PDT 24
Peak memory 202116 kb
Host smart-b9a196bc-3d06-4ddd-b07d-dee877408a6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160038667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3160038667
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2632127675
Short name T549
Test name
Test status
Simulation time 397279175345 ps
CPU time 958.61 seconds
Started Mar 14 12:34:33 PM PDT 24
Finished Mar 14 12:50:31 PM PDT 24
Peak memory 202160 kb
Host smart-22831c70-45b2-43b2-b930-bc7e75c37060
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632127675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2632127675
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4117389006
Short name T657
Test name
Test status
Simulation time 75064827689 ps
CPU time 320.64 seconds
Started Mar 14 12:34:24 PM PDT 24
Finished Mar 14 12:39:45 PM PDT 24
Peak memory 202480 kb
Host smart-0a381fe0-76c9-44eb-b3e1-c35a77f80122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117389006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4117389006
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3036057452
Short name T3
Test name
Test status
Simulation time 27030108112 ps
CPU time 16.5 seconds
Started Mar 14 12:34:33 PM PDT 24
Finished Mar 14 12:34:50 PM PDT 24
Peak memory 201932 kb
Host smart-c0b828b2-f1a9-4e0b-bd23-43905bc0ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036057452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3036057452
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4207070122
Short name T725
Test name
Test status
Simulation time 4959065244 ps
CPU time 11.35 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:26 PM PDT 24
Peak memory 201864 kb
Host smart-77019454-311a-4102-a74e-a5a953b048a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207070122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4207070122
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3944198433
Short name T567
Test name
Test status
Simulation time 5605462942 ps
CPU time 3.68 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:34:06 PM PDT 24
Peak memory 201952 kb
Host smart-668df7bf-bcef-4cca-af6b-beb42ef31b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944198433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3944198433
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.841552607
Short name T187
Test name
Test status
Simulation time 432141099386 ps
CPU time 634.8 seconds
Started Mar 14 12:34:28 PM PDT 24
Finished Mar 14 12:45:03 PM PDT 24
Peak memory 210572 kb
Host smart-a43b2fbc-4315-425a-af3e-c3914069a698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841552607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.841552607
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1607820394
Short name T346
Test name
Test status
Simulation time 212935130615 ps
CPU time 160.59 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:37:06 PM PDT 24
Peak memory 210788 kb
Host smart-7929376d-a0cf-4550-82c2-93a0e92583d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607820394 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1607820394
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.609323010
Short name T571
Test name
Test status
Simulation time 467050141 ps
CPU time 1.32 seconds
Started Mar 14 12:34:28 PM PDT 24
Finished Mar 14 12:34:30 PM PDT 24
Peak memory 201832 kb
Host smart-b830628f-06eb-481f-97eb-13c1ea57aae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609323010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.609323010
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4114099696
Short name T280
Test name
Test status
Simulation time 350409857700 ps
CPU time 790.46 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:47:37 PM PDT 24
Peak memory 202112 kb
Host smart-582be763-c254-498c-bc34-10a033e7be47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114099696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4114099696
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.564575406
Short name T774
Test name
Test status
Simulation time 375749552237 ps
CPU time 437.79 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:41:43 PM PDT 24
Peak memory 202052 kb
Host smart-f191ea1c-40bb-4ed1-8c97-b58d6b20c891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564575406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.564575406
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1416471751
Short name T93
Test name
Test status
Simulation time 335101582147 ps
CPU time 196.02 seconds
Started Mar 14 12:34:16 PM PDT 24
Finished Mar 14 12:37:32 PM PDT 24
Peak memory 201972 kb
Host smart-7a58e1b8-4abe-443c-ae53-508b32bdeee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416471751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1416471751
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2365329046
Short name T25
Test name
Test status
Simulation time 338331383866 ps
CPU time 743.94 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:46:53 PM PDT 24
Peak memory 202080 kb
Host smart-8fefe6d2-5ef2-4c5b-9796-f49c84c3a04f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365329046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2365329046
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1691827435
Short name T240
Test name
Test status
Simulation time 157787987984 ps
CPU time 107.24 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:36:14 PM PDT 24
Peak memory 202112 kb
Host smart-471b1dd7-bdcc-4e2b-ae3c-eb284984a2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691827435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1691827435
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3532450454
Short name T630
Test name
Test status
Simulation time 328200887029 ps
CPU time 211.19 seconds
Started Mar 14 12:34:16 PM PDT 24
Finished Mar 14 12:37:47 PM PDT 24
Peak memory 202028 kb
Host smart-d4f845fd-7a65-4581-8743-9ac1a42b5d10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532450454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3532450454
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1298157289
Short name T628
Test name
Test status
Simulation time 170257370243 ps
CPU time 96.97 seconds
Started Mar 14 12:34:35 PM PDT 24
Finished Mar 14 12:36:12 PM PDT 24
Peak memory 202144 kb
Host smart-94b50b69-57b4-472f-8f45-02c447ce8a22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298157289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1298157289
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2478857843
Short name T472
Test name
Test status
Simulation time 588717199396 ps
CPU time 1349.47 seconds
Started Mar 14 12:34:33 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 202040 kb
Host smart-6f6a29de-556f-4c96-84bc-745f91731570
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478857843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2478857843
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.917564205
Short name T351
Test name
Test status
Simulation time 116235064254 ps
CPU time 442.61 seconds
Started Mar 14 12:34:33 PM PDT 24
Finished Mar 14 12:41:55 PM PDT 24
Peak memory 202500 kb
Host smart-b8083fb0-7c47-4475-a5e8-be110d5bac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917564205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.917564205
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1236770904
Short name T484
Test name
Test status
Simulation time 41812783163 ps
CPU time 24.16 seconds
Started Mar 14 12:34:24 PM PDT 24
Finished Mar 14 12:34:48 PM PDT 24
Peak memory 201880 kb
Host smart-3c71f432-7e5a-437e-a02f-56affabc204d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236770904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1236770904
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4029057918
Short name T675
Test name
Test status
Simulation time 4290581225 ps
CPU time 11.39 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 201964 kb
Host smart-479a90e0-7c50-4f49-a160-38352b58ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029057918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4029057918
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4148741705
Short name T599
Test name
Test status
Simulation time 5876577258 ps
CPU time 13.81 seconds
Started Mar 14 12:34:23 PM PDT 24
Finished Mar 14 12:34:37 PM PDT 24
Peak memory 201980 kb
Host smart-fe3203be-808c-4550-882a-806bbb3854cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148741705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4148741705
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3512612642
Short name T237
Test name
Test status
Simulation time 185628513428 ps
CPU time 421.8 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:41:31 PM PDT 24
Peak memory 202112 kb
Host smart-a819eba1-a8b9-4a47-94b3-08fb47e829c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512612642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3512612642
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.4096703149
Short name T67
Test name
Test status
Simulation time 42660483591 ps
CPU time 115.88 seconds
Started Mar 14 12:34:22 PM PDT 24
Finished Mar 14 12:36:18 PM PDT 24
Peak memory 211756 kb
Host smart-a975e51b-3c18-40cb-9260-48ee878912ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096703149 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.4096703149
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.592744099
Short name T743
Test name
Test status
Simulation time 442590974 ps
CPU time 1.73 seconds
Started Mar 14 12:34:23 PM PDT 24
Finished Mar 14 12:34:25 PM PDT 24
Peak memory 201808 kb
Host smart-3c21f68d-568e-4e13-9486-b74f58e3d7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592744099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.592744099
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1994096647
Short name T635
Test name
Test status
Simulation time 321960823037 ps
CPU time 413.62 seconds
Started Mar 14 12:34:32 PM PDT 24
Finished Mar 14 12:41:26 PM PDT 24
Peak memory 202084 kb
Host smart-58453760-4503-4d68-8979-d9e3c59d091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994096647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1994096647
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2387748289
Short name T796
Test name
Test status
Simulation time 494902722212 ps
CPU time 297.75 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:39:23 PM PDT 24
Peak memory 202124 kb
Host smart-37ebe7a0-30fc-4ff4-921f-62b941a0a1a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387748289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2387748289
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3089530955
Short name T483
Test name
Test status
Simulation time 165641983652 ps
CPU time 98.14 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:36:03 PM PDT 24
Peak memory 202028 kb
Host smart-03b526e7-ef64-4806-b2fc-8fb054202e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089530955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3089530955
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3776288228
Short name T51
Test name
Test status
Simulation time 172598255842 ps
CPU time 107.95 seconds
Started Mar 14 12:34:20 PM PDT 24
Finished Mar 14 12:36:09 PM PDT 24
Peak memory 202060 kb
Host smart-79053d2a-390c-44e8-9ef1-b7c1334d95a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776288228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3776288228
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1288469126
Short name T201
Test name
Test status
Simulation time 571592961723 ps
CPU time 335.72 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:40:02 PM PDT 24
Peak memory 202256 kb
Host smart-8ea4ef5c-d17b-40e4-9346-e3324a2a87bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288469126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1288469126
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3540211466
Short name T470
Test name
Test status
Simulation time 395030753748 ps
CPU time 870.29 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:49:05 PM PDT 24
Peak memory 202100 kb
Host smart-9d3d89ad-bf04-4e85-9c8f-4950f3738759
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540211466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3540211466
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.122716342
Short name T591
Test name
Test status
Simulation time 74988159803 ps
CPU time 391.65 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 202460 kb
Host smart-2de36d78-bd72-4f3c-bc89-e524ed04c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122716342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.122716342
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4234679885
Short name T450
Test name
Test status
Simulation time 29981159922 ps
CPU time 4.97 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:34:41 PM PDT 24
Peak memory 201940 kb
Host smart-cd98c3ff-19bc-4008-be06-1180356d408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234679885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4234679885
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.33249403
Short name T717
Test name
Test status
Simulation time 4518059316 ps
CPU time 10.94 seconds
Started Mar 14 12:34:21 PM PDT 24
Finished Mar 14 12:34:32 PM PDT 24
Peak memory 201876 kb
Host smart-1065ea8c-1808-4cbd-8027-5d275c0aeda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33249403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.33249403
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1821840046
Short name T475
Test name
Test status
Simulation time 5951353994 ps
CPU time 3.8 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:18 PM PDT 24
Peak memory 201916 kb
Host smart-f6e7dd04-b5cd-4355-becb-335edf4866df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821840046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1821840046
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1809155060
Short name T333
Test name
Test status
Simulation time 135667978282 ps
CPU time 109.5 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:36:26 PM PDT 24
Peak memory 210484 kb
Host smart-f5172a0b-53ae-4b23-a04a-623b838a9c4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809155060 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1809155060
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2906510955
Short name T419
Test name
Test status
Simulation time 538038153 ps
CPU time 0.79 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:34:35 PM PDT 24
Peak memory 201828 kb
Host smart-1a8a0cf3-dae8-45b4-bc43-9fc342aa1d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906510955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2906510955
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3312468210
Short name T669
Test name
Test status
Simulation time 158483357351 ps
CPU time 95.02 seconds
Started Mar 14 12:34:33 PM PDT 24
Finished Mar 14 12:36:08 PM PDT 24
Peak memory 202156 kb
Host smart-86438b67-4c26-4589-902b-e0ccc3bff6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312468210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3312468210
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.859538540
Short name T521
Test name
Test status
Simulation time 327568883983 ps
CPU time 754.58 seconds
Started Mar 14 12:34:30 PM PDT 24
Finished Mar 14 12:47:05 PM PDT 24
Peak memory 202076 kb
Host smart-4a7da05c-5bfe-4046-aa26-16dd32c0d71c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=859538540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.859538540
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2677796542
Short name T651
Test name
Test status
Simulation time 501227171756 ps
CPU time 116.66 seconds
Started Mar 14 12:34:37 PM PDT 24
Finished Mar 14 12:36:34 PM PDT 24
Peak memory 202072 kb
Host smart-5692e5fb-c64b-4d00-b808-889e54d2e010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677796542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2677796542
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.291487397
Short name T355
Test name
Test status
Simulation time 481580565794 ps
CPU time 629.85 seconds
Started Mar 14 12:34:32 PM PDT 24
Finished Mar 14 12:45:02 PM PDT 24
Peak memory 202120 kb
Host smart-21eb0784-1504-4bc1-b3fe-783a86de3fb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=291487397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.291487397
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2086116464
Short name T311
Test name
Test status
Simulation time 178488470743 ps
CPU time 444.72 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 202076 kb
Host smart-5864f5c3-0d07-4273-b92c-953daaafe918
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086116464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2086116464
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2825342400
Short name T686
Test name
Test status
Simulation time 394900365947 ps
CPU time 785.29 seconds
Started Mar 14 12:35:50 PM PDT 24
Finished Mar 14 12:48:56 PM PDT 24
Peak memory 201692 kb
Host smart-f5753678-fa7c-40f9-a52c-bee341dcc8d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825342400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2825342400
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1899765326
Short name T782
Test name
Test status
Simulation time 118111891727 ps
CPU time 521.14 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:43:16 PM PDT 24
Peak memory 202388 kb
Host smart-64c995db-1a31-4cac-8e40-e59d00c2a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899765326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1899765326
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1848248619
Short name T100
Test name
Test status
Simulation time 38409303789 ps
CPU time 40.48 seconds
Started Mar 14 12:34:25 PM PDT 24
Finished Mar 14 12:35:06 PM PDT 24
Peak memory 201956 kb
Host smart-d1810e4c-6a0e-4fc9-8533-3c82c1ebb94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848248619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1848248619
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.998307022
Short name T608
Test name
Test status
Simulation time 3285379719 ps
CPU time 2.75 seconds
Started Mar 14 12:34:34 PM PDT 24
Finished Mar 14 12:34:37 PM PDT 24
Peak memory 201872 kb
Host smart-09310b2c-9b9b-49ed-912b-e2ee4e3f7c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998307022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.998307022
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3335788311
Short name T738
Test name
Test status
Simulation time 5893853719 ps
CPU time 4.58 seconds
Started Mar 14 12:34:28 PM PDT 24
Finished Mar 14 12:34:32 PM PDT 24
Peak memory 201956 kb
Host smart-8a62a8d3-1a64-4cad-a700-12f8e8916c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335788311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3335788311
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4177223963
Short name T674
Test name
Test status
Simulation time 410362278653 ps
CPU time 687.49 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:45:54 PM PDT 24
Peak memory 213372 kb
Host smart-b9ba6346-c502-4fd8-a3c4-3eec9ded2ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177223963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4177223963
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2096566687
Short name T689
Test name
Test status
Simulation time 50974724582 ps
CPU time 83.22 seconds
Started Mar 14 12:34:31 PM PDT 24
Finished Mar 14 12:35:54 PM PDT 24
Peak memory 210664 kb
Host smart-5f6c4885-a474-40b9-ac12-b6a397a98588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096566687 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2096566687
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1498179852
Short name T424
Test name
Test status
Simulation time 379583377 ps
CPU time 0.66 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:34:30 PM PDT 24
Peak memory 201860 kb
Host smart-1606bfae-65c8-4ef8-8a0d-14f4937d68dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498179852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1498179852
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3603516849
Short name T318
Test name
Test status
Simulation time 360137700640 ps
CPU time 413.83 seconds
Started Mar 14 12:35:36 PM PDT 24
Finished Mar 14 12:42:32 PM PDT 24
Peak memory 200668 kb
Host smart-956f20d7-4a64-48bd-ba3c-82bbb3347f58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603516849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3603516849
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3244473736
Short name T177
Test name
Test status
Simulation time 322830730859 ps
CPU time 149.14 seconds
Started Mar 14 12:34:29 PM PDT 24
Finished Mar 14 12:36:59 PM PDT 24
Peak memory 202088 kb
Host smart-5024004b-a842-4fe5-9068-0068af2d0e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244473736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3244473736
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.896350145
Short name T28
Test name
Test status
Simulation time 327845838237 ps
CPU time 586.22 seconds
Started Mar 14 12:34:27 PM PDT 24
Finished Mar 14 12:44:13 PM PDT 24
Peak memory 202132 kb
Host smart-93c0d2b4-dc41-4e28-afc1-463ea5632b89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=896350145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.896350145
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2136992277
Short name T1
Test name
Test status
Simulation time 165515011027 ps
CPU time 101.59 seconds
Started Mar 14 12:34:30 PM PDT 24
Finished Mar 14 12:36:12 PM PDT 24
Peak memory 202100 kb
Host smart-d968f62c-6db2-46db-98a0-3221b9bb6069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136992277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2136992277
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1980824336
Short name T664
Test name
Test status
Simulation time 327010390432 ps
CPU time 761.35 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:47:17 PM PDT 24
Peak memory 202096 kb
Host smart-ca42897c-b507-4333-855f-3a563f217182
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980824336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1980824336
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2930623615
Short name T325
Test name
Test status
Simulation time 365320757987 ps
CPU time 432.59 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:41:48 PM PDT 24
Peak memory 202152 kb
Host smart-e3399329-243d-45f4-8176-0def8be8396f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930623615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2930623615
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3896947626
Short name T394
Test name
Test status
Simulation time 384618450886 ps
CPU time 772.05 seconds
Started Mar 14 12:34:30 PM PDT 24
Finished Mar 14 12:47:22 PM PDT 24
Peak memory 201996 kb
Host smart-365d89eb-862f-49b7-8522-b4613dd602b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896947626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3896947626
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.369353322
Short name T54
Test name
Test status
Simulation time 86894220627 ps
CPU time 431.95 seconds
Started Mar 14 12:34:27 PM PDT 24
Finished Mar 14 12:41:39 PM PDT 24
Peak memory 202424 kb
Host smart-74fe622c-902e-4c83-9a0f-6e3e9d5db1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369353322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.369353322
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2788751903
Short name T395
Test name
Test status
Simulation time 24044117259 ps
CPU time 18.34 seconds
Started Mar 14 12:34:26 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 201932 kb
Host smart-b2b42637-63b8-4d9d-b928-045d5951243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788751903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2788751903
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.168681447
Short name T731
Test name
Test status
Simulation time 5212604716 ps
CPU time 11.99 seconds
Started Mar 14 12:34:36 PM PDT 24
Finished Mar 14 12:34:48 PM PDT 24
Peak memory 201964 kb
Host smart-bfac1b26-49dd-401e-872f-91d04078eec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168681447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.168681447
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1101403511
Short name T96
Test name
Test status
Simulation time 6097829451 ps
CPU time 7.96 seconds
Started Mar 14 12:34:32 PM PDT 24
Finished Mar 14 12:34:40 PM PDT 24
Peak memory 201932 kb
Host smart-7f981a92-9241-495e-a255-9b93c9e80910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101403511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1101403511
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2233762170
Short name T344
Test name
Test status
Simulation time 337864491675 ps
CPU time 353.7 seconds
Started Mar 14 12:34:32 PM PDT 24
Finished Mar 14 12:40:26 PM PDT 24
Peak memory 202040 kb
Host smart-6d8f91de-3219-4f01-9339-b1a74c144f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233762170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2233762170
Directory /workspace/9.adc_ctrl_stress_all/latest
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