Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7254	1			T1	57		T8	9		T35	86
testmodes[AdcCtrlTestmodeNormal]	5428	1			T1	48		T2	2		T3	3
testmodes[AdcCtrlTestmodeLowpower]	5420	1			T1	75		T5	1		T35	44
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4050	1			T1	18		T8	8		T35	46
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1731	1			T1	15		T8	1		T35	23
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1354	1			T1	23		T35	16		T34	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1743	1			T1	15		T35	20		T34	5
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1994	1			T1	10		T2	1		T3	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1356	1			T1	23		T35	17		T34	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1344	1			T1	24		T35	20		T34	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1373	1			T1	23		T35	13		T34	3
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2473	1			T1	28		T35	11		T34	18