Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20459

1

T1

180

T2

11

T8

24

auto[ADC_CTRL_FILTER_COND_OUT]

5530

1

T2

11

T3

29

T4

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20127

1

T1

180

T2

22

T8

24

auto[1]

5862

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	74	1			T184	1		T135	23		T185	1
values[1]	731	1			T2	11		T45	25		T47	22
values[2]	675	1			T2	11		T35	20		T112	1
values[3]	412	1			T12	12		T26	10		T30	13
values[4]	744	1			T10	1		T113	1		T117	19
values[5]	715	1			T8	14		T34	1		T44	12
values[6]	762	1			T139	11		T47	23		T119	7
values[7]	649	1			T119	20		T58	15		T59	23
values[8]	563	1			T7	1		T41	15		T110	1
values[9]	3483	1			T3	29		T4	19		T5	9
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	934	1			T45	25		T47	22		T58	17
values[1]	2875	1			T2	22		T3	29		T4	19
values[2]	432	1			T10	1		T12	12		T30	13
values[3]	848	1			T8	14		T59	28		T113	2
values[4]	659	1			T34	1		T44	12		T26	13
values[5]	671	1			T139	11		T47	23		T115	3
values[6]	676	1			T119	20		T113	1		T121	29
values[7]	561	1			T7	1		T110	1		T58	15
values[8]	841	1			T41	15		T12	4		T30	5
values[9]	303	1			T35	1		T47	19		T116	3
minimum	17189	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T45	14		T47	12		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T58	13		T143	2		T114	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T35	11		T26	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1630	1			T2	1		T3	3		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T30	1		T186	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T10	1		T12	7		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	7		T59	15		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T117	11		T118	9		T123	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T34	1		T44	5		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T44	7		T45	12		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T115	1		T116	1		T187	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T139	1		T47	11		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T119	7		T113	1		T121	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T119	1		T153	1		T189	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T110	1		T59	11		T190	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	1		T58	8		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	1		T12	4		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T109	19		T143	1		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T35	1		T47	15		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T191	1		T140	15		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17066	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	11		T47	10		T115	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T58	4		T114	7		T60	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	10		T35	9		T152	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	981	1			T2	10		T3	26		T4	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T30	12		T186	4		T125	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T12	5		T38	1		T125	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	7		T59	13		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	8		T118	10		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	2		T117	10		T192	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T45	11		T119	6		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T115	2		T116	10		T187	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	10		T47	12		T190	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T119	6		T121	12		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T119	6		T153	1		T194	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T59	12		T190	19		T125	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T58	7		T158	6		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T41	14		T30	4		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	17		T122	12		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T47	4		T116	2		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T191	1		T141	15		T195	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T8	1		T34	1		T70	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T185	1		T196	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T184	1		T135	12		T197	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	1		T45	14		T47	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T58	13		T143	2		T114	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	11		T112	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T114	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T26	10		T30	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	7		T38	4		T198	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T113	1		T186	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	1		T117	11		T118	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	7		T34	1		T44	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T44	7		T45	12		T153	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T115	1		T117	11		T192	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	1		T47	11		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T119	7		T59	11		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T119	1		T58	8		T189	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T41	1		T110	1		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	1		T158	1		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T35	1		T12	4		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1831	1			T3	3		T4	2		T5	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T196	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T135	11		T197	12		T199	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	10		T45	11		T47	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T58	4		T114	7		T192	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	9		T115	12		T169	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	10		T60	1		T123	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T30	12		T152	4		T200	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T12	5		T38	2		T198	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T186	4		T158	2		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T117	8		T118	10		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	7		T59	13		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	11		T153	7		T202	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T115	2		T117	10		T192	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T139	10		T47	12		T119	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T119	6		T59	12		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T119	6		T58	7		T32	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	14		T125	13		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T158	6		T172	8		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T30	4		T45	2		T47	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1070	1			T3	26		T4	17		T6	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T45	12		T47	11		T115	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T58	5		T143	2		T114	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	11		T35	10		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T2	11		T3	29		T4	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	13		T186	5		T125	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	1		T12	10		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	12		T59	14		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T117	9		T118	11		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T34	1		T44	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	1		T45	12		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T115	3		T116	11		T187	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	11		T47	13		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T119	7		T113	1		T121	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T119	7		T153	2		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T110	1		T59	13		T190	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T58	8		T158	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	15		T12	1		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T109	18		T143	1		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T35	1		T47	5		T116	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T191	2		T140	1		T141	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17189	1			T1	180		T8	10		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	13		T47	11		T203	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T58	12		T114	8		T192	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T35	10		T26	9		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1285	1			T5	8		T24	5		T46	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T146	11		T205	1		T206	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T12	2		T38	1		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	2		T59	14		T14	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T117	10		T118	8		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	4		T26	12		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T44	6		T45	11		T122	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T187	11		T207	7		T136	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T47	10		T190	12		T208	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T119	6		T121	16		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T189	4		T209	8		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T59	10		T190	23		T125	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T58	7		T172	9		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	3		T45	2		T59	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T109	18		T122	12		T192	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T47	14		T120	10		T211	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T140	14		T145	13		T195	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T185	1		T196	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T184	1		T135	12		T197	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	11		T45	12		T47	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	5		T143	2		T114	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	10		T112	1		T115	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	11		T114	1		T60	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T26	1		T30	13		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	10		T38	5		T198	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T113	1		T186	5		T158	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T117	9		T118	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	12		T34	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T44	1		T45	12		T153	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T115	3		T117	11		T192	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T139	11		T47	13		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T119	7		T59	13		T113	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T119	7		T58	8		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	15		T110	1		T125	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T158	7		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T35	1		T12	1		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1431	1			T3	29		T4	19		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T196	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T135	11		T197	12		T199	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T45	13		T47	11		T203	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T58	12		T114	8		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T35	10		T138	4		T212	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T124	16		T153	9		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T26	9		T205	1		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T12	2		T38	1		T198	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	4		T213	6		T134	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T117	10		T118	8		T123	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	2		T44	4		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T44	6		T45	11		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T117	10		T192	11		T36	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T47	10		T122	14		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T119	6		T59	10		T121	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T58	7		T189	4		T214	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T125	3		T193	11		T215	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T172	9		T209	8		T210	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T12	3		T45	2		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1470	1			T5	8		T24	5		T46	31

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22796

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3193

1

T2

11

T7

1

T41

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20079

1

T1

180

T7

1

T8

24

auto[1]

5910

1

T2

22

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T216	12		-	-		-	-
values[0]	30	1			T7	1		T191	2		T142	11
values[1]	727	1			T2	11		T47	23		T143	1
values[2]	767	1			T139	11		T47	22		T119	13
values[3]	828	1			T26	10		T45	5		T59	23
values[4]	812	1			T8	14		T12	12		T152	5
values[5]	410	1			T12	4		T119	7		T58	17
values[6]	687	1			T2	11		T41	15		T58	15
values[7]	587	1			T34	1		T110	1		T112	1
values[8]	2767	1			T3	29		T4	19		T5	9
values[9]	1181	1			T35	21		T26	13		T30	18
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T2	11		T7	1		T139	11
values[1]	854	1			T47	22		T59	23		T109	36
values[2]	750	1			T26	10		T45	5		T59	28
values[3]	676	1			T8	14		T12	12		T58	17
values[4]	530	1			T12	4		T119	7		T123	4
values[5]	741	1			T2	11		T41	15		T58	15
values[6]	2653	1			T3	29		T4	19		T5	9
values[7]	610	1			T10	1		T35	20		T44	12
values[8]	849	1			T35	1		T30	13		T45	23
values[9]	202	1			T26	13		T45	25		T113	1
minimum	17191	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	1		T143	1		T152	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	1		T139	1		T47	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T116	1		T117	11		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T47	12		T59	11		T109	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T60	1		T217	12		T185	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T26	10		T45	3		T59	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	7		T58	13		T152	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	7		T188	1		T201	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T119	1		T135	14		T209	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	4		T123	1		T203	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T58	8		T116	1		T192	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	1		T41	1		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1483	1			T3	3		T4	2		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	1		T110	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T35	11		T44	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T30	1		T112	1		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T35	1		T30	1		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T122	13		T36	1		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T45	14		T113	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T26	13		T184	1		T218	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T219	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	10		T152	4		T123	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T139	10		T47	12		T119	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T116	2		T117	10		T158	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	10		T59	12		T109	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T60	1		T217	6		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	2		T59	13		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	7		T58	4		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	5		T201	5		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T119	6		T135	10		T202	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T123	3		T203	16		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T58	7		T116	10		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	10		T41	14		T59	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	855	1			T3	26		T4	17		T6	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T119	6		T114	7		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	9		T117	8		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T30	4		T112	11		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	12		T45	11		T47	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T122	12		T14	4		T213	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T45	11		T153	1		T220	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T218	6		T200	15		T211	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T219	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T216	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T7	1		T191	1		T142	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	1		T143	1		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	11		T113	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T152	1		T123	11		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T139	1		T47	12		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T117	11		T60	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T26	10		T45	3		T59	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T8	7		T152	3		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	7		T188	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	1		T58	13		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T12	4		T123	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T58	8		T116	1		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T41	1		T59	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T112	1		T192	10		T189	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	1		T110	1		T114	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T3	3		T4	2		T5	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T119	1		T112	1		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T35	12		T30	1		T45	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T26	13		T30	1		T122	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T191	1		T221	13		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	10		T116	2		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	12		T223	7		T144	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T152	4		T123	11		T13	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T139	10		T47	10		T119	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T117	10		T60	1		T158	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	2		T59	12		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	7		T152	2		T115	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	5		T158	2		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T119	6		T58	4		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T123	3		T201	5		T213	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T58	7		T116	10		T187	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	10		T41	14		T59	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T192	7		T125	7		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T114	7		T192	2		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T3	26		T4	17		T6	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T119	6		T112	11		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	9		T30	12		T45	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T30	4		T122	12		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1