Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22528

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3461

1

T2

11

T41

15

T35

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20345

1

T1

180

T2

11

T7

1

auto[1]

5644

1

T2

11

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	271	1			T45	5		T116	3		T213	9
values[0]	27	1			T122	26		T287	1		-	-
values[1]	811	1			T2	11		T10	1		T26	13
values[2]	731	1			T7	1		T45	23		T58	15
values[3]	720	1			T41	15		T35	20		T139	11
values[4]	499	1			T143	1		T60	2		T120	22
values[5]	2886	1			T3	29		T4	19		T5	9
values[6]	800	1			T2	11		T35	1		T34	1
values[7]	498	1			T113	1		T115	13		T124	31
values[8]	682	1			T12	12		T110	1		T59	14
values[9]	883	1			T8	14		T26	10		T30	18
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	868	1			T2	11		T26	13		T119	13
values[1]	586	1			T7	1		T41	15		T45	23
values[2]	705	1			T35	20		T139	11		T143	2
values[3]	2703	1			T3	29		T4	19		T5	9
values[4]	703	1			T35	1		T12	4		T47	23
values[5]	742	1			T2	11		T34	1		T44	12
values[6]	675	1			T12	12		T113	1		T115	13
values[7]	550	1			T8	14		T110	1		T119	7
values[8]	885	1			T26	10		T30	18		T45	30
values[9]	122	1			T116	3		T17	2		T288	1
minimum	17450	1			T1	180		T8	10		T10	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	1		T112	1		T114	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T26	13		T119	7		T59	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T120	5		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T41	1		T45	12		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	1		T143	1		T117	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T35	11		T143	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T60	1		T190	13		T133	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	1		T12	4		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	1		T186	1		T192	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	1		T109	19		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T44	12		T47	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	7		T113	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T116	1		T192	14		T124	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	7		T110	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T59	9		T115	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T30	2		T45	14		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T26	10		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T116	1		T17	2		T270	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T288	1		T290	1		T291	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17168	1			T1	180		T8	9		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T47	12		T122	15		T202	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	10		T112	11		T117	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T119	6		T59	12		T117	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T120	2		T198	2		T141	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T41	14		T45	11		T119	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	10		T187	12		T136	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	9		T115	12		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T60	1		T190	12		T133	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T47	12		T58	4		T152	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T186	4		T192	7		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T109	17		T201	5		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	10		T47	4		T59	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	5		T115	12		T14	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T116	10		T192	2		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T8	7		T119	6		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T59	5		T115	2		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	16		T45	11		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	2		T123	11		T217	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T116	2		T292	2		T256	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T291	1		T259	13		T293	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T47	10		T122	11		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T116	1		T213	7		T209	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T45	3		T135	11		T144	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T287	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T122	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T2	1		T10	1		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	13		T47	12		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	1		T120	5		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	12		T58	8		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T139	1		T143	1		T117	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T41	1		T35	11		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T120	11		T187	12		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T143	1		T60	1		T190	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1561	1			T3	3		T4	2		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T113	1		T192	10		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T35	1		T34	1		T58	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	1		T44	12		T47	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T113	1		T115	1		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T124	17		T201	1		T203	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	7		T110	1		T172	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T59	9		T115	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T8	7		T30	2		T45	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	10		T143	1		T122	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T116	2		T213	2		T20	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T45	2		T135	6		T144	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T122	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	10		T112	11		T117	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T47	10		T119	6		T59	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T120	2		T198	2		T141	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T45	11		T58	7		T117	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T139	10		T212	4		T208	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T41	14		T35	9		T119	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T120	11		T187	12		T136	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T60	1		T190	12		T133	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T3	26		T4	17		T6	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T192	7		T125	9		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T58	4		T109	17		T201	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	10		T47	4		T59	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T115	12		T14	4		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T124	14		T203	16		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	5		T172	8		T132	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T59	5		T115	2		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T8	7		T30	16		T45	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T122	12		T123	11		T217	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	11		T112	12		T114	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T26	1		T119	7		T59	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	1		T120	3		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T41	15		T45	12		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	11		T143	1		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T35	10		T143	1		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T60	2		T190	13		T133	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T35	1		T12	1		T47	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T113	1		T186	5		T192	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	1		T109	18		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	11		T44	2		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	10		T113	1		T115	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T116	11		T192	3		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	12		T110	1		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T59	6		T115	3		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T30	18		T45	12		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T26	1		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T116	3		T17	2		T270	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T288	1		T290	1		T291	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17289	1			T1	180		T8	10		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T47	11		T122	12		T202	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T117	10		T192	11		T36	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	12		T119	6		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T120	4		T198	2		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T45	11		T58	7		T140	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T117	4		T187	11		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	10		T142	14		T294	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T5	8		T24	5		T46	31
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T190	12		T133	18		T193	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	3		T47	10		T58	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T192	9		T133	10		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T109	18		T38	1		T128	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	10		T47	14		T59	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	2		T14	4		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T192	13		T124	16		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	2		T172	9		T132	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T59	8		T122	12		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T45	13		T120	17		T213	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	9		T45	2		T123	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T292	4		T256	4		T295	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T291	1		T259	11		T293	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T190	23		T32	16		T210	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T47	11		T122	14		T15	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T116	3		T213	3		T209	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T45	3		T135	7		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T287	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T122	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T2	11		T10	1		T112	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	1		T47	11		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T120	3		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	12		T58	8		T117	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T139	11		T143	1		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T41	15		T35	10		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	12		T187	13		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T143	1		T60	2		T190	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T3	29		T4	19		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T113	1		T192	8		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	1		T34	1		T58	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	11		T44	2		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T113	1		T115	13		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T124	15		T201	1		T203	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	10		T110	1		T172	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T59	6		T115	3		T116	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T8	12		T30	18		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	1		T143	1		T122	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T213	6		T209	8		T20	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T45	2		T135	10		T144	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T122	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T117	10		T192	11		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	12		T47	11		T119	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T120	4		T198	2		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	11		T58	7		T117	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T117	4		T189	12		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T35	10		T142	14		T294	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T120	10		T187	11		T207	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T190	12		T133	18		T296	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T5	8		T12	3		T24	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T192	9		T125	1		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T58	12		T109	18		T128	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T44	10		T47	14		T59	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	4		T189	4		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T124	16		T203	15		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	2		T172	9		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	8		T192	13		T153	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	2		T45	13		T120	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	9		T122	12		T123	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10