Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22418

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3571

1

T2

11

T41

15

T35

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19835

1

T1

178

T7

1

T8

24

auto[1]

6154

1

T1

2

T2

22

T3

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	424	1			T1	2		T35	7		T34	2
values[0]	44	1			T15	18		T19	20		T157	5
values[1]	535	1			T30	13		T113	1		T117	19
values[2]	2941	1			T3	29		T4	19		T5	9
values[3]	649	1			T35	1		T34	1		T44	5
values[4]	684	1			T2	11		T139	11		T47	23
values[5]	787	1			T35	20		T143	1		T117	5
values[6]	745	1			T8	14		T44	7		T30	5
values[7]	732	1			T41	15		T12	4		T26	13
values[8]	496	1			T7	1		T10	1		T12	12
values[9]	1148	1			T2	11		T143	1		T113	1
minimum	16804	1			T1	178		T8	10		T35	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	802	1			T30	13		T45	28		T113	1
values[1]	2828	1			T3	29		T4	19		T5	9
values[2]	593	1			T139	11		T59	23		T109	36
values[3]	802	1			T2	11		T35	20		T34	1
values[4]	823	1			T47	22		T58	17		T143	1
values[5]	670	1			T8	14		T44	7		T12	4
values[6]	731	1			T7	1		T41	15		T26	13
values[7]	460	1			T10	1		T12	12		T119	7
values[8]	840	1			T2	11		T113	1		T152	5
values[9]	214	1			T114	16		T120	29		T37	7
minimum	17226	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T30	1		T113	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T45	15		T115	1		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T3	3		T4	2		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	1		T114	1		T213	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T59	11		T109	19		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T139	1		T118	9		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T47	26		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T35	11		T34	1		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T47	12		T117	5		T60	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T58	13		T143	1		T187	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	7		T44	7		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	4		T45	14		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T26	13		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T41	1		T115	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	1		T12	7		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T119	1		T112	1		T121	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T188	1		T122	15		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	1		T113	1		T152	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T120	18		T37	5		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T114	9		T297	1		T276	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T296	5		T270	1		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	12		T153	1		T144	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T45	13		T115	12		T117	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T3	26		T4	17		T6	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T213	2		T191	1		T128	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T59	12		T109	17		T186	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T139	10		T118	10		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	10		T47	16		T192	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T35	9		T119	6		T59	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T47	10		T60	1		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T58	4		T187	10		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	7		T30	4		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	11		T59	5		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T112	11		T116	2		T120	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T41	14		T115	12		T158	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	5		T115	2		T133	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T119	6		T121	12		T282	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T122	11		T192	12		T132	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	10		T152	2		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T120	11		T37	2		T251	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T114	7		T276	6		T249	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T296	5		T157	1		T298	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T1	2		T35	7		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T114	9		T240	27		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T15	11		T19	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T157	4		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T30	1		T113	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T117	11		T13	10		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1569	1			T3	3		T4	2		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T45	15		T114	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	5		T47	15		T58	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	1		T34	1		T118	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T2	1		T47	11		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T139	1		T119	7		T59	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T117	5		T60	1		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T35	11		T143	1		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T8	7		T44	7		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	14		T58	13		T59	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T26	13		T115	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T41	1		T12	4		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T10	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T112	1		T158	1		T121	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T143	1		T188	1		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T2	1		T113	1		T152	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16688	1			T1	178		T8	9		T35	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T242	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T114	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T15	7		T19	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T157	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T30	12		T153	1		T144	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T117	8		T13	6		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T3	26		T4	17		T6	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	13		T115	12		T191	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	4		T58	7		T59	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T118	10		T213	2		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	10		T47	12		T190	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T139	10		T119	6		T59	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	1		T120	11		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T35	9		T122	12		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	7		T30	4		T47	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T45	11		T58	4		T59	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T115	2		T116	2		T120	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T41	14		T119	6		T115	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	5		T133	17		T125	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T158	6		T121	12		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T122	11		T120	11		T192	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	10		T152	2		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T30	13		T113	1		T153	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T45	15		T115	13		T117	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T3	29		T4	19		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	1		T114	1		T213	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	13		T109	18		T186	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	11		T118	11		T153	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	11		T47	18		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T35	10		T34	1		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T47	11		T117	1		T60	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T58	5		T143	1		T187	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	12		T44	1		T30	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T45	12		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	1		T26	1		T112	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T41	15		T115	13		T158	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	1		T12	10		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T119	7		T112	1		T121	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T188	1		T122	12		T192	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	11		T113	1		T152	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T120	12		T37	5		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T114	8		T297	1		T276	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T296	6		T270	1		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T144	8		T142	10		T205	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T45	13		T117	10		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T5	8		T44	4		T24	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T213	6		T128	15		T206	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T59	10		T109	18		T264	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T118	8		T153	9		T135	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	24		T192	9		T190	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	10		T119	6		T59	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T47	11		T117	4		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T58	12		T187	13		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T8	2		T44	6		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	3		T45	13		T59	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T26	12		T120	4		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T172	9		T14	4		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	2		T133	18		T140	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T121	16		T189	12		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T122	14		T192	11		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T152	2		T192	13		T36	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T120	17		T37	2		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T114	8		T276	3		T240	26
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T296	4		T157	1		T298	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T1	2		T35	7		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T114	8		T240	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T15	12		T19	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T157	4		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T30	13		T113	1		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T117	9		T13	11		T184	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T3	29		T4	19		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T45	15		T114	1		T115	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T44	1		T47	5		T58	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	1		T34	1		T118	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	11		T47	13		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T139	11		T119	7		T59	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T117	1		T60	2		T120	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T35	10		T143	1		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	12		T44	1		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	12		T58	5		T59	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T26	1		T115	3		T116	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T41	15		T12	1		T119	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T10	1		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T112	1		T158	7		T121	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T143	1		T188	1		T122	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T2	11		T113	1		T152	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16804	1			T1	178		T8	10		T35	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T114	8		T240	26		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T15	6		T19	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T157	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T144	8		T208	10		T299	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T117	10		T13	5		T189	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T5	8		T24	5		T26	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T45	13		T140	14		T128	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	4		T47	14		T58	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T118	8		T213	6		T135	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T47	10		T190	12		T217	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T119	6		T59	14		T153	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T117	4		T120	10		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	10		T122	12		T123	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	2		T44	6		T47	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T45	13		T58	12		T59	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T26	12		T120	4		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	3		T190	23		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	2		T133	18		T140	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T121	16		T172	9		T14	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T122	14		T120	17		T192	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T152	2		T192	13		T36	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10