Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23067

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

2922

1

T2

11

T35

1

T44

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20169

1

T1

180

T2

11

T7

1

auto[1]

5820

1

T2

11

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	414	1			T45	25		T59	23		T152	5
values[0]	28	1			T262	8		T19	20		-	-
values[1]	603	1			T12	12		T47	22		T152	5
values[2]	677	1			T2	11		T35	20		T45	5
values[3]	554	1			T8	14		T35	1		T45	23
values[4]	749	1			T119	13		T143	1		T113	1
values[5]	3044	1			T3	29		T4	19		T5	9
values[6]	637	1			T26	10		T30	13		T47	23
values[7]	638	1			T2	11		T41	15		T44	7
values[8]	667	1			T7	1		T119	7		T143	1
values[9]	797	1			T10	1		T44	5		T12	4
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	647	1			T2	11		T35	20		T12	12
values[1]	546	1			T45	5		T47	19		T119	7
values[2]	609	1			T8	14		T35	1		T45	23
values[3]	3028	1			T3	29		T4	19		T5	9
values[4]	728	1			T34	1		T26	13		T30	5
values[5]	700	1			T2	11		T41	15		T26	10
values[6]	690	1			T44	7		T60	2		T158	3
values[7]	608	1			T7	1		T10	1		T119	7
values[8]	832	1			T12	4		T58	17		T59	23
values[9]	197	1			T44	5		T45	25		T112	12
minimum	17404	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T35	11		T47	12		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	1		T12	7		T116	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	15		T117	5		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	3		T119	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	7		T45	12		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T35	1		T119	7		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T110	1		T115	1		T140	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T34	1		T26	13		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T123	11		T190	24		T187	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	1		T41	1		T26	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T38	1		T125	6		T193	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T192	26		T190	13		T136	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	7		T60	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	1		T10	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T59	9		T143	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T58	13		T59	11		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	4		T114	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T44	5		T112	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T45	14		T115	1		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17118	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T132	3		T210	13		T294	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	9		T47	10		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	10		T12	5		T116	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	4		T153	1		T282	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	2		T119	6		T123	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	7		T45	11		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T119	6		T201	5		T187	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T115	12		T194	13		T205	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	4		T58	7		T109	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T123	11		T190	19		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	10		T41	14		T30	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T38	1		T125	22		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T192	14		T190	12		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T60	1		T158	2		T13	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T119	6		T59	13		T191	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T59	5		T213	7		T232	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T58	4		T59	12		T152	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T115	2		T117	8		T203	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T112	11		T146	14		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T45	11		T115	12		T275	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T132	14		T294	13		T301	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T59	11		T152	1		T189	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T45	14		T115	1		T117	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T262	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T19	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	12		T152	3		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	7		T124	17		T132	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T35	11		T47	15		T117	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T45	3		T119	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	7		T45	12		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T35	1		T113	1		T187	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T143	1		T122	15		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T119	7		T113	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T3	3		T4	2		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T110	1		T123	11		T190	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T26	10		T30	1		T47	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T132	1		T125	2		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T41	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T44	7		T60	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T119	1		T192	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	1		T188	1		T213	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	1		T44	5		T58	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	4		T59	9		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T59	12		T152	4		T249	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	11		T115	12		T117	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T19	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T47	10		T152	2		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	5		T124	14		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T35	9		T47	4		T117	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T2	10		T45	2		T119	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	7		T45	11		T121	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T187	12		T217	6		T169	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T122	11		T186	4		T135	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T119	6		T115	12		T201	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T3	26		T4	17		T6	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T123	11		T190	19		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	12		T47	12		T109	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T132	4		T125	9		T193	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	10		T41	14		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	1		T158	2		T13	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T119	6		T192	2		T191	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T213	7		T232	2		T32	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T58	4		T59	13		T112	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T59	5		T115	2		T203	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T35	10		T47	11		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	11		T12	10		T116	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	5		T117	1		T153	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	3		T119	7		T123	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	12		T45	12		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T35	1		T119	7		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T110	1		T115	13		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T34	1		T26	1		T30	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T123	12		T190	20		T187	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	11		T41	15		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	2		T125	24		T193	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T192	16		T190	13		T136	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T44	1		T60	2		T158	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T10	1		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T59	6		T143	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T58	5		T59	13		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T12	1		T114	1		T115	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T44	1		T112	12		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T45	12		T115	13		T300	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17244	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T132	15		T210	1		T294	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	10		T47	11		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	2		T124	16		T264	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T47	14		T117	4		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T45	2		T172	9		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	2		T45	11		T121	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T119	6		T187	11		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T5	8		T24	5		T46	31
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T140	14		T205	2		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T26	12		T58	7		T109	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T123	10		T190	23		T187	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T26	9		T47	10		T120	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T125	4		T193	11		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T192	24		T190	12		T136	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T44	6		T13	5		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T59	14		T207	12		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T59	8		T213	11		T32	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T58	12		T59	10		T114	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	3		T117	10		T203	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T44	4		T146	11		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T45	13		T275	11		T257	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T153	7		T254	9		T262	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T132	2		T210	12		T294	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T59	13		T152	5		T189	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	12		T115	13		T117	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T262	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T19	17		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	11		T152	3		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	10		T124	15		T132	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	10		T47	5		T117	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	11		T45	3		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	12		T45	12		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	1		T113	1		T187	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T143	1		T122	12		T186	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T119	7		T113	1		T115	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T3	29		T4	19		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T110	1		T123	12		T190	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T26	1		T30	13		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	5		T125	10		T193	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	11		T41	15		T139	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	1		T60	2		T158	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T119	7		T192	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	1		T188	1		T213	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	1		T44	1		T58	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T59	6		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T59	10		T189	4		T145	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T45	13		T117	10		T231	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T262	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	11		T152	2		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	2		T124	16		T132	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	10		T47	14		T117	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T45	2		T172	9		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	2		T45	11		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T187	11		T217	11		T276	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T122	14		T140	14		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T119	6		T140	14		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T5	8		T24	5		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T123	10		T190	23		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T26	9		T47	10		T109	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T125	1		T193	11		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T192	20		T190	12		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T44	6		T13	5		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T192	13		T207	12		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T213	11		T32	16		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	4		T58	12		T59	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	3		T59	8		T203	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10