Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22550

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3439

1

T2

11

T10

1

T12

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20353

1

T1

180

T2

22

T8

10

auto[1]

5636

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T143	2		T203	32		T32	10
values[0]	43	1			T132	17		T232	3		T264	21
values[1]	880	1			T2	11		T35	20		T34	1
values[2]	882	1			T7	1		T12	4		T26	13
values[3]	604	1			T2	11		T139	11		T109	36
values[4]	2843	1			T3	29		T4	19		T5	9
values[5]	657	1			T41	15		T47	19		T114	16
values[6]	634	1			T35	1		T30	13		T45	25
values[7]	515	1			T58	17		T143	1		T113	1
values[8]	666	1			T8	14		T10	1		T119	7
values[9]	853	1			T44	7		T45	5		T152	5
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	832	1			T35	20		T34	1		T44	5
values[1]	830	1			T7	1		T47	22		T119	13
values[2]	542	1			T2	11		T139	11		T116	3
values[3]	2851	1			T3	29		T4	19		T5	9
values[4]	741	1			T41	15		T114	16		T121	29
values[5]	560	1			T35	1		T30	13		T45	25
values[6]	440	1			T58	17		T143	1		T113	2
values[7]	826	1			T8	14		T10	1		T119	7
values[8]	644	1			T44	7		T45	5		T143	1
values[9]	189	1			T143	1		T203	32		T136	24
minimum	17534	1			T1	180		T2	11		T8	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T35	11		T34	1		T44	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T30	1		T114	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T59	20		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T47	12		T119	7		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T124	17		T135	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T139	1		T116	1		T120	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1477	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T12	7		T45	12		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	1		T213	7		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T114	9		T121	17		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	1		T45	14		T120	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	1		T115	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T58	13		T118	9		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T143	1		T113	2		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	7		T58	8		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	1		T119	1		T59	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T44	7		T45	3		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	1		T192	14		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T203	16		T136	9		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T143	1		T261	4		T234	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17150	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T2	1		T110	1		T132	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	9		T47	12		T186	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T30	4		T117	8		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T59	17		T152	2		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	10		T119	6		T112	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	10		T124	14		T135	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T139	10		T116	2		T120	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	914	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	5		T45	11		T119	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T41	14		T213	2		T232	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T114	7		T121	12		T194	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T45	11		T120	2		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T30	12		T115	12		T134	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T58	4		T118	10		T158	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T123	3		T223	7		T251	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	7		T58	7		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T119	6		T59	13		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T45	2		T115	12		T192	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T152	4		T192	2		T133	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T203	16		T136	15		T233	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T261	3		T302	16		T236	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	10		T132	14		T232	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T143	1		T203	16		T136	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T143	1		T32	1		T245	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T237	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T132	3		T232	1		T264	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T35	11		T34	1		T44	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T30	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T12	4		T26	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T47	12		T119	7		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	1		T124	17		T189	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	1		T109	19		T187	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T3	3		T4	2		T5	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	7		T45	12		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	1		T47	15		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T114	9		T121	17		T213	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	1		T45	14		T120	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T30	1		T184	1		T140	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T58	13		T118	9		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	1		T113	1		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	7		T58	8		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T119	1		T59	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T44	7		T45	3		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T152	1		T192	14		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T203	16		T136	15		T233	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T32	9		T245	4		T264	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T237	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T132	14		T232	2		T264	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T35	9		T47	12		T186	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	10		T30	4		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T59	17		T152	2		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	10		T119	6		T112	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	10		T124	14		T135	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T139	10		T109	17		T187	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T3	26		T4	17		T6	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	5		T45	11		T119	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T41	14		T47	4		T205	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T114	7		T121	12		T213	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	11		T120	2		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	12		T141	15		T194	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T58	4		T118	10		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T115	12		T123	3		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	7		T58	7		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T119	6		T59	13		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	2		T115	12		T192	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T152	4		T192	2		T133	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	10		T34	1		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T30	5		T114	1		T188	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	1		T59	19		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	11		T119	7		T112	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	11		T124	15		T135	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T139	11		T116	3		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	10		T45	12		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T41	15		T213	3		T232	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T114	8		T121	13		T194	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T35	1		T45	12		T120	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T30	13		T115	13		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T58	5		T118	11		T158	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T143	1		T113	2		T123	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T8	12		T58	8		T116	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T119	7		T59	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T44	1		T45	3		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T152	5		T192	3		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T203	17		T136	16		T233	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T143	1		T261	4		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17268	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	11		T110	1		T132	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T35	10		T44	4		T12	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T117	10		T122	12		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T59	18		T152	2		T117	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	11		T119	6		T109	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T124	16		T135	13		T137	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T120	17		T145	13		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T5	8		T24	5		T26	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	2		T45	11		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T213	6		T145	9		T205	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T114	8		T121	16		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T45	13		T120	4		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T140	14		T134	10		T207	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T58	12		T118	8		T207	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T140	14		T208	10		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	2		T58	7		T125	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T59	14		T120	10		T125	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T44	6		T45	2		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T192	13		T133	18		T210	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T203	15		T136	8		T168	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T261	3		T234	9		T239	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T132	10		T135	11		T195	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T132	2		T32	16		T264	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T143	1		T203	17		T136	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T143	1		T32	10		T245	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T237	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T132	15		T232	3		T264	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T35	10		T34	1		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	11		T30	5		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T12	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T47	11		T119	7		T112	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	11		T124	15		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	11		T109	18		T187	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T3	29		T4	19		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	10		T45	12		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T41	15		T47	5		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T114	8		T121	13		T213	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	1		T45	12		T120	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	13		T184	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T58	5		T118	11		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T143	1		T113	1		T115	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	12		T58	8		T116	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T119	7		T59	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T44	1		T45	3		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T152	5		T192	3		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T203	15		T136	8		T206	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T264	9		T239	10		T303	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T132	2		T264	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T35	10		T44	4		T47	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T122	12		T37	2		T32	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	3		T26	12		T59	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T47	11		T119	6		T117	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T124	16		T189	12		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T109	18		T187	13		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T5	8		T24	5		T26	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	2		T45	11		T123	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	14		T145	9		T205	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T114	8		T121	16		T213	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T45	13		T120	4		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T140	14		T142	14		T211	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T58	12		T118	8		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	14		T134	10		T207	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T8	2		T58	7		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T59	14		T120	10		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T44	6		T45	2		T192	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T192	13		T133	18		T137	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10