Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20442

1

T1

180

T2

11

T8

24

auto[ADC_CTRL_FILTER_COND_OUT]

5547

1

T2

11

T3

29

T4

19

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20171

1

T1

180

T2

22

T8

24

auto[1]

5818

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	313	1			T35	1		T109	36		T115	13
values[0]	57	1			T184	1		T135	23		T243	8
values[1]	756	1			T2	11		T45	25		T47	22
values[2]	620	1			T2	11		T35	20		T112	1
values[3]	516	1			T12	12		T26	10		T30	13
values[4]	688	1			T10	1		T113	1		T117	19
values[5]	756	1			T8	14		T34	1		T44	12
values[6]	679	1			T139	11		T47	23		T115	3
values[7]	647	1			T119	20		T113	1		T116	11
values[8]	611	1			T7	1		T110	1		T58	15
values[9]	3165	1			T3	29		T4	19		T5	9
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	777	1			T2	11		T45	25		T58	17
values[1]	2837	1			T2	11		T3	29		T4	19
values[2]	443	1			T12	12		T30	13		T186	5
values[3]	837	1			T10	1		T59	28		T113	2
values[4]	659	1			T8	14		T34	1		T44	12
values[5]	615	1			T139	11		T47	23		T115	3
values[6]	734	1			T119	20		T59	23		T113	1
values[7]	531	1			T7	1		T110	1		T58	15
values[8]	967	1			T41	15		T12	4		T30	5
values[9]	191	1			T35	1		T47	19		T115	13
minimum	17398	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T45	14		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T58	13		T143	2		T114	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	11		T26	10		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1616	1			T2	1		T3	3		T4	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	1		T186	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	7		T38	3		T140	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T59	15		T113	2		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T10	1		T117	11		T118	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	7		T34	1		T44	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T44	7		T45	12		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T115	1		T116	1		T187	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T139	1		T47	11		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T119	7		T59	11		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T119	1		T153	1		T189	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T110	1		T190	24		T125	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	1		T58	8		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T41	1		T12	4		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T109	19		T143	1		T192	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T35	1		T47	15		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T122	13		T191	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T192	10		T184	1		T132	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	10		T45	11		T115	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T58	4		T114	7		T60	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	9		T152	4		T169	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T2	10		T3	26		T4	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T30	12		T186	4		T125	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	5		T38	1		T125	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	13		T158	2		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T117	8		T118	10		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	7		T152	2		T117	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T45	11		T119	6		T122	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T115	2		T116	10		T187	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T139	10		T47	12		T190	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T119	6		T59	12		T121	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T119	6		T153	1		T194	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T190	19		T125	13		T215	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T58	7		T158	6		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T41	14		T30	4		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T109	17		T192	2		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T47	4		T115	12		T116	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T122	12		T191	1		T141	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	1		T34	1		T47	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T192	7		T132	12		T135	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T35	1		T115	1		T116	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T109	19		T191	1		T304	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T243	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T184	1		T135	12		T197	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T45	14		T47	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T58	13		T143	2		T114	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T35	11		T112	1		T169	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T114	1		T60	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T26	10		T30	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	7		T38	4		T125	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T113	1		T186	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	1		T117	11		T118	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	7		T34	1		T44	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T44	7		T45	12		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T115	1		T117	11		T36	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T139	1		T47	11		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T119	7		T113	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T119	1		T189	5		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T110	1		T59	11		T125	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	1		T58	8		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T41	1		T12	4		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1749	1			T3	3		T4	2		T5	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T115	12		T116	2		T120	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T109	17		T191	1		T275	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T243	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T135	11		T197	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	10		T45	11		T47	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T58	4		T114	7		T192	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	9		T169	19		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	10		T60	1		T123	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T30	12		T152	4		T251	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T12	5		T38	2		T125	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T186	4		T158	2		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T117	8		T118	10		T123	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	7		T59	13		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	11		T119	6		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T115	2		T117	10		T36	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T139	10		T47	12		T122	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T119	6		T116	10		T121	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T119	6		T32	9		T208	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	12		T125	13		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	7		T158	6		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T41	14		T30	4		T45	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1017	1			T3	26		T4	17		T6	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	11		T45	12		T115	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T58	5		T143	2		T114	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T35	10		T26	1		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T2	11		T3	29		T4	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T30	13		T186	5		T125	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	10		T38	3		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T59	14		T113	2		T158	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	1		T117	9		T118	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	12		T34	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T45	12		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T115	3		T116	11		T187	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	11		T47	13		T188	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T119	7		T59	13		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T119	7		T153	2		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T110	1		T190	20		T125	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	1		T58	8		T158	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T41	15		T12	1		T30	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T109	18		T143	1		T192	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T35	1		T47	5		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T122	13		T191	2		T141	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17234	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T192	8		T184	1		T132	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T45	13		T203	15		T32	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T58	12		T114	8		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T35	10		T26	9		T205	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T5	8		T24	5		T46	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T146	11		T206	27		T160	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T12	2		T38	1		T140	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T59	14		T14	4		T213	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T117	10		T118	8		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	2		T44	4		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	6		T45	11		T117	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T187	11		T132	2		T136	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T47	10		T190	12		T305	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T119	6		T59	10		T121	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T189	4		T209	8		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T190	23		T125	3		T215	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T58	7		T172	9		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	3		T45	2		T59	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T109	18		T192	13		T37	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T47	14		T227	2		T306	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T122	12		T145	13		T195	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T47	11		T19	4		T196	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T192	9		T132	10		T135	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T35	1		T115	13		T116	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T109	18		T191	2		T304	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T243	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T184	1		T135	12		T197	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	11		T45	12		T47	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T58	5		T143	2		T114	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	10		T112	1		T169	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	11		T114	1		T60	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T26	1		T30	13		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	10		T38	5		T125	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T113	1		T186	5		T158	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	1		T117	9		T118	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	12		T34	1		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	1		T45	12		T119	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T115	3		T117	11		T36	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	11		T47	13		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T119	7		T113	1		T116	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T119	7		T189	1		T32	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T110	1		T59	13		T125	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T58	8		T158	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T41	15		T12	1		T30	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1373	1			T3	29		T4	19		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T120	10		T237	7		T168	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T109	18		T304	17		T279	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T135	11		T197	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	13		T47	11		T203	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T58	12		T114	8		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T35	10		T138	4		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T124	16		T153	9		T133	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T26	9		T146	11		T204	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T12	2		T38	1		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	4		T213	6		T134	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T117	10		T118	8		T123	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	2		T44	4		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	6		T45	11		T117	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T117	10		T36	3		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T47	10		T122	14		T192	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T119	6		T121	16		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T189	4		T214	6		T208	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T59	10		T125	3		T193	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T58	7		T172	9		T209	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T45	2		T47	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1393	1			T5	8		T24	5		T46	31

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10