Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22523

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3466

1

T2

11

T41

15

T35

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20340

1

T1

180

T2

11

T7

1

auto[1]

5649

1

T2

11

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T214	7		T265	24		T307	15
values[0]	71	1			T26	13		T195	21		T308	11
values[1]	731	1			T2	11		T10	1		T47	22
values[2]	779	1			T7	1		T45	23		T58	15
values[3]	739	1			T41	15		T35	20		T139	11
values[4]	516	1			T143	1		T190	25		T133	36
values[5]	2833	1			T3	29		T4	19		T5	9
values[6]	769	1			T2	11		T35	1		T34	1
values[7]	574	1			T113	1		T115	13		T124	31
values[8]	617	1			T12	12		T110	1		T59	14
values[9]	1132	1			T8	14		T26	10		T30	18
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1069	1			T2	11		T7	1		T10	1
values[1]	637	1			T41	15		T45	23		T119	7
values[2]	660	1			T139	11		T143	1		T113	1
values[3]	2740	1			T3	29		T4	19		T5	9
values[4]	680	1			T35	1		T12	4		T47	23
values[5]	738	1			T2	11		T34	1		T44	12
values[6]	654	1			T12	12		T110	1		T113	1
values[7]	555	1			T59	14		T115	3		T122	25
values[8]	800	1			T8	14		T26	10		T30	18
values[9]	222	1			T116	3		T123	22		T17	2
minimum	17234	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T2	1		T7	1		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T26	13		T119	7		T59	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T120	5		T198	4		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T41	1		T45	12		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	1		T117	5		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T143	1		T113	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T35	11		T60	1		T192	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	1		T12	4		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T59	15		T113	1		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	1		T109	19		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T2	1		T44	12		T47	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	7		T110	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T116	1		T192	14		T124	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T172	10		T184	1		T132	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T59	9		T115	1		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T8	7		T30	2		T45	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	10		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T116	1		T17	2		T292	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T123	11		T309	1		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17067	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T47	12		T148	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T2	10		T117	10		T192	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T119	6		T59	12		T117	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T120	2		T198	2		T141	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T41	14		T45	11		T119	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T139	10		T187	12		T136	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T115	12		T158	2		T294	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T35	9		T60	1		T192	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	12		T58	4		T152	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T59	13		T186	4		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T109	17		T201	5		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	10		T47	4		T118	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	5		T115	12		T14	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T116	10		T192	2		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T172	8		T132	14		T128	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	5		T115	2		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	7		T30	16		T45	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	2		T217	6		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T116	2		T292	2		T256	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T123	11		T243	12		T291	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T34	1		T112	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T47	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T307	11		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T214	7		T265	15		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T308	1		T312	1		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T26	13		T195	10		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	1		T10	1		T112	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	12		T119	7		T122	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T117	5		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T45	12		T58	8		T59	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T139	1		T143	1		T187	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T41	1		T35	11		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T159	1		T207	8		T297	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T143	1		T190	13		T133	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T3	3		T4	2		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	5		T113	1		T192	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T35	1		T34	1		T58	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T44	7		T47	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T113	1		T115	1		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T124	17		T201	1		T203	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	7		T110	1		T172	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T59	9		T115	1		T116	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T8	7		T30	2		T45	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T26	10		T45	3		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T307	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T308	10		T312	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T195	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T2	10		T112	11		T117	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T47	10		T119	6		T122	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T198	2		T141	15		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	11		T58	7		T59	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T139	10		T187	12		T245	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T41	14		T35	9		T119	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	2		T146	14		T160	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T190	12		T133	17		T194	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T3	26		T4	17		T6	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T192	7		T125	9		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T58	4		T109	17		T169	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	10		T47	4		T59	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T115	12		T14	4		T32	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T124	14		T203	16		T153	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	5		T172	8		T132	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T59	5		T115	2		T116	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T8	7		T30	16		T45	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T45	2		T122	12		T123	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T2	11		T7	1		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T26	1		T119	7		T59	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	3		T198	4		T141	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T41	15		T45	12		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T139	11		T117	1		T187	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T143	1		T113	1		T115	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	10		T60	2		T192	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	1		T12	1		T47	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T59	14		T113	1		T186	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	1		T109	18		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	11		T44	2		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	10		T110	1		T113	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T116	11		T192	3		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T172	9		T184	1		T132	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T59	6		T115	3		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T8	12		T30	18		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	1		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T116	3		T17	2		T292	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T123	12		T309	1		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17202	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T47	11		T148	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T117	10		T192	11		T36	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	12		T119	6		T59	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T120	4		T198	2		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T45	11		T58	7		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T117	4		T187	11		T189	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T142	14		T294	9		T148	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T5	8		T24	5		T46	31
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	10		T192	9		T190	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	3		T47	10		T58	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T59	14		T133	10		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T109	18		T38	1		T128	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T44	10		T47	14		T118	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	2		T14	4		T189	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T192	13		T124	16		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T172	9		T132	2		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T59	8		T122	12		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	2		T45	13		T120	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	9		T45	2		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T292	4		T256	4		T295	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T123	10		T291	1		T163	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T47	11		T148	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T307	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T214	1		T265	10		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T308	11		T312	5		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T26	1		T195	12		T313	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T2	11		T10	1		T112	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T47	11		T119	7		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	1		T117	1		T289	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T45	12		T58	8		T59	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	11		T143	1		T187	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T41	15		T35	10		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T159	1		T207	1		T297	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T143	1		T190	13		T133	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T3	29		T4	19		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	1		T113	1		T192	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	1		T34	1		T58	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	11		T44	1		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T113	1		T115	13		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T124	15		T201	1		T203	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	10		T110	1		T172	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T59	6		T115	3		T116	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T8	12		T30	18		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T26	1		T45	3		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T307	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T214	6		T265	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T258	1		T314	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T26	12		T195	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T117	10		T120	4		T192	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T47	11		T119	6		T122	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T117	4		T198	2		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	11		T58	7		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T187	11		T189	12		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T35	10		T294	9		T304	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T207	7		T136	4		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T190	12		T133	18		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T5	8		T12	3		T24	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T44	4		T192	9		T125	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T58	12		T109	18		T128	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T44	6		T47	14		T59	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T14	4		T189	4		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T124	16		T203	15		T153	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	2		T172	9		T132	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T59	8		T192	13		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	2		T45	13		T120	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T26	9		T45	2		T122	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10