Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22686

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3303

1

T2

11

T7

1

T41

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20034

1

T1

180

T7

1

T8

10

auto[1]

5955

1

T2

22

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	263	1			T35	1		T45	25		T122	51
values[0]	23	1			T191	2		T144	9		T302	9
values[1]	777	1			T2	11		T7	1		T47	23
values[2]	700	1			T139	11		T47	22		T119	13
values[3]	908	1			T26	10		T45	5		T59	51
values[4]	711	1			T8	14		T12	12		T152	5
values[5]	455	1			T12	4		T119	7		T58	17
values[6]	697	1			T2	11		T41	15		T58	15
values[7]	584	1			T34	1		T59	14		T112	1
values[8]	2812	1			T3	29		T4	19		T5	9
values[9]	878	1			T35	20		T26	13		T30	18
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	779	1			T139	11		T47	23		T119	13
values[1]	793	1			T26	10		T47	22		T143	1
values[2]	754	1			T45	5		T59	51		T113	1
values[3]	707	1			T8	14		T12	12		T58	17
values[4]	533	1			T12	4		T119	7		T123	4
values[5]	735	1			T2	11		T41	15		T58	15
values[6]	2641	1			T3	29		T4	19		T5	9
values[7]	603	1			T10	1		T35	20		T44	12
values[8]	917	1			T35	1		T26	13		T30	13
values[9]	131	1			T45	25		T113	1		T153	2
minimum	17396	1			T1	180		T2	11		T7	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	1		T123	11		T36	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T139	1		T47	11		T119	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T116	1		T117	11		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T26	10		T47	12		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T60	1		T217	12		T185	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	3		T59	26		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	7		T58	13		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	7		T152	3		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T119	1		T135	14		T209	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	4		T123	1		T203	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T58	8		T116	1		T192	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T41	1		T59	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T3	3		T4	2		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T34	1		T110	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	1		T35	11		T44	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	5		T30	1		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T35	1		T30	1		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T26	13		T122	13		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T45	14		T113	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T189	13		T218	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17139	1			T1	180		T2	1		T8	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T7	1		T223	1		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T152	4		T123	11		T36	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T139	10		T47	12		T119	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T116	2		T117	10		T158	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	10		T115	14		T132	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T60	1		T217	6		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	2		T59	25		T158	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	7		T58	4		T115	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	5		T152	2		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T119	6		T135	10		T202	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T123	3		T203	16		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T58	7		T116	10		T192	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	10		T41	14		T59	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	880	1			T3	26		T4	17		T6	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T119	6		T114	7		T124	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	9		T47	4		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T30	4		T112	11		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	12		T45	11		T122	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T122	12		T14	4		T213	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T45	11		T153	1		T220	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T218	6		T200	5		T211	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	10		T8	1		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T223	7		T144	2		T254	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T35	1		T45	14		T122	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T122	13		T165	1		T198	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T302	3		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T191	1		T144	7		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T2	1		T143	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T47	11		T109	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T116	1		T13	10		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T139	1		T47	12		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T117	11		T60	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T26	10		T45	3		T59	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	7		T115	1		T117	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	7		T152	3		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T119	1		T58	13		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	4		T123	1		T201	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T58	8		T116	1		T187	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	1		T41	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T112	1		T192	10		T189	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T34	1		T59	9		T114	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T3	3		T4	2		T5	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T44	5		T110	1		T119	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T35	11		T30	1		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T26	13		T30	1		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T45	11		T122	11		T153	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T122	12		T165	14		T198	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T302	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T191	1		T144	2		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	10		T152	4		T123	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T47	12		T109	17		T223	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T116	2		T13	6		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T139	10		T47	10		T119	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T117	10		T60	1		T158	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T45	2		T59	25		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	7		T115	12		T190	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	5		T152	2		T158	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T119	6		T58	4		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T123	3		T201	5		T203	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T58	7		T116	10		T187	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	10		T41	14		T192	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T192	7		T125	7		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T59	5		T114	7		T192	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	983	1			T3	26		T4	17		T6	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T119	6		T112	11		T38	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T35	9		T30	12		T45	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	4		T14	4		T213	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T152	5		T123	12		T36	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T139	11		T47	13		T119	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T116	3		T117	11		T158	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T26	1		T47	11		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T60	2		T217	7		T185	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T45	3		T59	27		T113	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	12		T58	5		T115	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	10		T152	3		T188	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	7		T135	11		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	1		T123	4		T203	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T58	8		T116	11		T192	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	11		T41	15		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T3	29		T4	19		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	1		T110	1		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T10	1		T35	10		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	1		T30	5		T112	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	1		T30	13		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	1		T122	13		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T45	12		T113	1		T153	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T189	1		T218	7		T200	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17261	1			T1	180		T2	11		T8	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T7	1		T223	8		T144	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T123	10		T36	3		T190	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	10		T119	6		T109	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T117	10		T120	4		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T26	9		T47	11		T132	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T217	11		T137	10		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	2		T59	24		T120	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	2		T58	12		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	2		T152	2		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T135	13		T209	8		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T12	3		T203	15		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T58	7		T192	9		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T59	8		T192	24		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T5	8		T24	5		T46	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T114	8		T124	16		T210	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	10		T44	6		T47	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T44	4		T226	7		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T45	11		T122	14		T118	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T26	12		T122	12		T14	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T45	13		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T189	12		T211	13		T230	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T282	16		T128	15		T316	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T144	6		T254	9		T257	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T35	1		T45	12		T122	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T122	13		T165	15		T198	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T302	7		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T191	2		T144	3		T222	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	11		T143	1		T152	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	1		T47	13		T109	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T116	3		T13	11		T169	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T139	11		T47	11		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T117	11		T60	2		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T26	1		T45	3		T59	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T8	12		T115	13		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	10		T152	3		T188	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T119	7		T58	5		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	1		T123	4		T201	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T58	8		T116	11		T187	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	11		T41	15		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T112	1		T192	8		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T34	1		T59	6		T114	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T3	29		T4	19		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T44	1		T110	1		T119	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	10		T30	13		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T26	1		T30	5		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T45	13		T122	14		T252	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T122	12		T198	2		T261	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T302	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T144	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T123	10		T36	3		T190	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	10		T109	18		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	5		T142	23		T145	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T47	11		T119	6		T132	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T117	10		T120	4		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T26	9		T45	2		T59	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	2		T117	4		T190	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	2		T152	2		T207	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T58	12		T38	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T12	3		T203	15		T213	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T58	7		T187	11		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T192	11		T153	7		T37	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T192	9		T189	4		T160	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T59	8		T114	8		T192	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T5	8		T44	6		T24	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T44	4		T210	13		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	10		T45	11		T118	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T26	12		T14	4		T213	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10