Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	11		T143	1		T152	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T7	1		T139	11		T47	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T116	3		T117	11		T158	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	11		T59	13		T109	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T60	2		T217	7		T185	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T26	1		T45	3		T59	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	12		T58	5		T152	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	10		T188	1		T201	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T119	7		T135	11		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T12	1		T123	4		T203	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T58	8		T116	11		T192	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	11		T41	15		T59	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T3	29		T4	19		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T34	1		T110	1		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T35	10		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T30	5		T112	12		T184	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T35	1		T30	13		T45	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T122	13		T36	1		T201	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T45	12		T113	1		T153	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T26	1		T184	1		T218	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T219	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T123	10		T36	3		T190	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T47	10		T119	6		T144	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T117	10		T120	4		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T47	11		T59	10		T109	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T217	11		T137	10		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	9		T45	2		T59	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	2		T58	12		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T12	2		T207	12		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T135	13		T209	8		T144	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	3		T203	15		T213	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T58	7		T192	9		T187	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T59	8		T192	24		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T5	8		T24	5		T46	31
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T114	8		T124	16		T225	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	10		T44	10		T117	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T226	7		T227	2		T228	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T45	11		T47	14		T122	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T122	12		T14	4		T213	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T45	13		T140	14		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T26	12		T211	13		T230	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T7	1		T191	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T2	11		T143	1		T116	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	13		T113	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	5		T123	12		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T139	11		T47	11		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T117	11		T60	2		T158	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T26	1		T45	3		T59	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T8	12		T152	3		T115	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	10		T188	1		T158	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T119	7		T58	5		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T12	1		T123	4		T201	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T58	8		T116	11		T187	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	11		T41	15		T59	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T112	1		T192	8		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	1		T110	1		T114	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T3	29		T4	19		T5	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T119	7		T112	12		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T35	11		T30	13		T45	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T26	1		T30	5		T122	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T216	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T142	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	3		T190	23		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	10		T144	6		T231	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T123	10		T13	5		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	11		T119	6		T59	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T117	10		T120	4		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	9		T45	2		T59	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	2		T152	2		T117	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	2		T187	13		T207	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T58	12		T38	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T12	3		T213	6		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T58	7		T187	11		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T59	8		T192	11		T203	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T192	9		T189	4		T160	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T114	8		T192	13		T124	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T5	8		T44	10		T24	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T206	11		T226	7		T227	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T35	10		T45	24		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T26	12		T122	12		T14	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10