Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22550

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3439

1

T2

11

T10

1

T12

12

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20341

1

T1

180

T2

22

T8

10

auto[1]

5648

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	53	1			T2	11		T35	20		T132	17
values[1]	859	1			T44	5		T12	4		T26	13
values[2]	817	1			T7	1		T34	1		T47	22
values[3]	692	1			T2	11		T139	11		T109	36
values[4]	2854	1			T3	29		T4	19		T5	9
values[5]	655	1			T41	15		T47	19		T114	16
values[6]	577	1			T35	1		T45	25		T120	7
values[7]	584	1			T30	13		T58	17		T143	1
values[8]	631	1			T8	14		T10	1		T119	7
values[9]	1086	1			T44	7		T45	5		T143	2
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1208	1			T35	20		T34	1		T44	5
values[1]	774	1			T7	1		T26	13		T47	22
values[2]	588	1			T2	11		T139	11		T116	3
values[3]	2856	1			T3	29		T4	19		T5	9
values[4]	708	1			T114	16		T121	29		T213	9
values[5]	535	1			T35	1		T30	13		T45	25
values[6]	428	1			T58	17		T143	1		T113	2
values[7]	801	1			T8	14		T10	1		T119	7
values[8]	733	1			T44	7		T45	5		T143	1
values[9]	166	1			T143	1		T190	25		T136	24
minimum	17192	1			T1	180		T2	11		T8	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T35	11		T34	1		T44	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T30	1		T110	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	1		T26	13		T59	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	12		T119	7		T112	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T124	17		T13	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T139	1		T116	1		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	7		T45	12		T119	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T213	7		T232	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T114	9		T121	17		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T35	1		T45	14		T120	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T30	1		T115	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T58	13		T118	9		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T143	1		T113	2		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	7		T58	8		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T10	1		T119	1		T59	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T44	7		T45	3		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T152	1		T192	14		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T190	13		T136	9		T233	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T143	1		T210	13		T234	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T2	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T35	9		T47	12		T186	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T30	4		T117	8		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T59	17		T152	2		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	10		T119	6		T112	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	10		T124	14		T13	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T139	10		T116	2		T122	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	5		T45	11		T119	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T213	2		T232	8		T205	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T114	7		T121	12		T194	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T45	11		T120	2		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T30	12		T115	12		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T58	4		T118	10		T158	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T123	3		T134	3		T223	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	7		T58	7		T116	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T119	6		T59	13		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	2		T115	12		T192	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T152	4		T192	2		T133	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T190	12		T136	15		T233	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T235	1		T236	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T2	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T35	11		T237	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T2	1		T132	3		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T44	5		T12	4		T26	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T30	1		T110	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T34	1		T59	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	12		T119	7		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T124	17		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T139	1		T109	19		T187	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T3	3		T4	2		T5	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	7		T45	12		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T41	1		T47	15		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T114	9		T121	17		T133	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	1		T45	14		T120	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T184	1		T141	1		T194	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T58	13		T118	9		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	1		T143	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	7		T58	8		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T119	1		T59	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T44	7		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T143	1		T152	1		T192	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T35	9		T237	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T2	10		T132	14		T232	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	12		T186	4		T192	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T30	4		T122	12		T153	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T59	17		T152	2		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	10		T119	6		T112	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T2	10		T124	14		T13	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T139	10		T109	17		T187	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T3	26		T4	17		T6	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	5		T45	11		T119	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T41	14		T47	4		T205	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T114	7		T121	12		T133	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T45	11		T120	2		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T141	15		T194	27		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T58	4		T118	10		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T30	12		T115	12		T123	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	7		T58	7		T116	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T119	6		T59	13		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T45	2		T115	12		T190	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T152	4		T192	2		T133	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T35	10		T34	1		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T30	5		T110	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T26	1		T59	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T47	11		T119	7		T112	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	11		T124	15		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	11		T116	3		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T12	10		T45	12		T119	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T213	3		T232	9		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T114	8		T121	13		T194	29
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T35	1		T45	12		T120	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T30	13		T115	13		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T58	5		T118	11		T158	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T143	1		T113	2		T123	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	12		T58	8		T116	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T119	7		T59	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T44	1		T45	3		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T152	5		T192	3		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T190	13		T136	16		T233	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T143	1		T210	1		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T2	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T35	10		T44	4		T12	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T117	10		T122	12		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T26	12		T59	18		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	11		T119	6		T109	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T124	16		T13	5		T135	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T122	14		T120	17		T145	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1134	1			T5	8		T24	5		T26	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	2		T45	11		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T213	6		T145	9		T205	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T114	8		T121	16		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	13		T120	4		T153	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T140	14		T207	12		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T58	12		T118	8		T207	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T140	14		T134	10		T208	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	2		T58	7		T125	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T59	14		T120	10		T125	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	6		T45	2		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T192	13		T133	18		T225	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T190	12		T136	8		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T210	12		T234	9		T239	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T35	10		T237	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T2	11		T132	15		T232	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T44	1		T12	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	5		T110	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T34	1		T59	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	11		T119	7		T112	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	11		T124	15		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T139	11		T109	18		T187	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T3	29		T4	19		T5	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T12	10		T45	12		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T41	15		T47	5		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T114	8		T121	13		T133	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T35	1		T45	12		T120	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T184	1		T141	16		T194	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T58	5		T118	11		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	13		T143	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	12		T58	8		T116	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T119	7		T59	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T44	1		T45	3		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T143	1		T152	5		T192	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T35	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T132	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T44	4		T12	3		T26	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T122	12		T153	9		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T59	18		T152	2		T117	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	11		T119	6		T117	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T124	16		T13	5		T190	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T109	18		T187	13		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1135	1			T5	8		T24	5		T26	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	2		T45	11		T123	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	14		T145	9		T205	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T114	8		T121	16		T133	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	13		T120	4		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T142	14		T16	2		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T58	12		T118	8		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T140	28		T134	10		T207	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T8	2		T58	7		T192	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T59	14		T120	10		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T44	6		T45	2		T190	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T192	13		T133	18		T137	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10