Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22417

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3572

1

T2

11

T8

14

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20193

1

T1

180

T2

22

T7

1

auto[1]

5796

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	13	1			T241	6		T242	7		-	-
values[0]	30	1			T243	13		T244	17		-	-
values[1]	661	1			T2	11		T10	1		T41	15
values[2]	2901	1			T3	29		T4	19		T5	9
values[3]	776	1			T35	21		T143	1		T113	1
values[4]	755	1			T8	14		T12	4		T26	23
values[5]	374	1			T12	12		T30	5		T45	5
values[6]	504	1			T109	36		T60	2		T192	24
values[7]	844	1			T119	7		T112	12		T143	1
values[8]	730	1			T2	11		T7	1		T34	1
values[9]	1220	1			T44	5		T30	13		T110	1
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	825	1			T2	11		T10	1		T41	15
values[1]	3048	1			T3	29		T4	19		T5	9
values[2]	685	1			T8	14		T12	4		T26	13
values[3]	615	1			T26	10		T119	20		T58	17
values[4]	494	1			T12	12		T30	5		T45	5
values[5]	530	1			T119	7		T192	41		T14	11
values[6]	765	1			T2	11		T7	1		T34	1
values[7]	754	1			T143	2		T152	5		T115	13
values[8]	835	1			T44	5		T30	13		T110	1
values[9]	243	1			T59	14		T114	1		T122	26
minimum	17195	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T2	1		T41	1		T44	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T122	13		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T3	3		T4	2		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T35	11		T58	8		T59	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	3		T192	14		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	7		T12	4		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T119	7		T58	13		T123	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T26	10		T119	1		T59	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	15		T158	1		T213	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T12	7		T30	1		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T119	1		T192	10		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T192	12		T14	7		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	1		T112	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T34	1		T109	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T143	1		T152	1		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T143	1		T115	1		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T110	1		T47	12		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T44	5		T30	1		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T122	15		T120	11		T205	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T59	9		T114	1		T140	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17066	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T2	10		T41	14		T47	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T122	12		T123	3		T13	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T3	26		T4	17		T6	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T35	9		T58	7		T59	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	2		T192	2		T124	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	7		T116	12		T133	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T119	6		T58	4		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T119	6		T59	12		T117	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T47	4		T158	6		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	5		T30	4		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T119	6		T192	7		T169	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T192	12		T14	4		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T112	11		T153	1		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	10		T109	17		T215	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T152	4		T36	3		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T115	12		T135	11		T202	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	10		T38	1		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T30	12		T45	11		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T122	11		T120	11		T205	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T59	5		T245	4		T246	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	1		T34	1		T70	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T241	4		T242	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T244	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T243	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	1		T41	1		T44	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T59	15		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T3	3		T4	2		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T58	8		T113	1		T120	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T35	1		T152	3		T114	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	11		T143	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T119	7		T58	13		T123	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	7		T12	4		T26	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	15		T158	1		T213	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	7		T30	1		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T207	13		T136	7		T144	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T109	19		T60	1		T192	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T119	1		T112	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T143	1		T14	7		T136	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T143	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	1		T34	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T110	1		T47	12		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	436	1			T44	5		T30	1		T45	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T241	2		T242	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T244	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T243	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	10		T41	14		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T59	13		T122	12		T123	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T3	26		T4	17		T6	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T58	7		T120	2		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	2		T114	7		T192	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T35	9		T116	12		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T119	6		T58	4		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	7		T119	6		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T47	4		T158	6		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	5		T30	4		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T136	5		T144	10		T137	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T109	17		T60	1		T192	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T119	6		T112	11		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T14	4		T136	2		T215	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T36	3		T172	8		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	10		T115	12		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T47	10		T122	11		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T30	12		T45	11		T139	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T2	11		T41	15		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	1		T122	13		T123	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T3	29		T4	19		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T35	10		T58	8		T59	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T152	3		T192	3		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	12		T12	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T119	7		T58	5		T123	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	1		T119	7		T59	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T47	5		T158	7		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	10		T30	5		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T119	7		T192	8		T169	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T192	13		T14	7		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T112	12		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	11		T34	1		T109	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T143	1		T152	5		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T143	1		T115	13		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T110	1		T47	11		T201	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T44	1		T30	13		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T122	12		T120	12		T205	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T59	6		T114	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17195	1			T1	180		T8	10		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	6		T47	10		T190	23
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T122	12		T13	5		T37	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T5	8		T24	5		T45	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	10		T58	7		T59	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T152	2		T192	13		T124	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	2		T12	3		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T119	6		T58	12		T123	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T26	9		T59	10		T117	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	14		T213	6		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	2		T45	2		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T192	9		T136	6		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T192	11		T14	4		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T38	1		T207	12		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T109	18		T215	3		T128	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	3		T172	9		T207	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T189	12		T135	11		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	11		T189	4		T135	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T44	4		T45	11		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T122	14		T120	10		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T59	8		T140	14		T247	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T241	6		T242	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T244	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T243	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T2	11		T41	15		T44	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	1		T59	14		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T3	29		T4	19		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T58	8		T113	1		T120	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T35	1		T152	3		T114	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	10		T143	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T119	7		T58	5		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	12		T12	1		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	5		T158	7		T213	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	10		T30	5		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T207	1		T136	6		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T109	18		T60	2		T192	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T119	7		T112	12		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T143	1		T14	7		T136	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	1		T143	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	11		T34	1		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T110	1		T47	11		T122	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	435	1			T44	1		T30	13		T45	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T242	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T244	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T44	6		T140	14		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T59	14		T122	12		T13	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T5	8		T24	5		T45	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T58	7		T120	4		T189	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	2		T114	8		T192	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	10		T120	17		T133	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T119	6		T58	12		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	2		T12	3		T26	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T47	14		T213	6		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	2		T45	2		T59	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T207	12		T136	6		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T109	18		T192	11		T132	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T192	9		T193	11		T210	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	4		T136	4		T215	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	3		T172	9		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T189	12		T135	11		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	11		T122	14		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T44	4		T45	11		T59	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10