Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21990

1

T1

180

T2

22

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3999

1

T35

1

T34

1

T44

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19915

1

T1

180

T8

24

T10

1

auto[1]

6074

1

T2

22

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T113	1		T248	9		-	-
values[0]	50	1			T115	3		T13	16		T233	8
values[1]	508	1			T34	1		T30	13		T59	14
values[2]	738	1			T26	13		T152	5		T116	3
values[3]	843	1			T8	14		T35	1		T47	23
values[4]	459	1			T2	11		T30	5		T45	5
values[5]	667	1			T58	15		T114	1		T115	13
values[6]	606	1			T7	1		T44	12		T12	4
values[7]	731	1			T12	12		T47	41		T59	23
values[8]	839	1			T2	11		T41	15		T35	20
values[9]	3357	1			T3	29		T4	19		T5	9
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T34	1		T30	13		T59	14
values[1]	715	1			T8	14		T26	13		T152	5
values[2]	674	1			T2	11		T35	1		T30	5
values[3]	644	1			T45	5		T58	17		T132	23
values[4]	515	1			T58	15		T143	1		T114	1
values[5]	835	1			T7	1		T44	12		T12	4
values[6]	2939	1			T3	29		T4	19		T5	9
values[7]	700	1			T2	11		T41	15		T26	10
values[8]	856	1			T10	1		T35	20		T110	1
values[9]	125	1			T132	5		T37	7		T185	1
minimum	17201	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T59	9		T152	3		T115	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T34	1		T30	1		T120	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	7		T116	1		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T26	13		T152	1		T122	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	1		T30	1		T114	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	1		T47	11		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	3		T136	7		T210	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T58	13		T132	11		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T143	1		T36	1		T201	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T58	8		T114	1		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	1		T44	5		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T44	7		T12	4		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1522	1			T3	3		T4	2		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T47	12		T59	15		T143	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T2	1		T41	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T26	10		T117	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T35	11		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T110	1		T45	14		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T132	1		T249	1		T250	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T37	5		T185	1		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17071	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T213	7		T252	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T59	5		T152	2		T115	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T30	12		T120	11		T203	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	7		T116	2		T117	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T152	4		T122	11		T60	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T2	10		T30	4		T114	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	12		T119	6		T192	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T45	2		T136	5		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T58	4		T132	12		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T201	5		T153	7		T32	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T58	7		T116	10		T190	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T186	4		T38	1		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T45	11		T47	4		T59	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T3	26		T4	17		T6	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	10		T59	13		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	10		T41	14		T119	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	8		T158	6		T169	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T35	9		T139	10		T119	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	11		T187	12		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T132	4		T249	4		T250	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T37	2		T251	5		T254	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T213	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T113	1		T248	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T115	1		T13	10		T168	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T233	1		T252	1		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	9		T152	3		T153	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T34	1		T30	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T116	1		T117	11		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T26	13		T152	1		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	7		T114	9		T36	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T35	1		T47	11		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	1		T30	1		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T119	7		T58	13		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T36	1		T201	1		T153	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T58	8		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	1		T44	5		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T44	7		T12	4		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	7		T118	9		T213	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T47	27		T59	11		T109	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T41	1		T35	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T26	10		T59	15		T143	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1647	1			T3	3		T4	2		T5	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T110	1		T45	14		T187	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T115	2		T13	6		T256	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T233	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T59	5		T152	2		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	12		T120	11		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T116	2		T117	10		T158	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T152	4		T122	11		T60	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	7		T114	7		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T47	12		T192	12		T121	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T2	10		T30	4		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T119	6		T58	4		T132	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T201	5		T153	7		T257	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T58	7		T115	12		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T186	4		T218	6		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T45	11		T115	12		T123	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	5		T118	10		T213	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	14		T59	12		T109	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	10		T41	14		T35	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T59	13		T117	8		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T3	26		T4	17		T6	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T45	11		T187	12		T37	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T59	6		T152	3		T115	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T34	1		T30	13		T120	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	12		T116	3		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	1		T152	5		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	11		T30	5		T114	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	1		T47	13		T119	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T45	3		T136	6		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T58	5		T132	13		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T143	1		T36	1		T201	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T58	8		T114	1		T116	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	1		T44	1		T186	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T44	1		T12	1		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T3	29		T4	19		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T47	11		T59	14		T143	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	11		T41	15		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T26	1		T117	9		T158	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T10	1		T35	10		T139	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T110	1		T45	12		T113	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T132	5		T249	5		T250	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T37	5		T185	1		T251	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17187	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T213	3		T252	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T59	8		T152	2		T120	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T120	10		T203	15		T193	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	2		T117	10		T36	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	12		T122	14		T120	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T114	8		T217	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	10		T119	6		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	2		T136	6		T210	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	12		T132	10		T189	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T153	7		T32	16		T140	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T58	7		T190	12		T132	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T44	4		T142	14		T145	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T44	6		T12	3		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T5	8		T12	2		T24	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T47	11		T59	14		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	4		T212	8		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T26	9		T117	10		T140	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T35	10		T38	1		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T45	13		T187	11		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T250	9		T258	1		T259	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T37	2		T260	20		T261	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T256	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T213	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T113	1		T248	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T115	3		T13	11		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T233	8		T252	1		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T59	6		T152	3		T153	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	1		T30	13		T120	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T116	3		T117	11		T158	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T26	1		T152	5		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	12		T114	8		T36	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T35	1		T47	13		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	11		T30	5		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T119	7		T58	5		T184	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	1		T201	6		T153	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T58	8		T114	1		T115	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	1		T44	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T44	1		T12	1		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	10		T118	11		T213	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T47	16		T59	13		T109	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	11		T41	15		T35	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T26	1		T59	14		T143	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T3	29		T4	19		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T110	1		T45	12		T187	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T248	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T13	5		T168	3		T256	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T262	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T59	8		T152	2		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T120	10		T213	6		T193	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T117	10		T120	17		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T26	12		T122	14		T120	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	2		T114	8		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T47	10		T117	4		T192	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T45	2		T217	11		T32	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T119	6		T58	12		T132	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T153	7		T207	7		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T58	7		T190	12		T132	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T44	4		T140	14		T145	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	6		T12	3		T45	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	2		T118	8		T213	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	25		T59	10		T109	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T35	10		T206	11		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	9		T59	14		T117	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T5	8		T24	5		T46	31
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T45	13		T187	11		T37	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10