Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22095

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3894

1

T2

11

T35

1

T34

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20003

1

T1

180

T2

11

T8

24

auto[1]

5986

1

T2

11

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T113	1		T132	5		T202	1
values[0]	15	1			T233	8		T262	7		-	-
values[1]	604	1			T34	1		T30	13		T59	14
values[2]	668	1			T26	13		T152	5		T116	3
values[3]	795	1			T8	14		T35	1		T47	23
values[4]	546	1			T2	11		T30	5		T45	5
values[5]	647	1			T58	15		T143	1		T114	1
values[6]	574	1			T7	1		T44	12		T12	4
values[7]	712	1			T12	12		T47	41		T59	23
values[8]	948	1			T2	11		T41	15		T26	10
values[9]	3094	1			T3	29		T4	19		T5	9
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T34	1		T59	14		T115	3
values[1]	732	1			T8	14		T35	1		T26	13
values[2]	613	1			T2	11		T30	5		T47	23
values[3]	657	1			T45	5		T58	17		T132	23
values[4]	545	1			T58	15		T143	1		T114	1
values[5]	789	1			T7	1		T44	12		T12	4
values[6]	2930	1			T3	29		T4	19		T5	9
values[7]	671	1			T2	11		T41	15		T26	10
values[8]	952	1			T10	1		T35	20		T110	1
values[9]	99	1			T132	5		T37	7		T185	1
minimum	17364	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T59	9		T115	1		T120	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T34	1		T120	11		T203	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	7		T116	1		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T35	1		T26	13		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	1		T30	1		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	11		T112	1		T114	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T45	3		T39	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T58	13		T132	11		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	1		T36	1		T201	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T58	8		T114	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T44	5		T186	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T44	7		T12	4		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T3	3		T4	2		T5	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T47	12		T59	15		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	1		T119	1		T112	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T26	10		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T10	1		T35	11		T119	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T110	1		T45	14		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T37	5		T258	2		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T132	1		T185	1		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17112	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T30	1		T213	7		T193	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T59	5		T115	2		T120	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T120	11		T203	16		T32	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	7		T116	2		T117	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T152	4		T122	11		T60	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T2	10		T30	4		T119	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	12		T114	7		T192	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T45	2		T136	5		T253	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T58	4		T132	12		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T201	5		T153	7		T32	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T58	7		T115	12		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T186	4		T38	1		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T45	11		T59	12		T109	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	874	1			T3	26		T4	17		T6	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T47	10		T59	13		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T41	14		T119	6		T112	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	10		T117	8		T158	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T35	9		T119	6		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T45	11		T139	10		T187	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T37	2		T221	13		T157	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T132	4		T251	5		T260	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T8	1		T34	1		T152	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T30	12		T213	2		T193	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T202	1		T263	1		T264	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T113	1		T132	1		T215	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T233	1		T262	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T59	9		T152	3		T115	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	1		T30	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T116	1		T117	11		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T26	13		T152	1		T122	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	7		T36	5		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T35	1		T47	11		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T30	1		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T58	13		T132	11		T189	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T143	1		T36	1		T201	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T58	8		T114	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T44	5		T186	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	7		T12	4		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	7		T47	15		T118	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T47	12		T59	11		T109	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	1		T119	1		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T2	1		T26	10		T59	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1606	1			T3	3		T4	2		T5	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T110	1		T45	14		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T264	12		T265	9		T234	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T132	4		T215	3		T197	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T233	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T59	5		T152	2		T115	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	12		T120	11		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T116	2		T117	10		T158	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T152	4		T122	11		T60	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	7		T36	3		T217	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	12		T114	7		T192	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T2	10		T30	4		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T58	4		T132	12		T194	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T201	5		T153	7		T266	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T58	7		T115	12		T116	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T186	4		T218	6		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T45	11		T115	12		T123	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	5		T47	4		T118	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T47	10		T59	12		T109	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T41	14		T119	6		T14	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T2	10		T59	13		T117	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T3	26		T4	17		T6	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T45	11		T139	10		T187	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	6		T115	3		T120	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	1		T120	12		T203	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	12		T116	3		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T35	1		T26	1		T152	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T2	11		T30	5		T119	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T47	13		T112	1		T114	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T45	3		T39	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T58	5		T132	13		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T143	1		T36	1		T201	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T58	8		T114	1		T115	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	1		T44	1		T186	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T44	1		T12	1		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T3	29		T4	19		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T47	11		T59	14		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	15		T119	7		T112	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	11		T26	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T10	1		T35	10		T119	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T110	1		T45	12		T139	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T37	5		T258	1		T221	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T132	5		T185	1		T251	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17193	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T30	13		T213	3		T193	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T59	8		T120	17		T13	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T120	10		T203	15		T138	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	2		T117	10		T120	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T26	12		T122	14		T192	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T119	6		T217	11		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	10		T114	8		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	2		T136	6		T210	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T58	12		T132	10		T189	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T153	7		T32	16		T140	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T58	7		T190	12		T132	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T44	4		T145	13		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	6		T12	3		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T5	8		T12	2		T24	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T47	11		T59	14		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	4		T212	8		T231	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	9		T117	10		T140	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T35	10		T38	1		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T45	13		T187	11		T133	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T37	2		T258	1		T157	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T260	20		T261	3		T267	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T152	2		T240	8		T168	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T213	6		T193	11		T198	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T202	1		T263	1		T264	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T113	1		T132	5		T215	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	8		T262	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T59	6		T152	3		T115	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T34	1		T30	13		T120	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T116	3		T117	11		T158	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	1		T152	5		T122	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	12		T36	5		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T35	1		T47	13		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	11		T30	5		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T58	5		T132	13		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	1		T36	1		T201	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T58	8		T114	1		T115	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	1		T44	1		T186	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T44	1		T12	1		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	10		T47	5		T118	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T47	11		T59	13		T109	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T41	15		T119	7		T113	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T2	11		T26	1		T59	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T3	29		T4	19		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T110	1		T45	12		T139	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T264	9		T268	16		T265	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T215	3		T197	10		T269	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T262	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T59	8		T152	2		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T120	10		T213	6		T193	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T117	10		T120	21		T133	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	12		T122	14		T192	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T8	2		T36	3		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T47	10		T114	8		T117	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T45	2		T119	6		T32	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T58	12		T132	10		T189	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T153	7		T140	14		T207	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T58	7		T190	12		T132	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T44	4		T145	13		T208	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T44	6		T12	3		T45	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	2		T47	14		T118	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	11		T59	10		T109	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	4		T212	8		T231	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T26	9		T59	14		T117	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1247	1			T5	8		T35	10		T24	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	13		T187	11		T133	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10