Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22440

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3549

1

T2

11

T8

14

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20170

1

T1

180

T2

22

T7

1

auto[1]

5819

1

T3

29

T4

19

T5

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	226	1			T44	5		T110	1		T45	23
values[0]	17	1			T244	17		-	-		-	-
values[1]	646	1			T2	11		T10	1		T41	15
values[2]	2926	1			T3	29		T4	19		T5	9
values[3]	743	1			T35	20		T143	1		T113	1
values[4]	788	1			T8	14		T12	4		T26	23
values[5]	435	1			T12	12		T30	5		T45	5
values[6]	411	1			T60	2		T192	41		T184	1
values[7]	871	1			T119	7		T112	12		T109	36
values[8]	700	1			T2	11		T7	1		T34	1
values[9]	1045	1			T30	13		T139	11		T47	22
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	608	1			T2	11		T10	1		T41	15
values[1]	3043	1			T3	29		T4	19		T5	9
values[2]	741	1			T8	14		T12	4		T26	13
values[3]	613	1			T26	10		T119	20		T58	17
values[4]	495	1			T12	12		T30	5		T45	5
values[5]	547	1			T109	36		T60	2		T192	41
values[6]	778	1			T2	11		T7	1		T34	1
values[7]	720	1			T143	1		T115	13		T36	8
values[8]	988	1			T44	5		T30	13		T110	1
values[9]	87	1			T59	14		T114	1		T245	5
minimum	17369	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T41	1		T44	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	1		T59	15		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T3	3		T4	2		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T35	11		T58	8		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T152	3		T192	14		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	7		T12	4		T26	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T119	7		T58	13		T123	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	10		T119	1		T59	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T47	15		T158	1		T213	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	7		T30	1		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T192	10		T169	1		T136	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T109	19		T60	1		T192	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T7	1		T119	1		T112	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T34	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T143	1		T36	5		T172	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T115	1		T189	13		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T110	1		T47	12		T122	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T44	5		T30	1		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T205	3		T147	1		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T59	9		T114	1		T245	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17105	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T123	1		T160	4		T270	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	10		T41	14		T186	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T59	13		T122	12		T13	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T3	26		T4	17		T6	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T35	9		T58	7		T120	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T152	2		T192	2		T124	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	7		T116	12		T133	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T119	6		T58	4		T123	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T119	6		T59	12		T117	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T47	4		T158	6		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	5		T30	4		T45	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T192	7		T169	11		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T109	17		T60	1		T192	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T119	6		T112	11		T152	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	10		T215	3		T128	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	3		T172	8		T132	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T115	12		T135	11		T202	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	10		T122	11		T120	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T30	12		T45	11		T139	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T205	12		T254	1		T271	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T59	5		T245	4		T222	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T123	3		T160	2		T220	19

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T110	1		T214	7		T254	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T44	5		T45	12		T115	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T244	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	1		T41	1		T140	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	1		T59	15		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T3	3		T4	2		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T58	8		T120	5		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T152	3		T192	14		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T35	11		T143	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T119	7		T58	13		T123	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	7		T12	4		T26	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T47	15		T158	1		T213	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	7		T30	1		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T192	10		T169	1		T136	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T60	1		T192	12		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T119	1		T112	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T109	19		T143	1		T14	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T143	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T34	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	12		T122	15		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T30	1		T139	1		T59	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T254	1		T271	16		T242	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T45	11		T115	14		T211	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T244	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	10		T41	14		T134	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T59	13		T122	12		T123	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T3	26		T4	17		T6	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T58	7		T120	2		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	2		T192	2		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	9		T116	12		T133	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T119	6		T58	4		T123	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	7		T119	6		T59	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T47	4		T158	6		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T12	5		T30	4		T45	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T192	7		T169	11		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T60	1		T192	12		T132	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T119	6		T112	11		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T109	17		T14	4		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T36	3		T172	8		T132	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	10		T115	12		T135	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T47	10		T122	11		T120	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T30	12		T139	10		T59	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	11		T41	15		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T59	14		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T3	29		T4	19		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T35	10		T58	8		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T152	3		T192	3		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	12		T12	1		T26	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T119	7		T58	5		T123	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T26	1		T119	7		T59	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T47	5		T158	7		T213	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	10		T30	5		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T192	8		T169	12		T136	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T109	18		T60	2		T192	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	1		T119	7		T112	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	11		T34	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T143	1		T36	5		T172	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T115	13		T189	1		T135	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T110	1		T47	11		T122	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T44	1		T30	13		T45	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T205	13		T147	1		T254	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T59	6		T114	1		T245	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17265	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T123	4		T160	4		T270	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	6		T140	14		T134	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T59	14		T122	12		T13	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T5	8		T24	5		T45	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T35	10		T58	7		T120	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	2		T192	13		T124	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	2		T12	3		T26	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T119	6		T58	12		T123	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	9		T59	10		T117	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T47	14		T213	6		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	2		T45	2		T117	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T192	9		T136	6		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T109	18		T192	11		T14	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T207	12		T193	11		T212	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T215	3		T128	12		T240	26
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	3		T172	9		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T189	12		T135	11		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	11		T122	14		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T44	4		T45	11		T140	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T205	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T59	8		T268	16		T248	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T231	4		T206	11		T272	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T160	2		T220	19		T273	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T110	1		T214	1		T254	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T44	1		T45	12		T115	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T244	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	11		T41	15		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	1		T59	14		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T3	29		T4	19		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T58	8		T120	3		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T152	3		T192	3		T36	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T35	10		T143	1		T113	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T119	7		T58	5		T123	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	12		T12	1		T26	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T47	5		T158	7		T213	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	10		T30	5		T45	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T192	8		T169	12		T136	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T60	2		T192	13		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T119	7		T112	12		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T109	18		T143	1		T14	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	1		T143	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	11		T34	1		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T47	11		T122	12		T120	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T30	13		T139	11		T59	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T214	6		T242	3		T274	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T44	4		T45	11		T145	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T244	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	14		T134	10		T125	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T59	14		T122	12		T13	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T5	8		T44	6		T24	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T58	7		T120	4		T189	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	2		T192	13		T124	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T35	10		T133	18		T205	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T119	6		T58	12		T123	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	2		T12	3		T26	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T47	14		T213	6		T142	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	2		T45	2		T117	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T192	9		T136	6		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T192	11		T132	10		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T207	12		T193	11		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T109	18		T14	4		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	3		T172	9		T38	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T189	12		T135	11		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	11		T122	14		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T59	8		T140	14		T136	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10