Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23146

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

2843

1

T2

11

T34

1

T12

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20204

1

T1

180

T2

11

T7

1

auto[1]

5785

1

T2

11

T3

29

T4

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	58	1			T44	5		T208	20		T275	27
values[0]	24	1			T141	16		T262	8		-	-
values[1]	619	1			T12	12		T47	22		T119	7
values[2]	640	1			T2	11		T35	21		T45	5
values[3]	532	1			T8	14		T45	23		T143	1
values[4]	842	1			T119	13		T143	1		T113	1
values[5]	2987	1			T3	29		T4	19		T5	9
values[6]	658	1			T26	10		T30	13		T47	23
values[7]	690	1			T2	11		T41	15		T44	7
values[8]	623	1			T119	7		T143	1		T114	16
values[9]	1135	1			T7	1		T10	1		T12	4
minimum	17181	1			T1	180		T8	10		T35	185

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	772	1			T2	11		T35	20		T47	22
values[1]	731	1			T12	12		T45	5		T47	19
values[2]	475	1			T8	14		T35	1		T45	23
values[3]	3014	1			T3	29		T4	19		T5	9
values[4]	813	1			T34	1		T26	13		T30	5
values[5]	608	1			T2	11		T41	15		T26	10
values[6]	640	1			T44	7		T158	3		T192	40
values[7]	679	1			T7	1		T10	1		T119	7
values[8]	867	1			T12	4		T58	17		T59	23
values[9]	179	1			T44	5		T45	25		T112	12
minimum	17211	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T35	11		T47	12		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T116	1		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T45	3		T47	15		T119	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	7		T123	1		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	7		T35	1		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T119	7		T143	1		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T3	3		T4	2		T5	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T110	1		T115	1		T186	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T26	13		T30	1		T58	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T34	1		T123	11		T190	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T41	1		T26	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T60	1		T13	10		T125	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T44	7		T192	26		T190	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T158	1		T207	8		T209	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	1		T10	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T59	9		T143	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T58	13		T59	11		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T12	4		T114	1		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T44	5		T112	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T45	14		T115	1		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T141	1		T259	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T35	9		T47	10		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	10		T116	10		T117	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T45	2		T47	4		T119	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	5		T123	3		T187	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	7		T45	11		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T119	6		T245	4		T276	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T3	26		T4	17		T6	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T115	12		T186	4		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T30	4		T58	7		T109	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T123	11		T190	19		T187	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	10		T41	14		T30	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T60	1		T13	6		T125	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T192	14		T190	12		T134	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T158	2		T223	7		T194	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T119	6		T59	13		T165	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T59	5		T213	7		T232	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T58	4		T59	12		T152	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T115	12		T117	8		T203	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T112	11		T146	14		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T45	11		T115	2		T218	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T141	15		T259	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T44	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T208	11		T275	12		T157	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T262	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T141	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T47	12		T119	1		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	7		T132	3		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T35	12		T45	3		T47	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	1		T116	1		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	7		T45	12		T117	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T143	1		T113	1		T187	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T143	1		T122	15		T121	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T119	7		T113	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T3	3		T4	2		T5	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T34	1		T110	1		T123	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T26	10		T30	1		T47	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T132	1		T193	12		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	1		T41	1		T44	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T60	1		T158	1		T13	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T119	1		T114	9		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T143	1		T188	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	1		T10	1		T58	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T12	4		T45	14		T59	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T1	180		T8	9		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T208	9		T275	15		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T141	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	10		T119	6		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	5		T132	14		T125	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	9		T45	2		T47	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	10		T116	10		T117	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	7		T45	11		T128	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T187	12		T169	11		T202	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T122	11		T121	12		T217	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T119	6		T115	12		T186	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1002	1			T3	26		T4	17		T6	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T123	11		T190	19		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T30	12		T47	12		T109	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T132	4		T193	11		T205	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	10		T41	14		T139	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T60	1		T158	2		T13	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T119	6		T114	7		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T232	2		T32	17		T191	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T58	4		T59	25		T112	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	11		T59	5		T115	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T35	10		T47	11		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	11		T116	11		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	3		T47	5		T119	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	10		T123	4		T187	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	12		T35	1		T45	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T119	7		T143	1		T113	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T3	29		T4	19		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T110	1		T115	13		T186	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T26	1		T30	5		T58	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T34	1		T123	12		T190	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	11		T41	15		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	2		T13	11		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T44	1		T192	16		T190	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T158	3		T207	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T10	1		T119	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T59	6		T143	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T58	5		T59	13		T152	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T12	1		T114	1		T115	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T44	1		T112	12		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T45	12		T115	3		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T141	16		T259	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	10		T47	11		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T117	10		T132	2		T210	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	2		T47	14		T117	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	2		T187	11		T172	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	2		T45	11		T121	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T119	6		T225	1		T276	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T5	8		T24	5		T46	31
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T135	13		T205	2		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T26	12		T58	7		T109	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T123	10		T190	23		T187	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	9		T47	10		T120	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T13	5		T125	3		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	6		T192	24		T190	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T207	7		T209	8		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T59	14		T207	12		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T59	8		T213	11		T32	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T58	12		T59	10		T114	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T12	3		T117	10		T203	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T44	4		T146	11		T277	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T45	13		T278	22		T257	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T259	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T44	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T208	10		T275	16		T157	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T262	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	11		T119	7		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	10		T132	15		T125	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T35	11		T45	3		T47	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	11		T116	11		T117	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	12		T45	12		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	1		T113	1		T187	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T143	1		T122	12		T121	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T119	7		T113	1		T115	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T3	29		T4	19		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	1		T110	1		T123	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T26	1		T30	13		T47	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T132	5		T193	12		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	11		T41	15		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T60	2		T158	3		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T119	7		T114	8		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T143	1		T188	1		T232	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T7	1		T10	1		T58	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T12	1		T45	12		T59	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	180		T8	10		T35	185
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T44	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T208	10		T275	11		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T262	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	11		T152	2		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T12	2		T132	2		T210	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T35	10		T45	2		T47	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T117	10		T172	9		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	2		T45	11		T117	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T187	11		T210	13		T276	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T122	14		T121	16		T217	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T119	6		T140	14		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T5	8		T24	5		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T123	10		T190	23		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T26	9		T47	10		T109	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T193	11		T142	10		T138	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	6		T192	33		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	5		T213	11		T125	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T114	8		T207	12		T136	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T32	16		T214	2		T279	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T58	12		T59	24		T118	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	3		T45	13		T59	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10