Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25989

1

T1

180

T2

22

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22373

1

T1

180

T2

11

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T2

11

T35

1

T34

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19857

1

T1

178

T7

1

T8

24

auto[1]

6132

1

T1

2

T2

22

T3

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22159

1

T1

180

T2

2

T3

3

auto[1]

3830

1

T2

20

T3

26

T4

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	608	1			T1	2		T35	7		T34	2
values[0]	22	1			T19	20		T280	1		T281	1
values[1]	526	1			T30	13		T45	5		T113	1
values[2]	2955	1			T3	29		T4	19		T5	9
values[3]	682	1			T35	1		T44	5		T58	15
values[4]	673	1			T2	11		T34	1		T139	11
values[5]	783	1			T35	20		T47	22		T143	1
values[6]	816	1			T8	14		T44	7		T30	5
values[7]	693	1			T41	15		T12	4		T26	13
values[8]	513	1			T7	1		T10	1		T12	12
values[9]	914	1			T2	11		T143	1		T113	1
minimum	16804	1			T1	178		T8	10		T35	178

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T30	13		T45	28		T115	13
values[1]	2881	1			T3	29		T4	19		T5	9
values[2]	626	1			T139	11		T59	23		T109	36
values[3]	770	1			T2	11		T34	1		T47	42
values[4]	897	1			T35	20		T30	5		T45	25
values[5]	646	1			T8	14		T44	7		T12	4
values[6]	698	1			T7	1		T41	15		T26	13
values[7]	437	1			T10	1		T12	12		T119	7
values[8]	903	1			T2	11		T113	1		T152	5
values[9]	166	1			T114	16		T120	29		T37	7
minimum	17350	1			T1	180		T8	10		T35	185

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

4057

1

T5

8

T8

2

T35

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T30	1		T45	12		T13	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	3		T115	1		T117	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1552	1			T3	3		T4	2		T5	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T35	1		T113	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T59	11		T109	19		T118	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T139	1		T135	12		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T2	1		T47	26		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T34	1		T119	7		T59	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	11		T30	1		T47	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T45	14		T143	1		T60	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	7		T44	7		T12	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T112	1		T152	1		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T41	1		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T158	1		T172	10		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T10	1		T12	7		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T119	1		T112	1		T189	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T188	1		T122	15		T192	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T113	1		T152	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T37	5		T140	1		T276	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T114	9		T120	18		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17077	1			T1	180		T8	9		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T113	1		T184	1		T189	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T30	12		T45	11		T13	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	2		T115	12		T117	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	907	1			T3	26		T4	17		T6	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T213	2		T191	1		T223	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T59	12		T109	17		T118	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T139	10		T135	11		T194	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	10		T47	16		T201	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T119	6		T59	13		T122	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	9		T30	4		T47	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T45	11		T60	1		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	7		T59	5		T116	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T112	11		T152	4		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T41	14		T115	14		T116	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T158	6		T172	8		T14	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	5		T121	12		T133	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T119	6		T282	1		T218	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T122	11		T192	12		T132	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T2	10		T152	2		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T37	2		T276	6		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T114	7		T120	11		T232	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T34	1		T70	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T170	9		T283	4		T284	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T1	2		T35	7		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T152	3		T120	18		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T19	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T280	1		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T30	1		T13	10		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	3		T113	1		T117	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T3	3		T4	2		T5	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T113	1		T114	1		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T44	5		T58	8		T59	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T35	1		T213	7		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	1		T47	26		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T34	1		T139	1		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	11		T47	12		T117	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T143	1		T122	13		T60	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	7		T44	7		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	14		T112	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T41	1		T12	4		T26	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	1		T202	1		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T10	1		T12	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T119	1		T112	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T143	1		T188	1		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T2	1		T113	1		T114	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16688	1			T1	178		T8	9		T35	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T135	10		T146	1		T17	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T152	2		T120	11		T232	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T19	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T30	12		T13	6		T169	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	2		T117	8		T136	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T3	26		T4	17		T6	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T115	12		T153	1		T191	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T58	7		T59	12		T109	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T213	2		T135	11		T194	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	10		T47	16		T201	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T139	10		T119	6		T59	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T35	9		T47	10		T198	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T122	12		T60	1		T123	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	7		T30	4		T58	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T45	11		T112	11		T152	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	14		T115	14		T116	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T38	1		T202	12		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	5		T121	12		T133	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T119	6		T158	6		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T122	11		T192	12		T132	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	10		T114	7		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T34	1		T70	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	13		T45	12		T13	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	3		T115	13		T117	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T3	29		T4	19		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	1		T113	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T59	13		T109	18		T118	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T139	11		T135	12		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	11		T47	18		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T34	1		T119	7		T59	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	10		T30	5		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T45	12		T143	1		T60	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	12		T44	1		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T112	12		T152	5		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T41	15		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T158	7		T172	9		T14	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	1		T12	10		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T119	7		T112	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T188	1		T122	12		T192	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	11		T113	1		T152	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T37	5		T140	1		T276	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T114	8		T120	12		T232	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17210	1			T1	180		T8	10		T35	185
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T113	1		T184	1		T189	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T45	11		T13	5		T144	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	2		T117	10		T140	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T5	8		T44	4		T24	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T213	6		T128	23		T206	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T59	10		T109	18		T118	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T135	11		T145	13		T210	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	24		T190	12		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T119	6		T59	14		T122	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T35	10		T47	11		T58	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T45	13		T120	10		T192	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	2		T44	6		T12	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T153	7		T205	1		T214	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T26	12		T120	4		T210	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T172	9		T14	4		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T12	2		T121	16		T133	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T189	12		T207	12		T210	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T122	14		T192	11		T132	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T152	2		T192	13		T36	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T37	2		T276	3		T160	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T114	8		T120	17		T240	26
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T285	2		T19	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T189	8		T284	21		T286	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	432	1			T1	2		T35	7		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T152	3		T120	12		T232	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T19	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T280	1		T281	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T30	13		T13	11		T169	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	3		T113	1		T117	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T3	29		T4	19		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T113	1		T114	1		T115	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T44	1		T58	8		T59	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	1		T213	3		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	11		T47	18		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T34	1		T139	11		T119	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	10		T47	11		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T143	1		T122	13		T60	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	12		T44	1		T30	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T45	12		T112	12		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T41	15		T12	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T38	2		T202	13		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	1		T10	1		T12	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T119	7		T112	1		T158	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T143	1		T188	1		T122	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	11		T113	1		T114	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16804	1			T1	178		T8	10		T35	178
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T207	7		T135	13		T276	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T152	2		T120	17		T146	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T19	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T13	5		T144	8		T15	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T45	2		T117	10		T189	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T5	8		T24	5		T26	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T140	14		T128	15		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	4		T58	7		T59	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T213	6		T135	11		T210	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T47	24		T190	12		T217	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T119	6		T59	14		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T35	10		T47	11		T117	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T122	12		T123	10		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	2		T44	6		T58	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T45	13		T187	13		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	3		T26	12		T120	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T137	10		T205	1		T206	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T12	2		T121	16		T133	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T172	9		T14	4		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T122	14		T192	11		T132	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T114	8		T192	13		T36	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21932

1

T1

180

T2

22

T3

29

auto[1]

auto[0]

4057

1

T5

8

T8

2

T35

10