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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.07 96.67 100.00 100.00 98.83 98.33 91.17


Total test records in report: 903
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T790 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3608073130 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:12 PM PDT 24 520442513 ps
T89 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3816806451 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:17 PM PDT 24 399588349 ps
T78 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.984778787 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:16 PM PDT 24 588744557 ps
T67 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1481562246 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:17 PM PDT 24 684876435 ps
T91 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3053768379 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:09 PM PDT 24 554054230 ps
T55 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1198115787 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:20 PM PDT 24 4460506087 ps
T62 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1577032920 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:07 PM PDT 24 9973609451 ps
T56 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.436824749 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:18 PM PDT 24 4981879117 ps
T92 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3955098567 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:12 PM PDT 24 563226455 ps
T75 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2677183162 Mar 17 12:59:07 PM PDT 24 Mar 17 12:59:09 PM PDT 24 474246498 ps
T71 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1978918842 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 384870502 ps
T90 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1836582710 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 490454709 ps
T63 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.522674610 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:25 PM PDT 24 8746847487 ps
T79 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.953267587 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:11 PM PDT 24 639514326 ps
T791 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4011049921 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:07 PM PDT 24 584838089 ps
T107 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.921503506 Mar 17 12:59:06 PM PDT 24 Mar 17 01:00:38 PM PDT 24 26531832267 ps
T319 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3566219687 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:12 PM PDT 24 4469696667 ps
T104 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.528243482 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:22 PM PDT 24 2385461089 ps
T108 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2704312976 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:13 PM PDT 24 499489154 ps
T68 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3196159780 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:19 PM PDT 24 554663954 ps
T76 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.414608132 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:25 PM PDT 24 667487521 ps
T320 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3264759907 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:16 PM PDT 24 4440395935 ps
T105 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2229046764 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:23 PM PDT 24 5014517694 ps
T106 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4190407615 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:16 PM PDT 24 2362087496 ps
T93 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1128580119 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:18 PM PDT 24 5436577728 ps
T94 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2520397960 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:03 PM PDT 24 335188643 ps
T792 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2768416496 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 456231819 ps
T95 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.184398851 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 362673986 ps
T793 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1645218575 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:24 PM PDT 24 443174448 ps
T96 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2658355629 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:19 PM PDT 24 473956782 ps
T97 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.36608965 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:44 PM PDT 24 25246209314 ps
T794 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3325704786 Mar 17 12:59:17 PM PDT 24 Mar 17 12:59:18 PM PDT 24 390090590 ps
T795 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3699382939 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:06 PM PDT 24 1181725954 ps
T796 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2018593507 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:36 PM PDT 24 52525723844 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2486581386 Mar 17 12:59:19 PM PDT 24 Mar 17 12:59:22 PM PDT 24 516840082 ps
T797 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3558849388 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:26 PM PDT 24 400867319 ps
T798 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2906163479 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:18 PM PDT 24 406929184 ps
T799 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1119050526 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:17 PM PDT 24 2399288235 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.711346247 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:25 PM PDT 24 906960784 ps
T800 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2623139611 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:15 PM PDT 24 2575333021 ps
T80 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.467013014 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:18 PM PDT 24 8686298173 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2442359142 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:24 PM PDT 24 399386280 ps
T802 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.572592760 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:16 PM PDT 24 312905991 ps
T98 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.293720256 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:18 PM PDT 24 404857278 ps
T99 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2685165318 Mar 17 12:59:01 PM PDT 24 Mar 17 01:00:59 PM PDT 24 50911381154 ps
T803 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2280035484 Mar 17 12:59:18 PM PDT 24 Mar 17 12:59:21 PM PDT 24 2099958589 ps
T100 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2037555933 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 519354276 ps
T804 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1817018203 Mar 17 12:59:25 PM PDT 24 Mar 17 12:59:26 PM PDT 24 322333838 ps
T321 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4059194415 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:21 PM PDT 24 4406032814 ps
T805 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.167767091 Mar 17 12:59:19 PM PDT 24 Mar 17 12:59:20 PM PDT 24 450111380 ps
T806 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2668743493 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:24 PM PDT 24 406068751 ps
T807 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2586803012 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:25 PM PDT 24 963006435 ps
T808 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.512297233 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:24 PM PDT 24 457698391 ps
T809 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3000575363 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:13 PM PDT 24 591872616 ps
T810 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2840448671 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:13 PM PDT 24 299971350 ps
T101 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3178670151 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:10 PM PDT 24 1089785064 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2571117300 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:15 PM PDT 24 5113376480 ps
T102 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.140371571 Mar 17 12:59:17 PM PDT 24 Mar 17 12:59:18 PM PDT 24 565853644 ps
T812 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3527366767 Mar 17 12:59:17 PM PDT 24 Mar 17 12:59:19 PM PDT 24 464065305 ps
T813 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2385489970 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 519808017 ps
T814 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4125009140 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:06 PM PDT 24 302192170 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.397035458 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 353640150 ps
T816 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3930508011 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:12 PM PDT 24 402106375 ps
T817 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1257758660 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:25 PM PDT 24 543222589 ps
T818 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3327689741 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:12 PM PDT 24 4134286625 ps
T103 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.961141032 Mar 17 12:59:04 PM PDT 24 Mar 17 12:59:07 PM PDT 24 940325389 ps
T819 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.803611070 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:25 PM PDT 24 489757419 ps
T820 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.251139700 Mar 17 12:59:01 PM PDT 24 Mar 17 12:59:04 PM PDT 24 613602805 ps
T821 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1992201984 Mar 17 12:59:28 PM PDT 24 Mar 17 12:59:30 PM PDT 24 449979408 ps
T822 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1887851746 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:10 PM PDT 24 562021687 ps
T823 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1592417368 Mar 17 12:59:20 PM PDT 24 Mar 17 12:59:29 PM PDT 24 8499488618 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3963921300 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:08 PM PDT 24 1240322264 ps
T825 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1055049462 Mar 17 12:59:26 PM PDT 24 Mar 17 12:59:28 PM PDT 24 346150001 ps
T826 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3639699297 Mar 17 12:59:27 PM PDT 24 Mar 17 12:59:28 PM PDT 24 546495477 ps
T827 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4152030079 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:11 PM PDT 24 485970430 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4286571593 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:13 PM PDT 24 641437359 ps
T829 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3626754389 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:23 PM PDT 24 4590362785 ps
T830 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2945119013 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:07 PM PDT 24 404027310 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2726179604 Mar 17 12:59:17 PM PDT 24 Mar 17 12:59:19 PM PDT 24 473443868 ps
T832 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3414834919 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:07 PM PDT 24 411993467 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2265040623 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:16 PM PDT 24 2425755313 ps
T834 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1354199121 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:16 PM PDT 24 4068967953 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.572981415 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 437994667 ps
T836 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2545305718 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:17 PM PDT 24 448246477 ps
T837 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3154657016 Mar 17 12:59:25 PM PDT 24 Mar 17 12:59:27 PM PDT 24 499820937 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2502935393 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:12 PM PDT 24 2838793304 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3411929640 Mar 17 12:59:19 PM PDT 24 Mar 17 12:59:20 PM PDT 24 582327113 ps
T840 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.115000470 Mar 17 12:59:27 PM PDT 24 Mar 17 12:59:28 PM PDT 24 386722084 ps
T841 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3778129616 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:10 PM PDT 24 577613770 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1974683103 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:07 PM PDT 24 1283636687 ps
T843 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2157994047 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:24 PM PDT 24 8683191889 ps
T844 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.173568911 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:05 PM PDT 24 455558948 ps
T845 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2725794840 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:18 PM PDT 24 5139868796 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1283850675 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 425585717 ps
T847 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.389956865 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:08 PM PDT 24 485551734 ps
T848 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.864156285 Mar 17 12:59:22 PM PDT 24 Mar 17 12:59:23 PM PDT 24 285075823 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1619038166 Mar 17 12:59:19 PM PDT 24 Mar 17 12:59:20 PM PDT 24 353985829 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.693636446 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:09 PM PDT 24 336739516 ps
T851 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1679806344 Mar 17 12:59:26 PM PDT 24 Mar 17 12:59:28 PM PDT 24 521618214 ps
T852 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2918247234 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:13 PM PDT 24 2093610418 ps
T853 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1520288634 Mar 17 12:59:10 PM PDT 24 Mar 17 12:59:17 PM PDT 24 4381191065 ps
T854 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1998965673 Mar 17 12:59:24 PM PDT 24 Mar 17 12:59:25 PM PDT 24 311946516 ps
T855 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.475060813 Mar 17 12:59:24 PM PDT 24 Mar 17 12:59:25 PM PDT 24 314161679 ps
T856 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1723251873 Mar 17 12:59:24 PM PDT 24 Mar 17 12:59:25 PM PDT 24 577354056 ps
T857 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.802933302 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:22 PM PDT 24 2334697073 ps
T858 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.481402393 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:14 PM PDT 24 487687222 ps
T859 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1848376000 Mar 17 12:59:24 PM PDT 24 Mar 17 12:59:26 PM PDT 24 353696417 ps
T317 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.112761136 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:08 PM PDT 24 4472632275 ps
T860 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1688130238 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:12 PM PDT 24 289113855 ps
T861 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2718319530 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:08 PM PDT 24 2074779334 ps
T862 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1468805442 Mar 17 12:59:21 PM PDT 24 Mar 17 12:59:28 PM PDT 24 8084874884 ps
T863 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.37156938 Mar 17 12:59:07 PM PDT 24 Mar 17 12:59:10 PM PDT 24 583403237 ps
T864 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3086294275 Mar 17 12:59:19 PM PDT 24 Mar 17 12:59:21 PM PDT 24 684026606 ps
T318 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1104373294 Mar 17 12:59:20 PM PDT 24 Mar 17 12:59:28 PM PDT 24 8399965767 ps
T865 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2308759923 Mar 17 12:59:14 PM PDT 24 Mar 17 12:59:22 PM PDT 24 4401320322 ps
T866 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2802675545 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:15 PM PDT 24 518998757 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1417615077 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:16 PM PDT 24 1407874025 ps
T868 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.356015769 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:18 PM PDT 24 831421016 ps
T869 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2777502272 Mar 17 12:59:20 PM PDT 24 Mar 17 12:59:21 PM PDT 24 388900799 ps
T870 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4030010347 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:26 PM PDT 24 8798248459 ps
T871 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3308564215 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:16 PM PDT 24 4373104135 ps
T872 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2746748688 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:14 PM PDT 24 437604953 ps
T873 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1507865724 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:06 PM PDT 24 869931826 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1511406697 Mar 17 12:59:01 PM PDT 24 Mar 17 12:59:08 PM PDT 24 8671922146 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2967517636 Mar 17 12:59:06 PM PDT 24 Mar 17 12:59:07 PM PDT 24 464521615 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3614908646 Mar 17 12:59:08 PM PDT 24 Mar 17 12:59:09 PM PDT 24 477069332 ps
T877 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4184614662 Mar 17 12:59:07 PM PDT 24 Mar 17 12:59:08 PM PDT 24 414286444 ps
T878 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1153870584 Mar 17 12:59:23 PM PDT 24 Mar 17 12:59:25 PM PDT 24 290214925 ps
T879 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1670135392 Mar 17 12:59:07 PM PDT 24 Mar 17 12:59:08 PM PDT 24 477405472 ps
T880 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3292090937 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 542050454 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2415883593 Mar 17 12:59:09 PM PDT 24 Mar 17 12:59:13 PM PDT 24 4417518877 ps
T882 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1007580273 Mar 17 12:59:25 PM PDT 24 Mar 17 12:59:26 PM PDT 24 510527409 ps
T883 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3360174520 Mar 17 12:59:28 PM PDT 24 Mar 17 12:59:29 PM PDT 24 490960334 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.44597249 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:14 PM PDT 24 739335087 ps
T885 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1723384093 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:16 PM PDT 24 564958262 ps
T886 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2480765594 Mar 17 12:59:27 PM PDT 24 Mar 17 12:59:29 PM PDT 24 430108774 ps
T887 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2527433126 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:36 PM PDT 24 4492120786 ps
T888 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.956456857 Mar 17 12:59:17 PM PDT 24 Mar 17 12:59:18 PM PDT 24 387766168 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.27198573 Mar 17 12:59:12 PM PDT 24 Mar 17 12:59:16 PM PDT 24 1218921865 ps
T890 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3062620266 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:04 PM PDT 24 449524169 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3515768128 Mar 17 12:59:16 PM PDT 24 Mar 17 12:59:17 PM PDT 24 283262834 ps
T892 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1658013365 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:15 PM PDT 24 535187428 ps
T893 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2910531110 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:17 PM PDT 24 578672242 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3267827204 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:07 PM PDT 24 1004824240 ps
T895 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4197158626 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:15 PM PDT 24 420428204 ps
T896 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2321172092 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:08 PM PDT 24 1307576483 ps
T897 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1094431350 Mar 17 12:59:05 PM PDT 24 Mar 17 12:59:06 PM PDT 24 518864147 ps
T898 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1789835572 Mar 17 12:59:03 PM PDT 24 Mar 17 12:59:04 PM PDT 24 344193936 ps
T899 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2076504522 Mar 17 12:59:26 PM PDT 24 Mar 17 12:59:28 PM PDT 24 374911268 ps
T900 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4197824620 Mar 17 12:59:13 PM PDT 24 Mar 17 12:59:33 PM PDT 24 4672164119 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2658752722 Mar 17 12:59:15 PM PDT 24 Mar 17 12:59:19 PM PDT 24 422338475 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.864438957 Mar 17 12:59:11 PM PDT 24 Mar 17 12:59:13 PM PDT 24 414568643 ps
T903 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2682498033 Mar 17 12:59:02 PM PDT 24 Mar 17 12:59:04 PM PDT 24 297018176 ps

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.969023384
Short name T8
Test name
Test status
Simulation time 121138560344 ps
CPU time 262.88 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:32:40 PM PDT 24
Peak memory 210068 kb
Host smart-adf72fa4-b510-48f6-a381-2f07845764c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969023384 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.969023384
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2990340253
Short name T12
Test name
Test status
Simulation time 227695657437 ps
CPU time 162.98 seconds
Started Mar 17 12:26:54 PM PDT 24
Finished Mar 17 12:29:37 PM PDT 24
Peak memory 218220 kb
Host smart-12657825-c26f-4854-81d8-de0c4e36cab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990340253 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2990340253
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1331890202
Short name T2
Test name
Test status
Simulation time 319309983231 ps
CPU time 657.32 seconds
Started Mar 17 12:25:23 PM PDT 24
Finished Mar 17 12:36:21 PM PDT 24
Peak memory 201888 kb
Host smart-499bff7d-d484-448c-9d1d-d5a8fa215664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331890202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1331890202
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1162664723
Short name T47
Test name
Test status
Simulation time 518044101544 ps
CPU time 306.58 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:33:40 PM PDT 24
Peak memory 201708 kb
Host smart-dc028375-43de-4971-8795-b32d707c643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162664723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1162664723
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.893264682
Short name T153
Test name
Test status
Simulation time 528171503847 ps
CPU time 744.73 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:41:25 PM PDT 24
Peak memory 201680 kb
Host smart-81978355-e88d-469a-a3cb-46b18add9c7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893264682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.893264682
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.353177138
Short name T35
Test name
Test status
Simulation time 454346945296 ps
CPU time 552.46 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:36:11 PM PDT 24
Peak memory 210244 kb
Host smart-b3ccda9c-1a2a-4dc8-97d5-0b99310421c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353177138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
353177138
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3548782467
Short name T136
Test name
Test status
Simulation time 526896507013 ps
CPU time 83.84 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:29:22 PM PDT 24
Peak memory 200380 kb
Host smart-23db330a-170e-4d72-89a8-d101b4759aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548782467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3548782467
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1245418400
Short name T225
Test name
Test status
Simulation time 348921259770 ps
CPU time 429.79 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:34:02 PM PDT 24
Peak memory 210636 kb
Host smart-bb155b3e-bc7b-4d8a-8251-2381eba8431a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245418400 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1245418400
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2954203453
Short name T39
Test name
Test status
Simulation time 269886250864 ps
CPU time 412.94 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:35:57 PM PDT 24
Peak memory 210528 kb
Host smart-b1dd1b52-7ee0-4195-af5f-3aff97f7f990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954203453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2954203453
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2838290448
Short name T120
Test name
Test status
Simulation time 566436973540 ps
CPU time 1334.39 seconds
Started Mar 17 12:26:38 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 201816 kb
Host smart-acee4c27-72b1-4737-a1cd-d87a6bf5c07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838290448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2838290448
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3988988983
Short name T5
Test name
Test status
Simulation time 197807102781 ps
CPU time 460.15 seconds
Started Mar 17 12:27:14 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 201800 kb
Host smart-4ccebb3e-d219-484e-88d6-c527b5510540
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988988983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3988988983
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.557645789
Short name T128
Test name
Test status
Simulation time 530230772850 ps
CPU time 269.89 seconds
Started Mar 17 12:28:44 PM PDT 24
Finished Mar 17 12:33:14 PM PDT 24
Peak memory 201748 kb
Host smart-34c649bd-66f6-479e-b4c1-ffe40df81b66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557645789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.557645789
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1801546033
Short name T43
Test name
Test status
Simulation time 4611650262 ps
CPU time 2.71 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 216844 kb
Host smart-2fa05dd4-88b8-435a-be2d-bbf3d3cc841d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801546033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1801546033
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1381531447
Short name T192
Test name
Test status
Simulation time 486348512900 ps
CPU time 505.16 seconds
Started Mar 17 12:30:09 PM PDT 24
Finished Mar 17 12:38:35 PM PDT 24
Peak memory 201684 kb
Host smart-cba1f984-1d87-48c3-ac1a-ec8196203471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381531447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1381531447
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4130629640
Short name T59
Test name
Test status
Simulation time 557565219974 ps
CPU time 667.12 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:37:59 PM PDT 24
Peak memory 201832 kb
Host smart-33f832c1-7df9-4316-a2a8-968a7f89fb53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130629640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4130629640
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3416438519
Short name T194
Test name
Test status
Simulation time 485318384713 ps
CPU time 548.09 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:37:00 PM PDT 24
Peak memory 201720 kb
Host smart-c8e69d71-6758-49f3-839c-df0919e0eaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416438519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3416438519
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2237599773
Short name T115
Test name
Test status
Simulation time 502933229260 ps
CPU time 489.23 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:36:49 PM PDT 24
Peak memory 201748 kb
Host smart-e819ddc6-4288-410c-a448-2bcd91283da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237599773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2237599773
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3955098567
Short name T92
Test name
Test status
Simulation time 563226455 ps
CPU time 2.15 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201644 kb
Host smart-0c41a49a-ffb1-4a25-943d-47c3509c7d94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955098567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3955098567
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2167042334
Short name T208
Test name
Test status
Simulation time 327586624966 ps
CPU time 688.03 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:38:46 PM PDT 24
Peak memory 201788 kb
Host smart-71002f34-1d44-4edf-8cef-ea73b07f3f3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167042334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2167042334
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1481562246
Short name T67
Test name
Test status
Simulation time 684876435 ps
CPU time 3.38 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201528 kb
Host smart-3a657cbb-0c16-4a46-a969-55639609e086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481562246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1481562246
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3051247377
Short name T160
Test name
Test status
Simulation time 84436964340 ps
CPU time 175.1 seconds
Started Mar 17 12:26:47 PM PDT 24
Finished Mar 17 12:29:42 PM PDT 24
Peak memory 210172 kb
Host smart-e45c094a-0d4a-4bb2-ae18-44c653bd9874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051247377 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3051247377
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2683341885
Short name T213
Test name
Test status
Simulation time 335501934344 ps
CPU time 215.64 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:31:45 PM PDT 24
Peak memory 201604 kb
Host smart-25427816-7cc1-42db-ba4d-7ac3d0014caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683341885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2683341885
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3584139654
Short name T119
Test name
Test status
Simulation time 494932261044 ps
CPU time 321.61 seconds
Started Mar 17 12:26:55 PM PDT 24
Finished Mar 17 12:32:17 PM PDT 24
Peak memory 201812 kb
Host smart-98e5bde1-cf1d-4e91-aab0-cc2d33baa765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584139654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3584139654
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3947318617
Short name T132
Test name
Test status
Simulation time 510371796129 ps
CPU time 901.08 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:43:31 PM PDT 24
Peak memory 201668 kb
Host smart-42fe30c2-2df1-43dd-8e3b-c5c9b79819dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947318617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3947318617
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.663942333
Short name T141
Test name
Test status
Simulation time 328577754614 ps
CPU time 378.35 seconds
Started Mar 17 12:27:02 PM PDT 24
Finished Mar 17 12:33:21 PM PDT 24
Peak memory 201628 kb
Host smart-27c46ff9-80e0-4482-8610-b3e4b0af0f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663942333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.663942333
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1921268021
Short name T125
Test name
Test status
Simulation time 494184100099 ps
CPU time 553.4 seconds
Started Mar 17 12:28:02 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 201560 kb
Host smart-34c64033-33b9-452c-959e-e5233e35935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921268021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1921268021
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1039938458
Short name T19
Test name
Test status
Simulation time 659330566341 ps
CPU time 394.42 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:34:40 PM PDT 24
Peak memory 210020 kb
Host smart-4803cacd-00ba-4d38-90f2-4f2f2d99fbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039938458 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1039938458
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2450629781
Short name T157
Test name
Test status
Simulation time 333970707430 ps
CPU time 210.83 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:32:29 PM PDT 24
Peak memory 217936 kb
Host smart-ca33d68c-fc56-40ef-a46a-92fd5d70f750
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450629781 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2450629781
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.956660428
Short name T135
Test name
Test status
Simulation time 538103077254 ps
CPU time 1106.38 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:47:22 PM PDT 24
Peak memory 201636 kb
Host smart-f5cd039d-bb41-4b77-b412-1735b42f648b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956660428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.956660428
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1154605324
Short name T81
Test name
Test status
Simulation time 499963000 ps
CPU time 0.93 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 201468 kb
Host smart-0ba88fcf-a775-4dc3-a7fd-017f8d2959af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154605324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1154605324
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4059194415
Short name T321
Test name
Test status
Simulation time 4406032814 ps
CPU time 12.27 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:21 PM PDT 24
Peak memory 201824 kb
Host smart-7d9e2000-bfe4-4d4c-83dc-a33a28e60cb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059194415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4059194415
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4280334466
Short name T248
Test name
Test status
Simulation time 380940197568 ps
CPU time 58.84 seconds
Started Mar 17 12:28:40 PM PDT 24
Finished Mar 17 12:29:40 PM PDT 24
Peak memory 201692 kb
Host smart-6dafd406-bc1a-4455-838c-db5bd1c593f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280334466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4280334466
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.4113974453
Short name T262
Test name
Test status
Simulation time 332804581286 ps
CPU time 101.42 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:29:52 PM PDT 24
Peak memory 201552 kb
Host smart-8e2fa511-8935-4852-aae9-e0288c916db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113974453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.4113974453
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.281377619
Short name T234
Test name
Test status
Simulation time 491986921008 ps
CPU time 600.6 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:37:57 PM PDT 24
Peak memory 201700 kb
Host smart-b13bbd59-e9df-4ae1-b71b-1231d8c5f352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281377619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.281377619
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3883135016
Short name T191
Test name
Test status
Simulation time 161826235516 ps
CPU time 383.83 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:33:28 PM PDT 24
Peak memory 201740 kb
Host smart-44eb7d34-1da6-4a4b-b1cd-5cee6bc25cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883135016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3883135016
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2687636997
Short name T123
Test name
Test status
Simulation time 333001409865 ps
CPU time 790.27 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:41:35 PM PDT 24
Peak memory 201580 kb
Host smart-53ecb603-3703-4a78-8f3d-2bab42f986d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687636997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2687636997
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3611243286
Short name T44
Test name
Test status
Simulation time 463024900384 ps
CPU time 528.62 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:37:49 PM PDT 24
Peak memory 201672 kb
Host smart-1c896ab2-9c8d-4f21-86af-45a12961f831
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611243286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3611243286
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2479765035
Short name T87
Test name
Test status
Simulation time 490678536986 ps
CPU time 1103.53 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:44:46 PM PDT 24
Peak memory 201680 kb
Host smart-83c62f56-d611-4f3e-a63e-6dd736c1b6bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479765035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2479765035
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.993689006
Short name T242
Test name
Test status
Simulation time 592707609182 ps
CPU time 1605.18 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:53:22 PM PDT 24
Peak memory 212072 kb
Host smart-713f24a3-9341-41c5-914f-dbd3be071ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993689006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
993689006
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3548190528
Short name T256
Test name
Test status
Simulation time 192934011302 ps
CPU time 455.94 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:35:10 PM PDT 24
Peak memory 201716 kb
Host smart-5f4a8c6d-e341-437a-8bdf-cb8ffbdb2017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548190528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3548190528
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2956110807
Short name T244
Test name
Test status
Simulation time 162104975158 ps
CPU time 366.48 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 201720 kb
Host smart-eefc3031-a5dc-442d-b7e5-a83b79ee6e2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956110807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2956110807
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.522866373
Short name T261
Test name
Test status
Simulation time 212405716265 ps
CPU time 84.61 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:29:57 PM PDT 24
Peak memory 210124 kb
Host smart-d22fe0f9-853e-4295-a2e6-d1252f28ca9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522866373 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.522866373
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2924263305
Short name T114
Test name
Test status
Simulation time 341252500124 ps
CPU time 50.98 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 201788 kb
Host smart-306f5a01-8097-4edb-a720-a4d47416d763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924263305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2924263305
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2592700281
Short name T287
Test name
Test status
Simulation time 427405720153 ps
CPU time 95.16 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:30:15 PM PDT 24
Peak memory 201604 kb
Host smart-a8e0e7d4-8b8c-48d9-9b68-97a2b122eb03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592700281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2592700281
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1500567111
Short name T32
Test name
Test status
Simulation time 426360945677 ps
CPU time 502.76 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 202068 kb
Host smart-7795f6cf-2219-4fa3-bd9c-c3b33716e386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500567111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1500567111
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.473521921
Short name T26
Test name
Test status
Simulation time 344018731923 ps
CPU time 775.28 seconds
Started Mar 17 12:27:37 PM PDT 24
Finished Mar 17 12:40:33 PM PDT 24
Peak memory 201612 kb
Host smart-d0d3ffd3-2ace-477f-ab2d-cc2e3cdb2f79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473521921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.473521921
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3151640102
Short name T196
Test name
Test status
Simulation time 464235104247 ps
CPU time 177.88 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:31:20 PM PDT 24
Peak memory 201336 kb
Host smart-b78011a6-1874-44fc-acfc-1538399c8c9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151640102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3151640102
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1577865684
Short name T259
Test name
Test status
Simulation time 503359694285 ps
CPU time 347.54 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:33:53 PM PDT 24
Peak memory 201776 kb
Host smart-ab8cf0be-e983-45f9-a6be-2c124408d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577865684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1577865684
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.611981901
Short name T36
Test name
Test status
Simulation time 297077425403 ps
CPU time 534.04 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 210540 kb
Host smart-b362c86c-f7e2-4808-a210-01af990203f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611981901 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.611981901
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.233969469
Short name T243
Test name
Test status
Simulation time 499374428914 ps
CPU time 282.43 seconds
Started Mar 17 12:27:07 PM PDT 24
Finished Mar 17 12:31:51 PM PDT 24
Peak memory 201708 kb
Host smart-21264600-953d-452b-ba0a-4512888565e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233969469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.233969469
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3365187681
Short name T187
Test name
Test status
Simulation time 389745911002 ps
CPU time 866.47 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:42:33 PM PDT 24
Peak memory 201964 kb
Host smart-8eee3561-4b4a-4e66-b02d-0279ea5c3c73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365187681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3365187681
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3653149804
Short name T279
Test name
Test status
Simulation time 534860320582 ps
CPU time 334.5 seconds
Started Mar 17 12:27:22 PM PDT 24
Finished Mar 17 12:32:56 PM PDT 24
Peak memory 201920 kb
Host smart-89a0352e-4793-4467-9522-d90ebc449834
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653149804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3653149804
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.387195170
Short name T265
Test name
Test status
Simulation time 166450631418 ps
CPU time 201.4 seconds
Started Mar 17 12:28:41 PM PDT 24
Finished Mar 17 12:32:04 PM PDT 24
Peak memory 201544 kb
Host smart-2f196719-b986-416c-9553-51a51e256640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387195170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.387195170
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2687217664
Short name T178
Test name
Test status
Simulation time 124081382096 ps
CPU time 424.82 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:35:59 PM PDT 24
Peak memory 202032 kb
Host smart-2024bc22-52cb-405c-8e9a-bd50cdcc6c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687217664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2687217664
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3781812641
Short name T302
Test name
Test status
Simulation time 1470877299558 ps
CPU time 945.69 seconds
Started Mar 17 12:29:01 PM PDT 24
Finished Mar 17 12:44:47 PM PDT 24
Peak memory 210240 kb
Host smart-260ccd4c-2a48-4ae3-bf59-b224cb1f5920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781812641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3781812641
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.708748735
Short name T200
Test name
Test status
Simulation time 492571754555 ps
CPU time 264.16 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:32:06 PM PDT 24
Peak memory 202188 kb
Host smart-a5d99f4b-f544-4432-b5af-af59afb1a385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708748735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.708748735
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2970165126
Short name T122
Test name
Test status
Simulation time 336983449966 ps
CPU time 429.54 seconds
Started Mar 17 12:28:12 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 201568 kb
Host smart-14eac378-da88-481e-9232-3a1573d907cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970165126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2970165126
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1223063428
Short name T216
Test name
Test status
Simulation time 169457087517 ps
CPU time 363.55 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:34:52 PM PDT 24
Peak memory 201676 kb
Host smart-3a1ed0a3-af30-4737-ad5f-5c09bf03f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223063428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1223063428
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.485534436
Short name T307
Test name
Test status
Simulation time 514438411070 ps
CPU time 247.59 seconds
Started Mar 17 12:25:49 PM PDT 24
Finished Mar 17 12:29:57 PM PDT 24
Peak memory 201892 kb
Host smart-cfb374e9-62cd-451e-8e2a-73e28c52ba1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485534436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gatin
g.485534436
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3275905743
Short name T205
Test name
Test status
Simulation time 630339499224 ps
CPU time 100.72 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:29:39 PM PDT 24
Peak memory 210376 kb
Host smart-99c442e4-7a35-4cf6-b890-b1889877db0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275905743 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3275905743
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2018593507
Short name T796
Test name
Test status
Simulation time 52525723844 ps
CPU time 33.89 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 201848 kb
Host smart-5b6e4362-8463-4ac7-afd4-4a27afc4161b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018593507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2018593507
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2927156249
Short name T314
Test name
Test status
Simulation time 529742462198 ps
CPU time 1285.45 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:49:35 PM PDT 24
Peak memory 201608 kb
Host smart-a05d99d2-439d-4894-af56-50d7b1b059a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927156249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2927156249
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.531683057
Short name T237
Test name
Test status
Simulation time 352167769544 ps
CPU time 428.71 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:35:39 PM PDT 24
Peak memory 201668 kb
Host smart-a7cb3e7f-a894-4b08-879c-08dc6fda8f5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531683057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.531683057
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2460327968
Short name T247
Test name
Test status
Simulation time 539110178027 ps
CPU time 1176.32 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:48:09 PM PDT 24
Peak memory 201780 kb
Host smart-29f652f0-ac23-460b-b126-3a9aa321d22a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460327968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2460327968
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3350279809
Short name T219
Test name
Test status
Simulation time 516092530728 ps
CPU time 1163.15 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:48:07 PM PDT 24
Peak memory 201700 kb
Host smart-22215be8-0f6f-421d-8e0c-fe4b6afa7c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350279809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3350279809
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2090272815
Short name T45
Test name
Test status
Simulation time 501729303551 ps
CPU time 1172.09 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 201728 kb
Host smart-58cba550-796b-4be6-839c-0b0e5c81631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090272815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2090272815
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2371428253
Short name T281
Test name
Test status
Simulation time 326626789843 ps
CPU time 207.75 seconds
Started Mar 17 12:27:19 PM PDT 24
Finished Mar 17 12:30:47 PM PDT 24
Peak memory 200740 kb
Host smart-c81854e9-60b2-42f3-9743-6443aa7b193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371428253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2371428253
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3438593072
Short name T233
Test name
Test status
Simulation time 173503559500 ps
CPU time 48.46 seconds
Started Mar 17 12:26:33 PM PDT 24
Finished Mar 17 12:27:22 PM PDT 24
Peak memory 201816 kb
Host smart-4bb2da58-c5b5-4732-beac-d06b023f8ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438593072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3438593072
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2842740318
Short name T163
Test name
Test status
Simulation time 329865487638 ps
CPU time 205.47 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:31:26 PM PDT 24
Peak memory 201704 kb
Host smart-5977dc83-1e7a-4942-bb5c-0b70a502084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842740318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2842740318
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3870211336
Short name T52
Test name
Test status
Simulation time 82954066595 ps
CPU time 351.02 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:33:50 PM PDT 24
Peak memory 200640 kb
Host smart-ed7bc7d1-f0ab-4ddf-89b1-0d8550c68cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870211336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3870211336
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.251139700
Short name T820
Test name
Test status
Simulation time 613602805 ps
CPU time 3.04 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 211072 kb
Host smart-1e5719ae-3932-46aa-9f4f-f804d7346343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251139700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.251139700
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1577032920
Short name T62
Test name
Test status
Simulation time 9973609451 ps
CPU time 3.78 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201880 kb
Host smart-50f95d81-2e4f-4dd0-b2b8-ebaa6ea4b0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577032920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1577032920
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2766064826
Short name T61
Test name
Test status
Simulation time 8880828517 ps
CPU time 7.24 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201888 kb
Host smart-84d30141-ca4c-47f9-8ce5-084f66a246b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766064826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2766064826
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3652476205
Short name T324
Test name
Test status
Simulation time 443173542113 ps
CPU time 572.29 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:37:32 PM PDT 24
Peak memory 200948 kb
Host smart-5250e515-3d46-4eb2-bc88-4c47faba44a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652476205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3652476205
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1054964652
Short name T204
Test name
Test status
Simulation time 175800136737 ps
CPU time 424.77 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:33:15 PM PDT 24
Peak memory 201724 kb
Host smart-5d379c6f-79f3-4aef-b06f-868620d6068f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054964652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1054964652
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4129114012
Short name T235
Test name
Test status
Simulation time 520450747608 ps
CPU time 867.46 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:41:26 PM PDT 24
Peak memory 201816 kb
Host smart-c449e759-8649-46b9-8838-f7fc9938d901
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129114012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4129114012
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3096819674
Short name T296
Test name
Test status
Simulation time 492161707998 ps
CPU time 122.95 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:28:54 PM PDT 24
Peak memory 201712 kb
Host smart-314b82b5-f828-4d4b-87fb-aa46c0526a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096819674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3096819674
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1638475839
Short name T231
Test name
Test status
Simulation time 444709376942 ps
CPU time 231.02 seconds
Started Mar 17 12:27:50 PM PDT 24
Finished Mar 17 12:31:41 PM PDT 24
Peak memory 209748 kb
Host smart-0322b849-5612-4f46-a49e-2f7ce43d4d9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638475839 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1638475839
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2499774201
Short name T142
Test name
Test status
Simulation time 551774072708 ps
CPU time 430.01 seconds
Started Mar 17 12:27:12 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 201840 kb
Host smart-167c1909-b0a1-4905-b885-6e2f732266c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499774201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2499774201
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.4193557229
Short name T676
Test name
Test status
Simulation time 546980289128 ps
CPU time 806.36 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:40:45 PM PDT 24
Peak memory 218388 kb
Host smart-480d4f06-1b83-40e8-8474-905efe60ba83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193557229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.4193557229
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.122481918
Short name T308
Test name
Test status
Simulation time 165039523828 ps
CPU time 200.88 seconds
Started Mar 17 12:28:09 PM PDT 24
Finished Mar 17 12:31:31 PM PDT 24
Peak memory 201700 kb
Host smart-dc922a75-2169-45e2-a988-3483f81af6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122481918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.122481918
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1843238143
Short name T183
Test name
Test status
Simulation time 142919741591 ps
CPU time 445.45 seconds
Started Mar 17 12:28:12 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 201920 kb
Host smart-463bf9d5-1024-4f58-8a37-68b82c2a69f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843238143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1843238143
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.162864288
Short name T249
Test name
Test status
Simulation time 491899525597 ps
CPU time 1216.33 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:48:47 PM PDT 24
Peak memory 201668 kb
Host smart-331685a2-08ca-4187-8e4a-be926a6780fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162864288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.162864288
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.259887600
Short name T144
Test name
Test status
Simulation time 509662080280 ps
CPU time 224.12 seconds
Started Mar 17 12:28:42 PM PDT 24
Finished Mar 17 12:32:26 PM PDT 24
Peak memory 201676 kb
Host smart-f221cee6-be01-436d-8b6d-f042bff1e241
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259887600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.259887600
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3203772042
Short name T181
Test name
Test status
Simulation time 117619622571 ps
CPU time 439.54 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:35:34 PM PDT 24
Peak memory 202092 kb
Host smart-5db01d49-6797-4640-aadf-45e4d90979c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203772042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3203772042
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2952233991
Short name T195
Test name
Test status
Simulation time 211353893852 ps
CPU time 135.04 seconds
Started Mar 17 12:28:41 PM PDT 24
Finished Mar 17 12:30:57 PM PDT 24
Peak memory 201528 kb
Host smart-27c8ce0f-f517-4882-b544-f932860867e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952233991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2952233991
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1402797327
Short name T180
Test name
Test status
Simulation time 97760892962 ps
CPU time 387.79 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:35:28 PM PDT 24
Peak memory 202164 kb
Host smart-d6c4d2f0-fbdb-4efe-924a-1126faffe7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402797327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1402797327
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3699382939
Short name T795
Test name
Test status
Simulation time 1181725954 ps
CPU time 4.83 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 201848 kb
Host smart-c1050651-2acc-4f1d-b7b3-16c648068ea0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699382939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3699382939
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.44597249
Short name T884
Test name
Test status
Simulation time 739335087 ps
CPU time 2.33 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:14 PM PDT 24
Peak memory 201596 kb
Host smart-79f1436c-bd30-4a3c-b246-9a621d7a464f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44597249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_res
et.44597249
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1887851746
Short name T822
Test name
Test status
Simulation time 562021687 ps
CPU time 2.16 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 201660 kb
Host smart-5efa160a-0fc0-4cd9-8b54-db2ff35b35e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887851746 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1887851746
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.726668487
Short name T31
Test name
Test status
Simulation time 577770098 ps
CPU time 1.05 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201632 kb
Host smart-ffd63b41-77dc-4c2f-9e91-3fe398329264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726668487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.726668487
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4184614662
Short name T877
Test name
Test status
Simulation time 414286444 ps
CPU time 1.14 seconds
Started Mar 17 12:59:07 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201560 kb
Host smart-cd632d81-40b8-4781-a9ed-f5d0a15ab6b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184614662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4184614662
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3327689741
Short name T818
Test name
Test status
Simulation time 4134286625 ps
CPU time 9.04 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201848 kb
Host smart-a414ed84-e2bc-43aa-8ce1-21a9952e0675
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327689741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3327689741
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1354199121
Short name T834
Test name
Test status
Simulation time 4068967953 ps
CPU time 10.16 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201940 kb
Host smart-6e8bdd45-31d4-4bc1-8570-d641cfcf1419
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354199121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1354199121
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3267827204
Short name T894
Test name
Test status
Simulation time 1004824240 ps
CPU time 3.27 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201812 kb
Host smart-b283f6a5-afcc-429d-bf8a-0c06a18d460d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267827204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3267827204
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.36608965
Short name T97
Test name
Test status
Simulation time 25246209314 ps
CPU time 21.81 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:44 PM PDT 24
Peak memory 201848 kb
Host smart-03d09146-014d-45cc-9a01-f27348ef8f65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36608965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_ba
sh.36608965
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3963921300
Short name T824
Test name
Test status
Simulation time 1240322264 ps
CPU time 2.34 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201628 kb
Host smart-23d4a890-2ef0-465f-bb21-730abf27126c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963921300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3963921300
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.37156938
Short name T863
Test name
Test status
Simulation time 583403237 ps
CPU time 2.33 seconds
Started Mar 17 12:59:07 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 201664 kb
Host smart-7f58874a-6929-4f69-84de-f2a0fbe7d5a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37156938 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.37156938
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3414834919
Short name T832
Test name
Test status
Simulation time 411993467 ps
CPU time 1.82 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201632 kb
Host smart-32fee179-8a7d-4ab4-a0be-1a3004db304e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414834919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3414834919
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1789835572
Short name T898
Test name
Test status
Simulation time 344193936 ps
CPU time 1.07 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 201564 kb
Host smart-9e0132e5-3458-4e21-b735-6e7f2fbed3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789835572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1789835572
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1417615077
Short name T867
Test name
Test status
Simulation time 1407874025 ps
CPU time 2.86 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201600 kb
Host smart-15ced848-5946-45b1-a5c9-8238b980779d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417615077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1417615077
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2682498033
Short name T903
Test name
Test status
Simulation time 297018176 ps
CPU time 1.96 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 201940 kb
Host smart-50ef99cb-8129-47dc-adad-1af9c8fabc72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682498033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2682498033
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1511406697
Short name T874
Test name
Test status
Simulation time 8671922146 ps
CPU time 7.68 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201928 kb
Host smart-4378bf1d-5a8a-4e2a-917e-384d8aaf9701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511406697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1511406697
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.984778787
Short name T78
Test name
Test status
Simulation time 588744557 ps
CPU time 2.33 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201708 kb
Host smart-1aafd382-60fd-49bd-a2c7-524554a31c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984778787 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.984778787
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.4197158626
Short name T895
Test name
Test status
Simulation time 420428204 ps
CPU time 0.99 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201552 kb
Host smart-a7ff1883-862b-4a8f-8416-1c933a7b12a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197158626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.4197158626
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2545305718
Short name T836
Test name
Test status
Simulation time 448246477 ps
CPU time 1.68 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201624 kb
Host smart-2be7f0ed-11e1-44bd-a027-6c750e2986b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545305718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2545305718
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1198115787
Short name T55
Test name
Test status
Simulation time 4460506087 ps
CPU time 10.23 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:20 PM PDT 24
Peak memory 201936 kb
Host smart-a23787b5-1371-44a0-8ffa-645e569314af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198115787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1198115787
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1809849258
Short name T64
Test name
Test status
Simulation time 318287010 ps
CPU time 3.16 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 210068 kb
Host smart-66878df4-1286-4d49-8495-9f9c257a5ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809849258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1809849258
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3626754389
Short name T829
Test name
Test status
Simulation time 4590362785 ps
CPU time 11.37 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 201856 kb
Host smart-d66bcb70-7bf8-4441-86a3-f6d7c9a290a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626754389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3626754389
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2668743493
Short name T806
Test name
Test status
Simulation time 406068751 ps
CPU time 0.96 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 201644 kb
Host smart-4075d488-7ba4-4a89-9658-a90c3921f850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668743493 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2668743493
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.142378849
Short name T57
Test name
Test status
Simulation time 350750758 ps
CPU time 1.75 seconds
Started Mar 17 12:59:07 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201628 kb
Host smart-5e328f08-5e65-44cb-96ad-1673bd32255c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142378849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.142378849
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2746748688
Short name T872
Test name
Test status
Simulation time 437604953 ps
CPU time 1.61 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:14 PM PDT 24
Peak memory 201368 kb
Host smart-78ba98d9-2640-4634-a4a1-c5c254818cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746748688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2746748688
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.4197824620
Short name T900
Test name
Test status
Simulation time 4672164119 ps
CPU time 19.7 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:33 PM PDT 24
Peak memory 201896 kb
Host smart-c79b8003-e966-4f33-a41a-85c6b71dc18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197824620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.4197824620
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1094431350
Short name T897
Test name
Test status
Simulation time 518864147 ps
CPU time 1.88 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 201924 kb
Host smart-8ee87a47-dc1f-4976-8502-b7a80d265e05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094431350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1094431350
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1658013365
Short name T892
Test name
Test status
Simulation time 535187428 ps
CPU time 2.33 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201696 kb
Host smart-c01aa9bd-18d1-4741-b870-d3c0c6813f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658013365 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1658013365
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4152030079
Short name T827
Test name
Test status
Simulation time 485970430 ps
CPU time 0.98 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:11 PM PDT 24
Peak memory 201640 kb
Host smart-8e71faec-2ac3-440c-a0a3-dde32666f860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152030079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4152030079
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.572981415
Short name T835
Test name
Test status
Simulation time 437994667 ps
CPU time 0.92 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201636 kb
Host smart-9e7cf30d-95e2-4629-aec4-20af91750ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572981415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.572981415
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2725794840
Short name T845
Test name
Test status
Simulation time 5139868796 ps
CPU time 6.12 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201864 kb
Host smart-b7bd8309-8831-41c3-8e14-cf57185c7550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725794840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2725794840
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4286571593
Short name T828
Test name
Test status
Simulation time 641437359 ps
CPU time 1.54 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201932 kb
Host smart-387e2b8f-05d2-412d-8a39-67b8293ef7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286571593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4286571593
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1520288634
Short name T853
Test name
Test status
Simulation time 4381191065 ps
CPU time 6.5 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201892 kb
Host smart-757f82f3-9633-4466-87cc-90f85b168004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520288634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1520288634
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3411929640
Short name T839
Test name
Test status
Simulation time 582327113 ps
CPU time 1.29 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:20 PM PDT 24
Peak memory 201584 kb
Host smart-1a8c8158-9693-408a-b553-c125385581ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411929640 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3411929640
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2910531110
Short name T893
Test name
Test status
Simulation time 578672242 ps
CPU time 1.09 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201624 kb
Host smart-99f0817a-8ab1-4eb4-b3ab-0286c8e15c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910531110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2910531110
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2442359142
Short name T801
Test name
Test status
Simulation time 399386280 ps
CPU time 0.84 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 201520 kb
Host smart-8981c3b0-b342-4420-b7e0-a9477aad046c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442359142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2442359142
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4190407615
Short name T106
Test name
Test status
Simulation time 2362087496 ps
CPU time 6.47 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201704 kb
Host smart-a1e8eb43-7dbf-4de8-8fd9-9c820a86dbf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190407615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.4190407615
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.481402393
Short name T858
Test name
Test status
Simulation time 487687222 ps
CPU time 3.07 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:14 PM PDT 24
Peak memory 218268 kb
Host smart-22d2bf35-c6c8-4ed8-ab7b-0008e081f426
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481402393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.481402393
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4030010347
Short name T870
Test name
Test status
Simulation time 8798248459 ps
CPU time 16.74 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201820 kb
Host smart-1da4cf8d-3dce-4276-a74e-9dbf7eaa3002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030010347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4030010347
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1769257990
Short name T77
Test name
Test status
Simulation time 436240455 ps
CPU time 1.83 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201676 kb
Host smart-43818b2f-7d32-4bf3-8d21-c08f4bb7c504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769257990 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1769257990
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1257758660
Short name T817
Test name
Test status
Simulation time 543222589 ps
CPU time 1.98 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201528 kb
Host smart-3be9043b-7b27-421c-85c1-75d54ee51200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257758660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1257758660
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.397035458
Short name T815
Test name
Test status
Simulation time 353640150 ps
CPU time 0.89 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201632 kb
Host smart-a0866cba-636a-4b17-bbef-3353dfca5612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397035458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.397035458
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.436824749
Short name T56
Test name
Test status
Simulation time 4981879117 ps
CPU time 2.99 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201920 kb
Host smart-39962b9a-565e-4a70-b5f1-5c23b9b624a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436824749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.436824749
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2658752722
Short name T901
Test name
Test status
Simulation time 422338475 ps
CPU time 3.4 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 218200 kb
Host smart-7402391f-6f41-4aa7-83ac-61dec2991eec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658752722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2658752722
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2308759923
Short name T865
Test name
Test status
Simulation time 4401320322 ps
CPU time 7.22 seconds
Started Mar 17 12:59:14 PM PDT 24
Finished Mar 17 12:59:22 PM PDT 24
Peak memory 201876 kb
Host smart-41f9c427-1f42-49dd-9581-816f654e041d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308759923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2308759923
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1038352385
Short name T21
Test name
Test status
Simulation time 603140898 ps
CPU time 1.35 seconds
Started Mar 17 12:59:14 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201680 kb
Host smart-6ea51e8c-3cda-49a2-a820-bae311322aac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038352385 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1038352385
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.167767091
Short name T805
Test name
Test status
Simulation time 450111380 ps
CPU time 0.85 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:20 PM PDT 24
Peak memory 201640 kb
Host smart-18820207-9806-48a1-af09-f66c49557289
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167767091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.167767091
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3527366767
Short name T812
Test name
Test status
Simulation time 464065305 ps
CPU time 1.19 seconds
Started Mar 17 12:59:17 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 201592 kb
Host smart-e757af42-949a-45aa-9730-f666f421c26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527366767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3527366767
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.528243482
Short name T104
Test name
Test status
Simulation time 2385461089 ps
CPU time 6.02 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:22 PM PDT 24
Peak memory 201648 kb
Host smart-b1497f66-8e32-4a74-b984-452a811e3754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528243482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.528243482
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2906163479
Short name T798
Test name
Test status
Simulation time 406929184 ps
CPU time 2.82 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 217776 kb
Host smart-3c81982d-2d8b-4545-aeb2-39ddfc97b737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906163479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2906163479
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1468805442
Short name T862
Test name
Test status
Simulation time 8084874884 ps
CPU time 6.92 seconds
Started Mar 17 12:59:21 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201884 kb
Host smart-db048bee-99a5-4d3d-9a37-a7f8a31c006d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468805442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1468805442
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1836582710
Short name T90
Test name
Test status
Simulation time 490454709 ps
CPU time 1.1 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201628 kb
Host smart-b55c5417-2f77-4211-80e6-3775e26ec924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836582710 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1836582710
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.293720256
Short name T98
Test name
Test status
Simulation time 404857278 ps
CPU time 1.72 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201688 kb
Host smart-5f7ff66b-b7e5-46f3-9aa8-b8c4a7e7cce3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293720256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.293720256
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3515768128
Short name T891
Test name
Test status
Simulation time 283262834 ps
CPU time 1.32 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201624 kb
Host smart-95d51a1d-ec98-4431-b883-1568f0f38eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515768128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3515768128
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2280035484
Short name T803
Test name
Test status
Simulation time 2099958589 ps
CPU time 2.88 seconds
Started Mar 17 12:59:18 PM PDT 24
Finished Mar 17 12:59:21 PM PDT 24
Peak memory 201672 kb
Host smart-fdd49db0-ec87-4a38-b4e0-31f310dc7786
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280035484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2280035484
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1283850675
Short name T846
Test name
Test status
Simulation time 425585717 ps
CPU time 1.77 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201672 kb
Host smart-783c012c-a5b0-4cd5-8538-284969f332d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283850675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1283850675
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1592417368
Short name T823
Test name
Test status
Simulation time 8499488618 ps
CPU time 8.86 seconds
Started Mar 17 12:59:20 PM PDT 24
Finished Mar 17 12:59:29 PM PDT 24
Peak memory 201964 kb
Host smart-47618724-caa7-40f2-b85c-9ddd48df31ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592417368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1592417368
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3816806451
Short name T89
Test name
Test status
Simulation time 399588349 ps
CPU time 1.7 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201728 kb
Host smart-b009cdcb-efc4-4131-a3f6-1da883e61fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816806451 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3816806451
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2658355629
Short name T96
Test name
Test status
Simulation time 473956782 ps
CPU time 2.18 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 201684 kb
Host smart-ca1f40ff-9977-4b28-aa8b-0679c579c749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658355629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2658355629
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1619038166
Short name T849
Test name
Test status
Simulation time 353985829 ps
CPU time 1.11 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:20 PM PDT 24
Peak memory 201520 kb
Host smart-d8a6f98c-812b-436d-8451-3755cf2fcda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619038166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1619038166
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2623139611
Short name T800
Test name
Test status
Simulation time 2575333021 ps
CPU time 2.5 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201692 kb
Host smart-156bf7c3-2b16-4fcd-8ab8-18b0f7fcb739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623139611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2623139611
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3196159780
Short name T68
Test name
Test status
Simulation time 554663954 ps
CPU time 3.73 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 201816 kb
Host smart-94fd1779-1458-4be6-9255-4b00243387ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196159780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3196159780
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2157994047
Short name T843
Test name
Test status
Simulation time 8683191889 ps
CPU time 7.72 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 201896 kb
Host smart-a5be2dbb-6bfb-4e06-93b0-67532a37e330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157994047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2157994047
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1978918842
Short name T71
Test name
Test status
Simulation time 384870502 ps
CPU time 1.09 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201680 kb
Host smart-ef7e7fad-314e-41d0-82ca-316d2386fcbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978918842 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1978918842
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.140371571
Short name T102
Test name
Test status
Simulation time 565853644 ps
CPU time 1.13 seconds
Started Mar 17 12:59:17 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201592 kb
Host smart-14123ed6-1d85-493a-b62a-65f5eb077c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140371571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.140371571
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2726179604
Short name T831
Test name
Test status
Simulation time 473443868 ps
CPU time 1.67 seconds
Started Mar 17 12:59:17 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 201620 kb
Host smart-f6dad4c0-b5aa-4c94-b42b-af65c95cada8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726179604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2726179604
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3945457555
Short name T54
Test name
Test status
Simulation time 5135785256 ps
CPU time 7.73 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:27 PM PDT 24
Peak memory 201956 kb
Host smart-775ae84a-e546-4cec-b6b6-f6f03107f2ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945457555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3945457555
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3558849388
Short name T797
Test name
Test status
Simulation time 400867319 ps
CPU time 2.72 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201840 kb
Host smart-78ab650b-61d0-4375-9cda-9b5363a42a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558849388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3558849388
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1104373294
Short name T318
Test name
Test status
Simulation time 8399965767 ps
CPU time 7.79 seconds
Started Mar 17 12:59:20 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201964 kb
Host smart-9090da45-927f-4f14-a330-1fe790d8f9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104373294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1104373294
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3086294275
Short name T864
Test name
Test status
Simulation time 684026606 ps
CPU time 1.18 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:21 PM PDT 24
Peak memory 201588 kb
Host smart-6f5e2e13-cf5e-4cae-af05-fad142830eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086294275 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3086294275
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.184398851
Short name T95
Test name
Test status
Simulation time 362673986 ps
CPU time 1.04 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201552 kb
Host smart-5b29e980-3d9a-4a5b-a68e-a6e79a62d8d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184398851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.184398851
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2768416496
Short name T792
Test name
Test status
Simulation time 456231819 ps
CPU time 0.87 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201576 kb
Host smart-8cf112d0-9442-4a5b-874d-351288f92f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768416496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2768416496
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2527433126
Short name T887
Test name
Test status
Simulation time 4492120786 ps
CPU time 19.37 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:36 PM PDT 24
Peak memory 201956 kb
Host smart-eb18942f-3f28-4b73-ba6a-52c8756e1bc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527433126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2527433126
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2486581386
Short name T69
Test name
Test status
Simulation time 516840082 ps
CPU time 2.84 seconds
Started Mar 17 12:59:19 PM PDT 24
Finished Mar 17 12:59:22 PM PDT 24
Peak memory 201928 kb
Host smart-d7274fdd-8606-4868-b835-004dcaa71aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486581386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2486581386
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.522674610
Short name T63
Test name
Test status
Simulation time 8746847487 ps
CPU time 8.1 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201896 kb
Host smart-82a6cc13-3774-481e-9157-e136eaacdeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522674610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.522674610
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1974683103
Short name T842
Test name
Test status
Simulation time 1283636687 ps
CPU time 4.5 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 202144 kb
Host smart-fd1cf7f3-c0c7-4150-adfb-4f1fbf74f2b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974683103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1974683103
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2685165318
Short name T99
Test name
Test status
Simulation time 50911381154 ps
CPU time 118.19 seconds
Started Mar 17 12:59:01 PM PDT 24
Finished Mar 17 01:00:59 PM PDT 24
Peak memory 201892 kb
Host smart-5b6a6ce0-10bb-446b-bdd4-b6a150af45e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685165318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2685165318
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3178670151
Short name T101
Test name
Test status
Simulation time 1089785064 ps
CPU time 1.38 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 201648 kb
Host smart-76ded07b-cee0-4f28-8f48-3cfc1c9dc7ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178670151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3178670151
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2802675545
Short name T866
Test name
Test status
Simulation time 518998757 ps
CPU time 2.23 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201664 kb
Host smart-72d939e4-d301-4ef9-b9fa-205cd6824b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802675545 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2802675545
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3053768379
Short name T91
Test name
Test status
Simulation time 554054230 ps
CPU time 1.02 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201596 kb
Host smart-7bebf20b-329e-49b7-87ed-81da7f03bc33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053768379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3053768379
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4125009140
Short name T814
Test name
Test status
Simulation time 302192170 ps
CPU time 1.38 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 201604 kb
Host smart-adb66f1b-ac48-4442-a4b9-aa29b6c29bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125009140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4125009140
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2502935393
Short name T838
Test name
Test status
Simulation time 2838793304 ps
CPU time 2.18 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201688 kb
Host smart-103ede34-c616-4741-b3d4-4940c47f74fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502935393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2502935393
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.173568911
Short name T844
Test name
Test status
Simulation time 455558948 ps
CPU time 2.19 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:05 PM PDT 24
Peak memory 201872 kb
Host smart-51cfe48e-5150-4c96-85d3-35f7d530582f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173568911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.173568911
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.112761136
Short name T317
Test name
Test status
Simulation time 4472632275 ps
CPU time 2.73 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201912 kb
Host smart-d34a15a8-de48-4409-ab0d-80ebacd1edd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112761136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.112761136
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.956456857
Short name T888
Test name
Test status
Simulation time 387766168 ps
CPU time 1.5 seconds
Started Mar 17 12:59:17 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201528 kb
Host smart-b6d51baa-fcae-44d1-b6a9-da4834aa906a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956456857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.956456857
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3325704786
Short name T794
Test name
Test status
Simulation time 390090590 ps
CPU time 1.55 seconds
Started Mar 17 12:59:17 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201608 kb
Host smart-7f18f241-5d9c-4cd2-97ee-609ca5244b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325704786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3325704786
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2777502272
Short name T869
Test name
Test status
Simulation time 388900799 ps
CPU time 0.7 seconds
Started Mar 17 12:59:20 PM PDT 24
Finished Mar 17 12:59:21 PM PDT 24
Peak memory 201656 kb
Host smart-80cceab6-f826-40c7-afaf-f7b848a338ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777502272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2777502272
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.572592760
Short name T802
Test name
Test status
Simulation time 312905991 ps
CPU time 0.81 seconds
Started Mar 17 12:59:16 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201608 kb
Host smart-b32850eb-0ea1-4cab-a519-3e1200147492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572592760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.572592760
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2385489970
Short name T813
Test name
Test status
Simulation time 519808017 ps
CPU time 0.9 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201576 kb
Host smart-c6c23af8-0c45-4629-a44b-6d8556424e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385489970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2385489970
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1370239104
Short name T788
Test name
Test status
Simulation time 303514530 ps
CPU time 1.02 seconds
Started Mar 17 12:59:18 PM PDT 24
Finished Mar 17 12:59:19 PM PDT 24
Peak memory 201620 kb
Host smart-a9bdb880-708e-409d-b360-5c66153b81c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370239104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1370239104
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1723384093
Short name T885
Test name
Test status
Simulation time 564958262 ps
CPU time 0.94 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201568 kb
Host smart-0d11611b-a9fb-4cfc-affe-de4ca0ea223a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723384093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1723384093
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3292090937
Short name T880
Test name
Test status
Simulation time 542050454 ps
CPU time 0.84 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201568 kb
Host smart-3375bf4e-4fc5-4b31-8319-958f968cd07f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292090937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3292090937
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.864156285
Short name T848
Test name
Test status
Simulation time 285075823 ps
CPU time 1.25 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 201636 kb
Host smart-e3c37053-4d2f-45d5-929b-054f88d45b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864156285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.864156285
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1679806344
Short name T851
Test name
Test status
Simulation time 521618214 ps
CPU time 1.89 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201600 kb
Host smart-4f832b55-6b02-4b52-a5c7-dc3d11a0d770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679806344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1679806344
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1507865724
Short name T873
Test name
Test status
Simulation time 869931826 ps
CPU time 2.11 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:06 PM PDT 24
Peak memory 201868 kb
Host smart-309c25a8-4bc4-45ed-9d95-a3a651536d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507865724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1507865724
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1128580119
Short name T93
Test name
Test status
Simulation time 5436577728 ps
CPU time 7.99 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201856 kb
Host smart-c4c2c5d1-5d84-4b40-bef9-04310021a17d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128580119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1128580119
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.961141032
Short name T103
Test name
Test status
Simulation time 940325389 ps
CPU time 3.02 seconds
Started Mar 17 12:59:04 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201628 kb
Host smart-ce48147f-59a6-4c1d-a353-b176e80c3e1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961141032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.961141032
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4011049921
Short name T791
Test name
Test status
Simulation time 584838089 ps
CPU time 1.46 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201624 kb
Host smart-9f56c033-b9c5-4d8e-ad4a-300587e77d8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011049921 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4011049921
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3062620266
Short name T890
Test name
Test status
Simulation time 449524169 ps
CPU time 1.21 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:04 PM PDT 24
Peak memory 201624 kb
Host smart-d3e56bf3-e4b6-4f70-8bb7-c3ae2eaf50da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062620266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3062620266
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2945119013
Short name T830
Test name
Test status
Simulation time 404027310 ps
CPU time 1.69 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201640 kb
Host smart-053e9b5e-8582-4231-a0e0-095a76f5208e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945119013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2945119013
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2718319530
Short name T861
Test name
Test status
Simulation time 2074779334 ps
CPU time 3.32 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201616 kb
Host smart-c125fae2-d75f-4448-975f-706909c3b998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718319530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2718319530
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.711346247
Short name T74
Test name
Test status
Simulation time 906960784 ps
CPU time 2.52 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201892 kb
Host smart-9ba6d185-8c2c-4310-b110-3fb37aab7def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711346247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.711346247
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3154657016
Short name T837
Test name
Test status
Simulation time 499820937 ps
CPU time 1.79 seconds
Started Mar 17 12:59:25 PM PDT 24
Finished Mar 17 12:59:27 PM PDT 24
Peak memory 201636 kb
Host smart-c06da0fb-8314-4300-bea3-cfb32c01f6de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154657016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3154657016
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3639699297
Short name T826
Test name
Test status
Simulation time 546495477 ps
CPU time 0.84 seconds
Started Mar 17 12:59:27 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201608 kb
Host smart-23ce9819-2a4d-4151-8515-91f6cc380447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639699297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3639699297
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1055049462
Short name T825
Test name
Test status
Simulation time 346150001 ps
CPU time 1.47 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201612 kb
Host smart-7679a8d0-5c50-4ede-81a3-70b83f116172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055049462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1055049462
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1723251873
Short name T856
Test name
Test status
Simulation time 577354056 ps
CPU time 0.71 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201588 kb
Host smart-66a71c8b-824b-41d6-a8ef-e5551704d532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723251873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1723251873
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1141204405
Short name T789
Test name
Test status
Simulation time 420097779 ps
CPU time 1.38 seconds
Started Mar 17 12:59:25 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201632 kb
Host smart-76613b69-79c3-4a66-aabf-9bd32bd13429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141204405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1141204405
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1007580273
Short name T882
Test name
Test status
Simulation time 510527409 ps
CPU time 1.05 seconds
Started Mar 17 12:59:25 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201624 kb
Host smart-a21a2f12-d50e-4c26-bfd4-0d8d698069db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007580273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1007580273
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.475060813
Short name T855
Test name
Test status
Simulation time 314161679 ps
CPU time 1.1 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201592 kb
Host smart-00d79615-24c3-4013-8979-b795c3e188b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475060813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.475060813
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1992201984
Short name T821
Test name
Test status
Simulation time 449979408 ps
CPU time 1.66 seconds
Started Mar 17 12:59:28 PM PDT 24
Finished Mar 17 12:59:30 PM PDT 24
Peak memory 201624 kb
Host smart-bd09bd44-628e-4a5d-9cb8-74039583fdb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992201984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1992201984
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1153870584
Short name T878
Test name
Test status
Simulation time 290214925 ps
CPU time 1.25 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201576 kb
Host smart-4408b9de-193c-4cba-aced-42848029177b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153870584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1153870584
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.27198573
Short name T889
Test name
Test status
Simulation time 1218921865 ps
CPU time 3.81 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201776 kb
Host smart-1518062a-2c00-4cb8-b217-eb58d846ca84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasi
ng.27198573
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.921503506
Short name T107
Test name
Test status
Simulation time 26531832267 ps
CPU time 91.57 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 01:00:38 PM PDT 24
Peak memory 201868 kb
Host smart-29aa4603-6724-479e-ae50-c477d3c13dd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921503506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.921503506
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2321172092
Short name T896
Test name
Test status
Simulation time 1307576483 ps
CPU time 2.24 seconds
Started Mar 17 12:59:05 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201652 kb
Host smart-679ccc12-c23c-4fc4-9fb0-746f0eb680c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321172092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2321172092
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.389956865
Short name T847
Test name
Test status
Simulation time 485551734 ps
CPU time 1.92 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201624 kb
Host smart-1e7daa42-4495-45df-915a-1a8665aa6310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389956865 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.389956865
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2520397960
Short name T94
Test name
Test status
Simulation time 335188643 ps
CPU time 0.89 seconds
Started Mar 17 12:59:02 PM PDT 24
Finished Mar 17 12:59:03 PM PDT 24
Peak memory 201624 kb
Host smart-c9c1ecb7-4eba-466c-9bfd-3fe213d66adb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520397960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2520397960
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2840448671
Short name T810
Test name
Test status
Simulation time 299971350 ps
CPU time 0.83 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201604 kb
Host smart-4f97bbc4-3325-4b3d-8d3a-554ff2b2618c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840448671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2840448671
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2571117300
Short name T811
Test name
Test status
Simulation time 5113376480 ps
CPU time 11.82 seconds
Started Mar 17 12:59:03 PM PDT 24
Finished Mar 17 12:59:15 PM PDT 24
Peak memory 201840 kb
Host smart-fe085c7f-624b-4534-afea-69f9384ff70d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571117300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2571117300
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.803611070
Short name T819
Test name
Test status
Simulation time 489757419 ps
CPU time 2.18 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201896 kb
Host smart-9e49d05c-4ae0-4c71-886b-cc473678283d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803611070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.803611070
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2415883593
Short name T881
Test name
Test status
Simulation time 4417518877 ps
CPU time 3.68 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201796 kb
Host smart-68b83d77-73c1-4dee-ba2a-cd963655c168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415883593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2415883593
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.512297233
Short name T808
Test name
Test status
Simulation time 457698391 ps
CPU time 0.89 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 201680 kb
Host smart-ef3fc731-8061-43bc-aecc-911a8643e3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512297233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.512297233
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4042200138
Short name T787
Test name
Test status
Simulation time 560486046 ps
CPU time 0.97 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201568 kb
Host smart-3033bb7f-bd8d-4355-a019-cf6db8d4b369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042200138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4042200138
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1998965673
Short name T854
Test name
Test status
Simulation time 311946516 ps
CPU time 1.37 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201600 kb
Host smart-980696bd-6d88-48f0-972a-4b55b7197f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998965673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1998965673
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2076504522
Short name T899
Test name
Test status
Simulation time 374911268 ps
CPU time 1.52 seconds
Started Mar 17 12:59:26 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201656 kb
Host smart-9583c0f1-bcd4-4709-928a-844801d27ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076504522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2076504522
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1817018203
Short name T804
Test name
Test status
Simulation time 322333838 ps
CPU time 0.84 seconds
Started Mar 17 12:59:25 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201624 kb
Host smart-fed4d9be-5452-4ee9-98f2-81627a1ec92f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817018203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1817018203
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2480765594
Short name T886
Test name
Test status
Simulation time 430108774 ps
CPU time 1.56 seconds
Started Mar 17 12:59:27 PM PDT 24
Finished Mar 17 12:59:29 PM PDT 24
Peak memory 201624 kb
Host smart-6d47a819-331a-4d76-bdc9-9026b0b01546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480765594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2480765594
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.115000470
Short name T840
Test name
Test status
Simulation time 386722084 ps
CPU time 1.49 seconds
Started Mar 17 12:59:27 PM PDT 24
Finished Mar 17 12:59:28 PM PDT 24
Peak memory 201600 kb
Host smart-f5b0abfa-eef9-4fd2-a95c-5a3de245480c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115000470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.115000470
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3360174520
Short name T883
Test name
Test status
Simulation time 490960334 ps
CPU time 0.96 seconds
Started Mar 17 12:59:28 PM PDT 24
Finished Mar 17 12:59:29 PM PDT 24
Peak memory 201632 kb
Host smart-6f824570-c660-415a-a6b4-2221489f355b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360174520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3360174520
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1848376000
Short name T859
Test name
Test status
Simulation time 353696417 ps
CPU time 1.51 seconds
Started Mar 17 12:59:24 PM PDT 24
Finished Mar 17 12:59:26 PM PDT 24
Peak memory 201824 kb
Host smart-c5253812-783e-485b-92a1-bccd91575d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848376000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1848376000
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1645218575
Short name T793
Test name
Test status
Simulation time 443174448 ps
CPU time 1.56 seconds
Started Mar 17 12:59:22 PM PDT 24
Finished Mar 17 12:59:24 PM PDT 24
Peak memory 201604 kb
Host smart-07607e01-266d-4878-98fe-33ba8620d79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645218575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1645218575
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3930508011
Short name T816
Test name
Test status
Simulation time 402106375 ps
CPU time 1.78 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201704 kb
Host smart-16a56292-54f7-45d3-8d19-8bcee56d4939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930508011 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3930508011
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3614908646
Short name T876
Test name
Test status
Simulation time 477069332 ps
CPU time 1.44 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201676 kb
Host smart-c412b870-bd29-4cc1-8aeb-0155663f7b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614908646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3614908646
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1688130238
Short name T860
Test name
Test status
Simulation time 289113855 ps
CPU time 1.31 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201552 kb
Host smart-40057602-136f-443e-b927-6ca096fdcaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688130238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1688130238
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2229046764
Short name T105
Test name
Test status
Simulation time 5014517694 ps
CPU time 12.22 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:23 PM PDT 24
Peak memory 201876 kb
Host smart-97c8ba4f-cbcb-4ade-81a1-9f461947e495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229046764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2229046764
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3566219687
Short name T319
Test name
Test status
Simulation time 4469696667 ps
CPU time 3.83 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201852 kb
Host smart-b6bbd797-6690-45a7-95f9-ed20f6633836
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566219687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3566219687
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1670135392
Short name T879
Test name
Test status
Simulation time 477405472 ps
CPU time 1.07 seconds
Started Mar 17 12:59:07 PM PDT 24
Finished Mar 17 12:59:08 PM PDT 24
Peak memory 201676 kb
Host smart-b4f6b9fa-f276-4bdc-b5f5-018b88b12a1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670135392 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1670135392
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3608073130
Short name T790
Test name
Test status
Simulation time 520442513 ps
CPU time 0.96 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:12 PM PDT 24
Peak memory 201668 kb
Host smart-1866c18b-045f-49f5-a0dd-7b4c1c3800ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608073130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3608073130
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.802933302
Short name T857
Test name
Test status
Simulation time 2334697073 ps
CPU time 9.1 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:22 PM PDT 24
Peak memory 201728 kb
Host smart-a30fbf37-f60f-4023-80f6-c955b33bdebf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802933302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.802933302
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.356015769
Short name T868
Test name
Test status
Simulation time 831421016 ps
CPU time 2.81 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201896 kb
Host smart-e9b10fcf-1f0d-4959-affe-cdd8e22fc13e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356015769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.356015769
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.414608132
Short name T76
Test name
Test status
Simulation time 667487521 ps
CPU time 2.37 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 201644 kb
Host smart-c163303d-4f91-4dcc-8b71-605d68e9cb71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414608132 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.414608132
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2704312976
Short name T108
Test name
Test status
Simulation time 499489154 ps
CPU time 1.32 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201616 kb
Host smart-2eab6772-528b-4d09-ab6e-384856e8d7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704312976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2704312976
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3000575363
Short name T809
Test name
Test status
Simulation time 591872616 ps
CPU time 0.8 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201672 kb
Host smart-4ae07dbd-da23-4e98-95ab-670ed6e66833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000575363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3000575363
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1119050526
Short name T799
Test name
Test status
Simulation time 2399288235 ps
CPU time 6.48 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:17 PM PDT 24
Peak memory 201700 kb
Host smart-62592d42-66cb-4b9a-86ee-5bd1aa299adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119050526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1119050526
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2586803012
Short name T807
Test name
Test status
Simulation time 963006435 ps
CPU time 2.14 seconds
Started Mar 17 12:59:23 PM PDT 24
Finished Mar 17 12:59:25 PM PDT 24
Peak memory 210028 kb
Host smart-43bc510f-1821-45b6-9092-3fbaa2a4d0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586803012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2586803012
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3264759907
Short name T320
Test name
Test status
Simulation time 4440395935 ps
CPU time 3.97 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201884 kb
Host smart-93ed9fd0-5e8c-41a7-979a-3f1a04b7d33d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264759907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3264759907
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3778129616
Short name T841
Test name
Test status
Simulation time 577613770 ps
CPU time 1.36 seconds
Started Mar 17 12:59:09 PM PDT 24
Finished Mar 17 12:59:10 PM PDT 24
Peak memory 201680 kb
Host smart-74695015-38cc-487a-a0f2-7fbc652de57a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778129616 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3778129616
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2037555933
Short name T100
Test name
Test status
Simulation time 519354276 ps
CPU time 1.14 seconds
Started Mar 17 12:59:15 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201632 kb
Host smart-a4e2454a-4e79-42aa-861e-0f4c3b876285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037555933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2037555933
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2842786625
Short name T786
Test name
Test status
Simulation time 356144389 ps
CPU time 1.08 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201548 kb
Host smart-95e34581-2858-4952-96b0-b58181be9750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842786625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2842786625
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2265040623
Short name T833
Test name
Test status
Simulation time 2425755313 ps
CPU time 3.5 seconds
Started Mar 17 12:59:12 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201460 kb
Host smart-06040113-db2e-45b0-a2ec-4e35c58eb6e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265040623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2265040623
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.864438957
Short name T902
Test name
Test status
Simulation time 414568643 ps
CPU time 2.35 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201864 kb
Host smart-12481c47-e7f4-4398-b391-c98ef8a9fc6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864438957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.864438957
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.467013014
Short name T80
Test name
Test status
Simulation time 8686298173 ps
CPU time 7.28 seconds
Started Mar 17 12:59:11 PM PDT 24
Finished Mar 17 12:59:18 PM PDT 24
Peak memory 201884 kb
Host smart-e4894c88-bbaf-4a71-8a59-fca57e4f8317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467013014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.467013014
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.953267587
Short name T79
Test name
Test status
Simulation time 639514326 ps
CPU time 1.58 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:11 PM PDT 24
Peak memory 210076 kb
Host smart-197c26d6-bd67-46e9-90ad-36c902ef268c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953267587 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.953267587
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.693636446
Short name T850
Test name
Test status
Simulation time 336739516 ps
CPU time 1.51 seconds
Started Mar 17 12:59:08 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201628 kb
Host smart-c81b5cf8-2fb5-4bd5-bdaf-7c89d66ae197
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693636446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.693636446
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2967517636
Short name T875
Test name
Test status
Simulation time 464521615 ps
CPU time 0.76 seconds
Started Mar 17 12:59:06 PM PDT 24
Finished Mar 17 12:59:07 PM PDT 24
Peak memory 201656 kb
Host smart-07e97be7-c7c6-4921-88e2-d0ffe7d8fe4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967517636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2967517636
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2918247234
Short name T852
Test name
Test status
Simulation time 2093610418 ps
CPU time 2.84 seconds
Started Mar 17 12:59:10 PM PDT 24
Finished Mar 17 12:59:13 PM PDT 24
Peak memory 201628 kb
Host smart-d4dfa18f-b983-4300-ba58-95f31f56c50d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918247234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2918247234
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2677183162
Short name T75
Test name
Test status
Simulation time 474246498 ps
CPU time 2.32 seconds
Started Mar 17 12:59:07 PM PDT 24
Finished Mar 17 12:59:09 PM PDT 24
Peak memory 201908 kb
Host smart-76d3cabf-6e05-4614-9050-a307b23b75ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677183162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2677183162
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3308564215
Short name T871
Test name
Test status
Simulation time 4373104135 ps
CPU time 3.21 seconds
Started Mar 17 12:59:13 PM PDT 24
Finished Mar 17 12:59:16 PM PDT 24
Peak memory 201540 kb
Host smart-21a070e6-8559-44bc-8e18-51c4393197f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308564215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3308564215
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.901449819
Short name T623
Test name
Test status
Simulation time 610816026 ps
CPU time 0.73 seconds
Started Mar 17 12:23:36 PM PDT 24
Finished Mar 17 12:23:37 PM PDT 24
Peak memory 201368 kb
Host smart-5b2194c4-ee06-46dd-9f3f-9de34c2713ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901449819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.901449819
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.174512885
Short name T134
Test name
Test status
Simulation time 351561045294 ps
CPU time 33.63 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:43 PM PDT 24
Peak memory 201720 kb
Host smart-3e302e50-1583-45fb-a7ef-21462db290eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174512885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.174512885
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4106736811
Short name T640
Test name
Test status
Simulation time 163108447691 ps
CPU time 94 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:27:13 PM PDT 24
Peak memory 201796 kb
Host smart-29d2114c-96db-480a-ae25-6b0aa40dc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106736811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4106736811
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3784669362
Short name T591
Test name
Test status
Simulation time 324861075361 ps
CPU time 187.8 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:28:47 PM PDT 24
Peak memory 201700 kb
Host smart-c1109a8e-65fc-487d-b86a-c1c2cbc55d2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784669362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3784669362
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.300586609
Short name T517
Test name
Test status
Simulation time 169262267298 ps
CPU time 90.72 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:29:14 PM PDT 24
Peak memory 201620 kb
Host smart-7e9a5d8b-2c25-45da-8723-c42271f70f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300586609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.300586609
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.130598464
Short name T489
Test name
Test status
Simulation time 163970675709 ps
CPU time 218.47 seconds
Started Mar 17 12:25:52 PM PDT 24
Finished Mar 17 12:29:31 PM PDT 24
Peak memory 201676 kb
Host smart-d415fc9f-590c-4ead-9bb7-4f74f91c3dfc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=130598464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.130598464
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.404223064
Short name T295
Test name
Test status
Simulation time 512582900582 ps
CPU time 310.35 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:32:31 PM PDT 24
Peak memory 201616 kb
Host smart-66ba59a4-ccd9-4d99-a470-0861e84a95bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404223064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.404223064
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.780276441
Short name T675
Test name
Test status
Simulation time 585139571202 ps
CPU time 1317.78 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:50:28 PM PDT 24
Peak memory 201688 kb
Host smart-f1a2f896-35b6-468a-bbf5-3b3879f5c5f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780276441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.780276441
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3004047286
Short name T349
Test name
Test status
Simulation time 67376515035 ps
CPU time 378.62 seconds
Started Mar 17 12:26:13 PM PDT 24
Finished Mar 17 12:32:32 PM PDT 24
Peak memory 201844 kb
Host smart-2c280450-15a4-499e-8647-19af15e6de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004047286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3004047286
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1401705168
Short name T438
Test name
Test status
Simulation time 26728099068 ps
CPU time 62.94 seconds
Started Mar 17 12:24:13 PM PDT 24
Finished Mar 17 12:25:17 PM PDT 24
Peak memory 201504 kb
Host smart-c0480a68-a76c-457c-9358-756705e0a1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401705168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1401705168
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3442151312
Short name T422
Test name
Test status
Simulation time 4022967259 ps
CPU time 3.02 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:27:59 PM PDT 24
Peak memory 200348 kb
Host smart-e105ca96-1fc2-4f4e-8f24-f098e58e5f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442151312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3442151312
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1322184655
Short name T521
Test name
Test status
Simulation time 5803603665 ps
CPU time 7.89 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:51 PM PDT 24
Peak memory 201456 kb
Host smart-db6d51b2-9483-48aa-bcb1-1075b3de8906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322184655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1322184655
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4284079927
Short name T608
Test name
Test status
Simulation time 250074721351 ps
CPU time 793 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:41:08 PM PDT 24
Peak memory 210184 kb
Host smart-6a801103-8475-4cf7-a505-bbcbca37a4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284079927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4284079927
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1193986010
Short name T18
Test name
Test status
Simulation time 151026629903 ps
CPU time 600.39 seconds
Started Mar 17 12:25:42 PM PDT 24
Finished Mar 17 12:35:42 PM PDT 24
Peak memory 211576 kb
Host smart-7c5c86ca-0988-4ee1-b402-cff1f0171a27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193986010 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1193986010
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2172877735
Short name T564
Test name
Test status
Simulation time 479552682 ps
CPU time 1.73 seconds
Started Mar 17 12:24:16 PM PDT 24
Finished Mar 17 12:24:18 PM PDT 24
Peak memory 201348 kb
Host smart-886a892b-5772-42ed-a810-1e173975cb92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172877735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2172877735
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4261024831
Short name T298
Test name
Test status
Simulation time 494160512828 ps
CPU time 833.52 seconds
Started Mar 17 12:26:08 PM PDT 24
Finished Mar 17 12:40:02 PM PDT 24
Peak memory 201672 kb
Host smart-45457492-5c67-41d1-bb1e-f8757e967f58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261024831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4261024831
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1156840900
Short name T760
Test name
Test status
Simulation time 340768326096 ps
CPU time 773.21 seconds
Started Mar 17 12:22:38 PM PDT 24
Finished Mar 17 12:35:32 PM PDT 24
Peak memory 202112 kb
Host smart-8a8fa51b-fab9-4220-8457-ff70c14c7592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156840900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1156840900
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2150837211
Short name T283
Test name
Test status
Simulation time 160877446392 ps
CPU time 148.93 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:30:30 PM PDT 24
Peak memory 200780 kb
Host smart-824e12f8-be63-42e4-b9e5-d8197c0977c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150837211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2150837211
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.684916889
Short name T353
Test name
Test status
Simulation time 484215130614 ps
CPU time 1150.23 seconds
Started Mar 17 12:26:08 PM PDT 24
Finished Mar 17 12:45:19 PM PDT 24
Peak memory 201668 kb
Host smart-75b6d92e-774c-45bb-bf3e-adb5378b4a62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684916889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.684916889
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.998120538
Short name T350
Test name
Test status
Simulation time 495473700760 ps
CPU time 593.95 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:38:08 PM PDT 24
Peak memory 201696 kb
Host smart-747a5c07-40fb-407a-b04c-8e9cea16f788
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=998120538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.998120538
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.711152155
Short name T718
Test name
Test status
Simulation time 342197393553 ps
CPU time 74.36 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:29:31 PM PDT 24
Peak memory 201664 kb
Host smart-af167b0c-853d-4246-9add-69eff07c9434
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711152155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.711152155
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1558767358
Short name T775
Test name
Test status
Simulation time 398785520241 ps
CPU time 96.27 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 200160 kb
Host smart-95f4d5f2-9e26-4174-9638-1426a5ec032e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558767358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1558767358
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1356673106
Short name T177
Test name
Test status
Simulation time 127750285629 ps
CPU time 654.09 seconds
Started Mar 17 12:28:41 PM PDT 24
Finished Mar 17 12:39:37 PM PDT 24
Peak memory 202072 kb
Host smart-5c060720-df0b-4935-b614-d6aee2a5fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356673106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1356673106
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1809898585
Short name T515
Test name
Test status
Simulation time 31124266509 ps
CPU time 19.79 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 201432 kb
Host smart-9b934381-abac-4781-a2dc-94f57c16bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809898585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1809898585
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1515449031
Short name T684
Test name
Test status
Simulation time 3836260995 ps
CPU time 3.13 seconds
Started Mar 17 12:26:20 PM PDT 24
Finished Mar 17 12:26:23 PM PDT 24
Peak memory 201564 kb
Host smart-2963db90-1c7b-499b-8cf6-7563f01b1592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515449031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1515449031
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1359428534
Short name T83
Test name
Test status
Simulation time 4170003090 ps
CPU time 10.24 seconds
Started Mar 17 12:24:33 PM PDT 24
Finished Mar 17 12:24:44 PM PDT 24
Peak memory 217332 kb
Host smart-d6c5274d-3989-4f63-b5be-c31b103a3893
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359428534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1359428534
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3224254831
Short name T530
Test name
Test status
Simulation time 5923430863 ps
CPU time 14.64 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:28:19 PM PDT 24
Peak memory 200824 kb
Host smart-b7f03eca-dbe2-4245-b788-b75c1db81e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224254831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3224254831
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2070033113
Short name T770
Test name
Test status
Simulation time 415103834 ps
CPU time 1.7 seconds
Started Mar 17 12:26:25 PM PDT 24
Finished Mar 17 12:26:27 PM PDT 24
Peak memory 201600 kb
Host smart-af342bef-09b9-4a50-8c25-d962fcac3aa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070033113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2070033113
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1610337027
Short name T193
Test name
Test status
Simulation time 186489708137 ps
CPU time 156.18 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:30:42 PM PDT 24
Peak memory 201364 kb
Host smart-b5836e64-5c12-4831-bc3d-c54880cc63c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610337027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1610337027
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2446882787
Short name T246
Test name
Test status
Simulation time 327888218040 ps
CPU time 216.86 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:31:52 PM PDT 24
Peak memory 200524 kb
Host smart-99b630ae-e223-4fbb-b65e-602f5f9aadd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446882787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2446882787
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.735333995
Short name T301
Test name
Test status
Simulation time 492022680229 ps
CPU time 582.91 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:38:13 PM PDT 24
Peak memory 201700 kb
Host smart-bd788796-bd9f-48ae-bcb7-b9db814007a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735333995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.735333995
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3309162063
Short name T747
Test name
Test status
Simulation time 328896062335 ps
CPU time 399.89 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 201480 kb
Host smart-790b62e5-561c-4f12-86bb-405285d690a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309162063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3309162063
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.148157181
Short name T603
Test name
Test status
Simulation time 161228281233 ps
CPU time 75.88 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:27:26 PM PDT 24
Peak memory 201776 kb
Host smart-84338486-9ce5-4f63-8bd7-fa0566984fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148157181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.148157181
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3009150369
Short name T479
Test name
Test status
Simulation time 164563762249 ps
CPU time 186.36 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:31:12 PM PDT 24
Peak memory 201368 kb
Host smart-1b3e760e-ddd0-4810-b24d-31a1c279673e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009150369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3009150369
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1684528367
Short name T493
Test name
Test status
Simulation time 604931281991 ps
CPU time 1411.44 seconds
Started Mar 17 12:26:14 PM PDT 24
Finished Mar 17 12:49:46 PM PDT 24
Peak memory 201884 kb
Host smart-c7ee8d5b-1882-4184-acc4-27f36835514d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684528367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1684528367
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.464268407
Short name T527
Test name
Test status
Simulation time 77928367752 ps
CPU time 440.77 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 200008 kb
Host smart-9403f8cd-482e-47d5-a2a4-4125bcd36da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464268407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.464268407
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.218241686
Short name T703
Test name
Test status
Simulation time 31006099192 ps
CPU time 10.11 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 199624 kb
Host smart-b156f96c-2508-4a2d-8ca1-9754515f7f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218241686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.218241686
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3324021464
Short name T408
Test name
Test status
Simulation time 4426860534 ps
CPU time 3.37 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 201136 kb
Host smart-8a381c33-47da-42d4-9f3c-67b16faee8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324021464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3324021464
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1865195704
Short name T577
Test name
Test status
Simulation time 5588397523 ps
CPU time 4 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201176 kb
Host smart-14bc238c-f13c-46b3-b4fc-f89c40827beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865195704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1865195704
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3174262937
Short name T713
Test name
Test status
Simulation time 333051051026 ps
CPU time 1089.21 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:46:06 PM PDT 24
Peak memory 202000 kb
Host smart-ac1f4911-5e42-4bda-b02c-a7083e8903dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174262937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3174262937
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3538817414
Short name T292
Test name
Test status
Simulation time 31474350997 ps
CPU time 64.53 seconds
Started Mar 17 12:27:46 PM PDT 24
Finished Mar 17 12:28:51 PM PDT 24
Peak memory 209208 kb
Host smart-cf60e7b7-2585-490a-a8c5-24b114ef1367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538817414 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3538817414
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3252305057
Short name T558
Test name
Test status
Simulation time 324564866 ps
CPU time 1 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:24 PM PDT 24
Peak memory 201812 kb
Host smart-88225c2d-c75e-4f52-b830-c5b7bfde1973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252305057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3252305057
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.582599487
Short name T691
Test name
Test status
Simulation time 338958880120 ps
CPU time 27.35 seconds
Started Mar 17 12:26:17 PM PDT 24
Finished Mar 17 12:26:44 PM PDT 24
Peak memory 201900 kb
Host smart-26b96abe-6212-478d-8ffc-3cc472ec5f8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582599487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.582599487
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.550968028
Short name T218
Test name
Test status
Simulation time 326181953483 ps
CPU time 774.89 seconds
Started Mar 17 12:26:22 PM PDT 24
Finished Mar 17 12:39:17 PM PDT 24
Peak memory 201772 kb
Host smart-ee060244-89cb-4752-9de5-3fdfeb16c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550968028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.550968028
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.468574770
Short name T759
Test name
Test status
Simulation time 164491535668 ps
CPU time 102.23 seconds
Started Mar 17 12:26:20 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 201820 kb
Host smart-2d248440-0635-4156-a8df-7b0cb0631016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468574770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.468574770
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3995916911
Short name T464
Test name
Test status
Simulation time 488034412635 ps
CPU time 436.12 seconds
Started Mar 17 12:26:20 PM PDT 24
Finished Mar 17 12:33:37 PM PDT 24
Peak memory 201764 kb
Host smart-39a68166-ce23-4a76-8a9f-7e4f54874a27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995916911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3995916911
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.285714005
Short name T238
Test name
Test status
Simulation time 204506806598 ps
CPU time 482.29 seconds
Started Mar 17 12:26:19 PM PDT 24
Finished Mar 17 12:34:22 PM PDT 24
Peak memory 201824 kb
Host smart-84e94c38-7878-48b5-a467-ad81a5a38b3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285714005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.285714005
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2090525221
Short name T46
Test name
Test status
Simulation time 596927682261 ps
CPU time 733.31 seconds
Started Mar 17 12:26:20 PM PDT 24
Finished Mar 17 12:38:33 PM PDT 24
Peak memory 201888 kb
Host smart-2d3bf578-3103-4aa8-84e2-25f148a6034a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090525221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2090525221
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3631361169
Short name T326
Test name
Test status
Simulation time 77411001240 ps
CPU time 413.9 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:33:31 PM PDT 24
Peak memory 202068 kb
Host smart-5514cebe-2a09-40b1-a4ec-cafac3fc9ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631361169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3631361169
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1530975526
Short name T710
Test name
Test status
Simulation time 29968939853 ps
CPU time 17.04 seconds
Started Mar 17 12:26:26 PM PDT 24
Finished Mar 17 12:26:43 PM PDT 24
Peak memory 201612 kb
Host smart-75a9be41-f9dd-4def-b772-962b33619575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530975526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1530975526
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2140309868
Short name T738
Test name
Test status
Simulation time 3571194761 ps
CPU time 4.32 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:26:42 PM PDT 24
Peak memory 201472 kb
Host smart-f78a7a02-dd07-4e37-899a-02fb255e5e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140309868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2140309868
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2731262524
Short name T785
Test name
Test status
Simulation time 5927876044 ps
CPU time 11.69 seconds
Started Mar 17 12:26:23 PM PDT 24
Finished Mar 17 12:26:35 PM PDT 24
Peak memory 201552 kb
Host smart-526d25bc-0568-4fb3-8b13-34f4d20f9113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731262524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2731262524
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1419196688
Short name T719
Test name
Test status
Simulation time 180615301813 ps
CPU time 90.73 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 201300 kb
Host smart-03ac8f7b-2911-4e0a-8426-4a4c4dd8dcde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419196688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1419196688
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.23051482
Short name T761
Test name
Test status
Simulation time 490863277 ps
CPU time 1.33 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 200056 kb
Host smart-ff6acbc4-7d2f-4e8b-9a54-563e2d9b922a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.23051482
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1622782614
Short name T666
Test name
Test status
Simulation time 168057686100 ps
CPU time 375.55 seconds
Started Mar 17 12:26:35 PM PDT 24
Finished Mar 17 12:32:51 PM PDT 24
Peak memory 201852 kb
Host smart-dbc96535-093e-4119-9ca8-5fdec3439262
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622782614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1622782614
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.447865975
Short name T695
Test name
Test status
Simulation time 169542184632 ps
CPU time 398.67 seconds
Started Mar 17 12:26:37 PM PDT 24
Finished Mar 17 12:33:17 PM PDT 24
Peak memory 201896 kb
Host smart-ae6795e1-85f5-43d4-9e1d-10374a703cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447865975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.447865975
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2765072277
Short name T726
Test name
Test status
Simulation time 325853625675 ps
CPU time 97.74 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:29:39 PM PDT 24
Peak memory 201376 kb
Host smart-669296ab-5a13-4403-a55f-b6da1891c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765072277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2765072277
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.39349934
Short name T596
Test name
Test status
Simulation time 168008433890 ps
CPU time 58.68 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 200864 kb
Host smart-9bfdb11e-3b50-4dc9-adc7-c08a29768e75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt
_fixed.39349934
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.539945931
Short name T481
Test name
Test status
Simulation time 321653697029 ps
CPU time 743.95 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:40:25 PM PDT 24
Peak memory 200460 kb
Host smart-c4f63f81-4225-495c-ac55-724d31756d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539945931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.539945931
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.705148588
Short name T654
Test name
Test status
Simulation time 328526723184 ps
CPU time 795.09 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:39:52 PM PDT 24
Peak memory 201692 kb
Host smart-9befcad4-4803-4b19-b23f-4f94272d4649
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705148588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.705148588
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2313883446
Short name T269
Test name
Test status
Simulation time 344015466516 ps
CPU time 810.36 seconds
Started Mar 17 12:26:36 PM PDT 24
Finished Mar 17 12:40:07 PM PDT 24
Peak memory 201676 kb
Host smart-0bbc8189-41d8-4b32-8a6b-686715f34f0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313883446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2313883446
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1326793739
Short name T723
Test name
Test status
Simulation time 390275504571 ps
CPU time 216.52 seconds
Started Mar 17 12:26:39 PM PDT 24
Finished Mar 17 12:30:17 PM PDT 24
Peak memory 201884 kb
Host smart-5ca73706-7896-4007-98df-1699435c128f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326793739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1326793739
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.510105620
Short name T631
Test name
Test status
Simulation time 134597603182 ps
CPU time 522.54 seconds
Started Mar 17 12:26:31 PM PDT 24
Finished Mar 17 12:35:14 PM PDT 24
Peak memory 202192 kb
Host smart-608014d2-f762-4922-8b21-c2e8e05d09d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510105620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.510105620
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.770630682
Short name T395
Test name
Test status
Simulation time 32381683617 ps
CPU time 12.93 seconds
Started Mar 17 12:26:34 PM PDT 24
Finished Mar 17 12:26:47 PM PDT 24
Peak memory 201472 kb
Host smart-6b53a54a-7083-4dd3-8971-bcfc5535cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770630682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.770630682
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.71769654
Short name T419
Test name
Test status
Simulation time 5377770113 ps
CPU time 13.06 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:28:14 PM PDT 24
Peak memory 200928 kb
Host smart-61ac1825-91cb-4494-bd71-7db8047cdab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71769654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.71769654
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.4202406746
Short name T776
Test name
Test status
Simulation time 5786158132 ps
CPU time 4.38 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:38 PM PDT 24
Peak memory 201524 kb
Host smart-8e9aa0ab-3403-4f7d-b9aa-aa4482ae2bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202406746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.4202406746
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.706079371
Short name T15
Test name
Test status
Simulation time 284431447158 ps
CPU time 174.93 seconds
Started Mar 17 12:26:39 PM PDT 24
Finished Mar 17 12:29:35 PM PDT 24
Peak memory 210608 kb
Host smart-18e79fe9-4160-4411-9e90-2b70f2f276d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706079371 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.706079371
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2041192919
Short name T520
Test name
Test status
Simulation time 374087744 ps
CPU time 1.5 seconds
Started Mar 17 12:26:47 PM PDT 24
Finished Mar 17 12:26:48 PM PDT 24
Peak memory 201468 kb
Host smart-10292239-3d5f-4f74-9e31-1eb90282e498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041192919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2041192919
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1699968303
Short name T299
Test name
Test status
Simulation time 164519731251 ps
CPU time 28.02 seconds
Started Mar 17 12:26:40 PM PDT 24
Finished Mar 17 12:27:08 PM PDT 24
Peak memory 201852 kb
Host smart-7b742367-19fe-452b-99bd-016fe6350543
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699968303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1699968303
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.942154719
Short name T253
Test name
Test status
Simulation time 329646684083 ps
CPU time 738.58 seconds
Started Mar 17 12:26:37 PM PDT 24
Finished Mar 17 12:38:57 PM PDT 24
Peak memory 201768 kb
Host smart-d38e6a7e-1754-47ad-bc79-50e0e727a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942154719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.942154719
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1648954013
Short name T129
Test name
Test status
Simulation time 326178512461 ps
CPU time 383.12 seconds
Started Mar 17 12:28:39 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 201660 kb
Host smart-55629186-8939-47d7-95f1-e081792d771d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648954013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1648954013
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2791659163
Short name T167
Test name
Test status
Simulation time 328884967919 ps
CPU time 47 seconds
Started Mar 17 12:26:42 PM PDT 24
Finished Mar 17 12:27:29 PM PDT 24
Peak memory 201668 kb
Host smart-581de533-0bdb-4551-9564-ad685f65454a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791659163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2791659163
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1710451876
Short name T488
Test name
Test status
Simulation time 505100668644 ps
CPU time 585.61 seconds
Started Mar 17 12:26:38 PM PDT 24
Finished Mar 17 12:36:24 PM PDT 24
Peak memory 201828 kb
Host smart-84665879-3a63-423f-9d6a-8bbfcf2fdadc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710451876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1710451876
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4248663976
Short name T446
Test name
Test status
Simulation time 187607416708 ps
CPU time 113.94 seconds
Started Mar 17 12:26:40 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 201820 kb
Host smart-c3456686-199f-4790-9c77-bfcc7019f1a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248663976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4248663976
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2159987270
Short name T503
Test name
Test status
Simulation time 398455541744 ps
CPU time 435.62 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 201100 kb
Host smart-7b6c0a1b-e370-4a92-93d2-d359bfc71e65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159987270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2159987270
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1310867590
Short name T174
Test name
Test status
Simulation time 99394928392 ps
CPU time 509.53 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 202020 kb
Host smart-29098492-2595-4932-8cf6-552cf24c0867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310867590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1310867590
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2397428580
Short name T752
Test name
Test status
Simulation time 44919983798 ps
CPU time 20.45 seconds
Started Mar 17 12:26:46 PM PDT 24
Finished Mar 17 12:27:07 PM PDT 24
Peak memory 201480 kb
Host smart-94841f2b-85f2-4391-ab0e-fb882dc9a5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397428580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2397428580
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2705607522
Short name T358
Test name
Test status
Simulation time 3222904688 ps
CPU time 6.47 seconds
Started Mar 17 12:26:37 PM PDT 24
Finished Mar 17 12:26:45 PM PDT 24
Peak memory 201872 kb
Host smart-2745b474-13a1-430c-acad-d00ca0831b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705607522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2705607522
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2804573080
Short name T540
Test name
Test status
Simulation time 5539730454 ps
CPU time 13.86 seconds
Started Mar 17 12:26:37 PM PDT 24
Finished Mar 17 12:26:53 PM PDT 24
Peak memory 201640 kb
Host smart-747090b1-49fc-49b1-866b-8f902400063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804573080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2804573080
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3583752669
Short name T645
Test name
Test status
Simulation time 383490164 ps
CPU time 1.46 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:26:54 PM PDT 24
Peak memory 201524 kb
Host smart-8964d4cc-6c5f-44c9-9737-483f131c01ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583752669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3583752669
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2915931207
Short name T781
Test name
Test status
Simulation time 491623159604 ps
CPU time 1114.47 seconds
Started Mar 17 12:26:42 PM PDT 24
Finished Mar 17 12:45:17 PM PDT 24
Peak memory 201824 kb
Host smart-13995f3f-8728-4189-a24d-017978e55f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915931207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2915931207
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3368337666
Short name T186
Test name
Test status
Simulation time 168780318093 ps
CPU time 419.52 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:35:22 PM PDT 24
Peak memory 200924 kb
Host smart-f46e0f2f-bbbf-4df7-a101-c820d00d04cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368337666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3368337666
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.262690413
Short name T151
Test name
Test status
Simulation time 162256801087 ps
CPU time 198.04 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:30:16 PM PDT 24
Peak memory 201752 kb
Host smart-fc96accd-3d13-4bd4-aae0-f5cc149fd867
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=262690413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.262690413
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.639785955
Short name T624
Test name
Test status
Simulation time 485948349970 ps
CPU time 547.97 seconds
Started Mar 17 12:26:57 PM PDT 24
Finished Mar 17 12:36:05 PM PDT 24
Peak memory 201740 kb
Host smart-a2fc8d31-6beb-42e3-ba08-25e24c3169bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639785955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.639785955
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1230226791
Short name T388
Test name
Test status
Simulation time 479180223217 ps
CPU time 1073.63 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:44:52 PM PDT 24
Peak memory 201884 kb
Host smart-2ac1939a-f1de-4ba4-ba0e-9e0466a0e49c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230226791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1230226791
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3547958646
Short name T209
Test name
Test status
Simulation time 179256971913 ps
CPU time 80.48 seconds
Started Mar 17 12:26:50 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201788 kb
Host smart-2051f7c1-d982-43f5-852d-ad872d011726
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547958646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3547958646
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2142907555
Short name T372
Test name
Test status
Simulation time 209914217969 ps
CPU time 144.4 seconds
Started Mar 17 12:26:47 PM PDT 24
Finished Mar 17 12:29:11 PM PDT 24
Peak memory 201796 kb
Host smart-4b4627e8-ab9a-447e-9aaa-aeafa8a16925
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142907555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2142907555
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1031777523
Short name T53
Test name
Test status
Simulation time 115320042478 ps
CPU time 508.94 seconds
Started Mar 17 12:26:56 PM PDT 24
Finished Mar 17 12:35:25 PM PDT 24
Peak memory 202060 kb
Host smart-284d367d-125b-4474-8787-1d25bac4ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031777523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1031777523
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3792517752
Short name T668
Test name
Test status
Simulation time 34298514321 ps
CPU time 42.83 seconds
Started Mar 17 12:26:50 PM PDT 24
Finished Mar 17 12:27:33 PM PDT 24
Peak memory 201496 kb
Host smart-bd366ec1-8122-4629-92a2-e65e26a87843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792517752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3792517752
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1588029399
Short name T428
Test name
Test status
Simulation time 4465390654 ps
CPU time 5.86 seconds
Started Mar 17 12:26:51 PM PDT 24
Finished Mar 17 12:26:57 PM PDT 24
Peak memory 201532 kb
Host smart-34961ecb-9014-427d-b31a-e8f0d913e24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588029399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1588029399
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4160756495
Short name T702
Test name
Test status
Simulation time 5952474253 ps
CPU time 4.38 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:27:02 PM PDT 24
Peak memory 201572 kb
Host smart-ba543c70-d624-481a-a559-79d2b5d0378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160756495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4160756495
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3203616832
Short name T466
Test name
Test status
Simulation time 318840338 ps
CPU time 1.37 seconds
Started Mar 17 12:26:55 PM PDT 24
Finished Mar 17 12:26:56 PM PDT 24
Peak memory 201396 kb
Host smart-a933fe71-4fa1-4047-9768-f4d8e46464ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203616832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3203616832
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2571608500
Short name T203
Test name
Test status
Simulation time 201200408589 ps
CPU time 234.48 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:30:53 PM PDT 24
Peak memory 201892 kb
Host smart-5d95ab61-249d-48dc-a895-b6a4f690a825
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571608500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2571608500
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.988724848
Short name T170
Test name
Test status
Simulation time 322855227518 ps
CPU time 200.5 seconds
Started Mar 17 12:26:57 PM PDT 24
Finished Mar 17 12:30:18 PM PDT 24
Peak memory 201732 kb
Host smart-eb4a9386-e49d-4ec1-b06c-04c6f299520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988724848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.988724848
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1834380755
Short name T542
Test name
Test status
Simulation time 498828386268 ps
CPU time 396.56 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:33:29 PM PDT 24
Peak memory 201884 kb
Host smart-3ce1d4e6-6523-4720-9f14-27a268a293f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834380755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1834380755
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.916179334
Short name T263
Test name
Test status
Simulation time 490222606060 ps
CPU time 329.46 seconds
Started Mar 17 12:26:57 PM PDT 24
Finished Mar 17 12:32:27 PM PDT 24
Peak memory 201728 kb
Host smart-fe7e6b17-8351-4ada-9c32-eb11cca4cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916179334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.916179334
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3794417826
Short name T615
Test name
Test status
Simulation time 492046509520 ps
CPU time 1085.28 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:45:03 PM PDT 24
Peak memory 201840 kb
Host smart-8ccdf21e-564f-4b5c-9933-015d42d7e46e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794417826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3794417826
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.708222185
Short name T748
Test name
Test status
Simulation time 199739725112 ps
CPU time 449.14 seconds
Started Mar 17 12:26:55 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 201692 kb
Host smart-853a44eb-4524-43ac-b8d9-cb93ba9118bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708222185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.708222185
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1681944583
Short name T377
Test name
Test status
Simulation time 404829784068 ps
CPU time 965.53 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:43:37 PM PDT 24
Peak memory 201728 kb
Host smart-0634276f-5093-4a14-ba82-0129dee8414b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681944583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1681944583
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.653392285
Short name T721
Test name
Test status
Simulation time 112297756005 ps
CPU time 449.56 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:34:28 PM PDT 24
Peak memory 202136 kb
Host smart-b1d46d5a-6370-45ec-803a-3250c0078d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653392285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.653392285
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3366474599
Short name T396
Test name
Test status
Simulation time 34102709574 ps
CPU time 40.93 seconds
Started Mar 17 12:27:38 PM PDT 24
Finished Mar 17 12:28:19 PM PDT 24
Peak memory 201592 kb
Host smart-9a6f64b8-97c7-45b1-9f13-540cc0dfe22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366474599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3366474599
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2513068228
Short name T482
Test name
Test status
Simulation time 3254455928 ps
CPU time 1.29 seconds
Started Mar 17 12:27:02 PM PDT 24
Finished Mar 17 12:27:05 PM PDT 24
Peak memory 201188 kb
Host smart-77ab572b-6b6a-4af0-b40a-63196b42df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513068228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2513068228
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.948577450
Short name T373
Test name
Test status
Simulation time 5662647040 ps
CPU time 14.61 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:29:04 PM PDT 24
Peak memory 201520 kb
Host smart-0beed97e-b5e5-49b1-bf64-8bd516abc13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948577450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.948577450
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2991022723
Short name T70
Test name
Test status
Simulation time 6198223045 ps
CPU time 2.99 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:27:07 PM PDT 24
Peak memory 201480 kb
Host smart-ced2584f-a598-4769-91d3-cad267292fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991022723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2991022723
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.534602003
Short name T555
Test name
Test status
Simulation time 547639814 ps
CPU time 0.85 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:35 PM PDT 24
Peak memory 201016 kb
Host smart-d4845707-2760-4b4c-8c79-d3de6426b925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534602003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.534602003
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.503355842
Short name T690
Test name
Test status
Simulation time 162444975547 ps
CPU time 355.5 seconds
Started Mar 17 12:26:54 PM PDT 24
Finished Mar 17 12:32:50 PM PDT 24
Peak memory 201984 kb
Host smart-f1754002-cdf2-4ec0-a0eb-f8e9a0e6d5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503355842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.503355842
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3372581066
Short name T714
Test name
Test status
Simulation time 503161683039 ps
CPU time 428.82 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:34:13 PM PDT 24
Peak memory 201500 kb
Host smart-db057f33-6bd3-4699-9343-54596d4ba691
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372581066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3372581066
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2134691072
Short name T549
Test name
Test status
Simulation time 488830784003 ps
CPU time 597.22 seconds
Started Mar 17 12:27:39 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 201752 kb
Host smart-bcd4124b-6b96-4b49-aada-8bff03da5fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134691072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2134691072
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2203597312
Short name T532
Test name
Test status
Simulation time 175416637065 ps
CPU time 424.26 seconds
Started Mar 17 12:27:02 PM PDT 24
Finished Mar 17 12:34:08 PM PDT 24
Peak memory 201520 kb
Host smart-b3e8fc8f-2229-456e-817b-27927784eaf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203597312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2203597312
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3241860877
Short name T667
Test name
Test status
Simulation time 366586878268 ps
CPU time 412.46 seconds
Started Mar 17 12:27:30 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 201972 kb
Host smart-35f5dd92-74d2-4057-8bec-d14ee0fb8268
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241860877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3241860877
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3301551513
Short name T526
Test name
Test status
Simulation time 591363594447 ps
CPU time 1318.07 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:49:16 PM PDT 24
Peak memory 201788 kb
Host smart-205c798e-4fdf-4a66-8ce3-58308bfcbec2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301551513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3301551513
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3997698260
Short name T173
Test name
Test status
Simulation time 111750663119 ps
CPU time 377.32 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:33:30 PM PDT 24
Peak memory 201996 kb
Host smart-54464776-1443-4f74-ace4-d4d2607f3ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997698260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3997698260
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3658513921
Short name T656
Test name
Test status
Simulation time 29762486103 ps
CPU time 65.35 seconds
Started Mar 17 12:26:55 PM PDT 24
Finished Mar 17 12:28:01 PM PDT 24
Peak memory 201532 kb
Host smart-33049280-e570-454b-b4c4-adf50291b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658513921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3658513921
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.71371873
Short name T331
Test name
Test status
Simulation time 5073719238 ps
CPU time 3.35 seconds
Started Mar 17 12:26:58 PM PDT 24
Finished Mar 17 12:27:01 PM PDT 24
Peak memory 201620 kb
Host smart-6636c076-4dc9-460f-8eb7-cc47b6a2408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71371873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.71371873
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3141564652
Short name T351
Test name
Test status
Simulation time 5515409567 ps
CPU time 5.94 seconds
Started Mar 17 12:26:52 PM PDT 24
Finished Mar 17 12:26:58 PM PDT 24
Peak memory 201536 kb
Host smart-8e3a11bc-dff9-4995-b0f2-dcd78af92696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141564652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3141564652
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2821344217
Short name T13
Test name
Test status
Simulation time 152415999784 ps
CPU time 95.97 seconds
Started Mar 17 12:27:07 PM PDT 24
Finished Mar 17 12:28:43 PM PDT 24
Peak memory 210396 kb
Host smart-7c9303d7-d392-4faa-a732-517303db5f3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821344217 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2821344217
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2775058946
Short name T665
Test name
Test status
Simulation time 437878721 ps
CPU time 0.84 seconds
Started Mar 17 12:27:02 PM PDT 24
Finished Mar 17 12:27:03 PM PDT 24
Peak memory 201328 kb
Host smart-2b853972-9257-4990-afc0-5bf483b81d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775058946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2775058946
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1960219062
Short name T162
Test name
Test status
Simulation time 525861302394 ps
CPU time 294.65 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:32:00 PM PDT 24
Peak memory 201784 kb
Host smart-f05c2982-fc27-408e-97e3-76132a822109
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960219062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1960219062
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2640614330
Short name T644
Test name
Test status
Simulation time 165790639610 ps
CPU time 354.64 seconds
Started Mar 17 12:26:56 PM PDT 24
Finished Mar 17 12:32:51 PM PDT 24
Peak memory 201820 kb
Host smart-39705642-9b1c-4110-8ebc-1100a2ee69a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640614330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2640614330
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1644273181
Short name T525
Test name
Test status
Simulation time 164956872362 ps
CPU time 98.66 seconds
Started Mar 17 12:27:02 PM PDT 24
Finished Mar 17 12:28:41 PM PDT 24
Peak memory 201692 kb
Host smart-3e10c922-5ef3-4dbe-ad55-d6b9e3c38bb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644273181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1644273181
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3738665819
Short name T288
Test name
Test status
Simulation time 323096596592 ps
CPU time 780.32 seconds
Started Mar 17 12:26:57 PM PDT 24
Finished Mar 17 12:39:58 PM PDT 24
Peak memory 201816 kb
Host smart-bc5e9bb8-75ff-4637-8ac5-273c531e0a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738665819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3738665819
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.588929159
Short name T593
Test name
Test status
Simulation time 494362241724 ps
CPU time 1188.14 seconds
Started Mar 17 12:26:56 PM PDT 24
Finished Mar 17 12:46:44 PM PDT 24
Peak memory 202112 kb
Host smart-4ad87d91-eb2d-4376-81ae-ad2c06d5f4d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=588929159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.588929159
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2758966706
Short name T673
Test name
Test status
Simulation time 569329669267 ps
CPU time 666.7 seconds
Started Mar 17 12:27:07 PM PDT 24
Finished Mar 17 12:38:15 PM PDT 24
Peak memory 201712 kb
Host smart-8196dacb-3aab-4051-b132-59eeeb47a6ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758966706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2758966706
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2640726844
Short name T553
Test name
Test status
Simulation time 200194905645 ps
CPU time 421.55 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:34:05 PM PDT 24
Peak memory 201640 kb
Host smart-f072ae03-2b01-4729-a180-46ab37144fed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640726844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2640726844
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1340692262
Short name T49
Test name
Test status
Simulation time 130312234769 ps
CPU time 703.41 seconds
Started Mar 17 12:27:44 PM PDT 24
Finished Mar 17 12:39:28 PM PDT 24
Peak memory 202100 kb
Host smart-9267a18b-47c4-4020-ac23-f8a22636dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340692262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1340692262
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3365930489
Short name T659
Test name
Test status
Simulation time 25973309103 ps
CPU time 64.39 seconds
Started Mar 17 12:26:57 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 201508 kb
Host smart-135f0e53-fe47-4b10-a7bc-4a7c3c9bf38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365930489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3365930489
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4190422956
Short name T569
Test name
Test status
Simulation time 3017298826 ps
CPU time 1.8 seconds
Started Mar 17 12:27:06 PM PDT 24
Finished Mar 17 12:27:09 PM PDT 24
Peak memory 201436 kb
Host smart-59b4e382-5cb6-4350-b5d7-eb5e8012ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190422956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4190422956
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.742461156
Short name T333
Test name
Test status
Simulation time 6000034249 ps
CPU time 4.25 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:38 PM PDT 24
Peak memory 201040 kb
Host smart-c9dbbccb-8b93-4f64-b430-d1f6f7a221b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742461156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.742461156
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1872102386
Short name T636
Test name
Test status
Simulation time 167482800168 ps
CPU time 105.87 seconds
Started Mar 17 12:27:44 PM PDT 24
Finished Mar 17 12:29:30 PM PDT 24
Peak memory 201760 kb
Host smart-95dba86d-1c2f-4844-844c-9878834df986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872102386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1872102386
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.687895646
Short name T535
Test name
Test status
Simulation time 403544795 ps
CPU time 1.53 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:27:07 PM PDT 24
Peak memory 201472 kb
Host smart-0baf68f4-28ce-4d2c-88d1-1d0d80520f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687895646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.687895646
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1507717503
Short name T260
Test name
Test status
Simulation time 200773564006 ps
CPU time 109.33 seconds
Started Mar 17 12:27:51 PM PDT 24
Finished Mar 17 12:29:41 PM PDT 24
Peak memory 201804 kb
Host smart-786df1cc-20bb-44fb-90f4-9c8f88ad7315
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507717503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1507717503
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.536167377
Short name T693
Test name
Test status
Simulation time 566136631674 ps
CPU time 1305.42 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:50:19 PM PDT 24
Peak memory 200836 kb
Host smart-8046712e-fabf-49b9-a306-910fb148c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536167377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.536167377
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.343383302
Short name T454
Test name
Test status
Simulation time 504010300580 ps
CPU time 1087.12 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:45:11 PM PDT 24
Peak memory 201456 kb
Host smart-56e005fa-0a49-430f-b414-f8804b12784a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=343383302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.343383302
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2728169508
Short name T156
Test name
Test status
Simulation time 332346301075 ps
CPU time 78.4 seconds
Started Mar 17 12:27:12 PM PDT 24
Finished Mar 17 12:28:31 PM PDT 24
Peak memory 201684 kb
Host smart-814cb8b9-0419-4357-8f17-aedf2b84cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728169508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2728169508
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3389062673
Short name T468
Test name
Test status
Simulation time 326837767111 ps
CPU time 80.31 seconds
Started Mar 17 12:27:54 PM PDT 24
Finished Mar 17 12:29:14 PM PDT 24
Peak memory 201744 kb
Host smart-baf8a243-7446-4f99-a1b7-6b6a84d1c2c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389062673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3389062673
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.4181571032
Short name T140
Test name
Test status
Simulation time 524573243746 ps
CPU time 299.84 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:32:04 PM PDT 24
Peak memory 201756 kb
Host smart-7372548e-9328-43c8-bcac-f26ef9587397
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181571032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.4181571032
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2553535812
Short name T506
Test name
Test status
Simulation time 404783149836 ps
CPU time 868.77 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:43:03 PM PDT 24
Peak memory 201044 kb
Host smart-6353eedc-2cf2-49d3-bf31-8ffe73221817
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553535812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2553535812
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1327248334
Short name T176
Test name
Test status
Simulation time 74294126619 ps
CPU time 299.1 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:32:13 PM PDT 24
Peak memory 201984 kb
Host smart-7dcae55c-8a26-433c-af00-39a3f93633f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327248334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1327248334
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3221238412
Short name T389
Test name
Test status
Simulation time 32278641994 ps
CPU time 18.99 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 201508 kb
Host smart-f8bd6bb7-020e-4700-a323-c5d0cdf9a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221238412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3221238412
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2512054570
Short name T427
Test name
Test status
Simulation time 4030046869 ps
CPU time 3.38 seconds
Started Mar 17 12:27:13 PM PDT 24
Finished Mar 17 12:27:16 PM PDT 24
Peak memory 201452 kb
Host smart-0d1088c5-8e0c-4fb4-8f1d-aa5798067d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512054570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2512054570
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3094898276
Short name T451
Test name
Test status
Simulation time 5737477466 ps
CPU time 4.33 seconds
Started Mar 17 12:27:06 PM PDT 24
Finished Mar 17 12:27:11 PM PDT 24
Peak memory 201520 kb
Host smart-3c75a224-94ae-4ebc-a23e-9546071e049d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094898276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3094898276
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2828753408
Short name T547
Test name
Test status
Simulation time 88190692672 ps
CPU time 109.69 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:29:06 PM PDT 24
Peak memory 201688 kb
Host smart-eb5eca8f-7493-4bf8-bae0-c39bc48ac822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828753408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2828753408
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.75517111
Short name T393
Test name
Test status
Simulation time 499694020 ps
CPU time 1.85 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 201156 kb
Host smart-4a0d46cb-2175-48c9-9eec-191c04c0e273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75517111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.75517111
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1321881004
Short name T648
Test name
Test status
Simulation time 164831090451 ps
CPU time 356 seconds
Started Mar 17 12:27:06 PM PDT 24
Finished Mar 17 12:33:03 PM PDT 24
Peak memory 201892 kb
Host smart-b85bbfae-dfb1-4360-9b9b-7d71e8585f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321881004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1321881004
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.646570628
Short name T406
Test name
Test status
Simulation time 492741339330 ps
CPU time 602.62 seconds
Started Mar 17 12:27:04 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 201760 kb
Host smart-bdba84dd-e73d-421b-9be0-571086edf4a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=646570628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.646570628
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2644763574
Short name T403
Test name
Test status
Simulation time 161126136886 ps
CPU time 357.91 seconds
Started Mar 17 12:27:16 PM PDT 24
Finished Mar 17 12:33:14 PM PDT 24
Peak memory 201612 kb
Host smart-d9931dc5-66fc-4c5f-888f-7c8d0e68423f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644763574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2644763574
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1932332983
Short name T364
Test name
Test status
Simulation time 160163828841 ps
CPU time 386.85 seconds
Started Mar 17 12:27:16 PM PDT 24
Finished Mar 17 12:33:43 PM PDT 24
Peak memory 201768 kb
Host smart-d709344c-3d51-42dc-bccd-74a156bf93be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932332983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1932332983
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.413340198
Short name T304
Test name
Test status
Simulation time 185512226820 ps
CPU time 237.04 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:31:14 PM PDT 24
Peak memory 201460 kb
Host smart-f6d633f2-4d09-4c77-97a6-9d5539694305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413340198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.413340198
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3210113067
Short name T425
Test name
Test status
Simulation time 596260409937 ps
CPU time 1252.1 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:48:09 PM PDT 24
Peak memory 201340 kb
Host smart-bb657c55-47ea-457b-b02d-4de72c99a392
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210113067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3210113067
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3595024239
Short name T442
Test name
Test status
Simulation time 124862462047 ps
CPU time 598.92 seconds
Started Mar 17 12:27:03 PM PDT 24
Finished Mar 17 12:37:03 PM PDT 24
Peak memory 202112 kb
Host smart-b21527df-a6cf-4cb1-8fae-8916ca4ac480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595024239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3595024239
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.4230434296
Short name T407
Test name
Test status
Simulation time 39031853683 ps
CPU time 14.75 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 201432 kb
Host smart-c86b3cfb-8672-4271-8528-323878cea18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230434296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.4230434296
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2034534926
Short name T441
Test name
Test status
Simulation time 4715596728 ps
CPU time 10.69 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:27:28 PM PDT 24
Peak memory 201432 kb
Host smart-4f2c9372-3ffe-40e8-b0a9-671ae5eedbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034534926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2034534926
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.626636034
Short name T663
Test name
Test status
Simulation time 5669145835 ps
CPU time 7.95 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:23 PM PDT 24
Peak memory 201388 kb
Host smart-f5fdf900-e65a-47ee-b9eb-f20cf2290e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626636034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.626636034
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.96893919
Short name T507
Test name
Test status
Simulation time 380021181184 ps
CPU time 92.75 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:29:34 PM PDT 24
Peak memory 201616 kb
Host smart-a8d6f7b7-24a5-4022-b967-6cbbacedc971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96893919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.96893919
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1474995355
Short name T257
Test name
Test status
Simulation time 284631857770 ps
CPU time 363.38 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:33:20 PM PDT 24
Peak memory 210540 kb
Host smart-458f29e1-7cca-4346-b86c-0d85abe3d36b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474995355 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1474995355
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.941193883
Short name T746
Test name
Test status
Simulation time 532441918 ps
CPU time 1.57 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:27:51 PM PDT 24
Peak memory 200092 kb
Host smart-3f7b418e-0c30-4466-a134-747170a9c300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941193883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.941193883
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1817493803
Short name T282
Test name
Test status
Simulation time 519154523808 ps
CPU time 507.48 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:36:23 PM PDT 24
Peak memory 200824 kb
Host smart-94225f03-49d0-406a-b053-e76e976a4532
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817493803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1817493803
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.259407785
Short name T501
Test name
Test status
Simulation time 168675580872 ps
CPU time 404.72 seconds
Started Mar 17 12:25:25 PM PDT 24
Finished Mar 17 12:32:10 PM PDT 24
Peak memory 201704 kb
Host smart-fdaecb1e-684c-4d20-b2ea-361c4fccf9d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=259407785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt
_fixed.259407785
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1892142252
Short name T732
Test name
Test status
Simulation time 323355737339 ps
CPU time 693.16 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:39:05 PM PDT 24
Peak memory 201612 kb
Host smart-660756f2-ebca-4eb7-837b-e490ed6cb61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892142252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1892142252
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3779266381
Short name T88
Test name
Test status
Simulation time 328212131492 ps
CPU time 167.5 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:30:51 PM PDT 24
Peak memory 201668 kb
Host smart-1110f060-b48d-4ba0-bdba-86b231720de5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779266381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3779266381
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4154596614
Short name T297
Test name
Test status
Simulation time 313871386857 ps
CPU time 729.52 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:40:18 PM PDT 24
Peak memory 201636 kb
Host smart-f8c49963-e99b-4a51-9519-024c75f0e015
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154596614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4154596614
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1827876457
Short name T379
Test name
Test status
Simulation time 192550592322 ps
CPU time 318.55 seconds
Started Mar 17 12:25:56 PM PDT 24
Finished Mar 17 12:31:15 PM PDT 24
Peak memory 201748 kb
Host smart-facae7b7-c8a6-45ba-9b9c-34c5e3772c90
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827876457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1827876457
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3397999699
Short name T27
Test name
Test status
Simulation time 99675235130 ps
CPU time 497.75 seconds
Started Mar 17 12:25:53 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 202004 kb
Host smart-9d233804-138a-4b31-8560-a17b17730d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397999699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3397999699
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3408511832
Short name T402
Test name
Test status
Simulation time 22354931194 ps
CPU time 56.32 seconds
Started Mar 17 12:25:20 PM PDT 24
Finished Mar 17 12:26:17 PM PDT 24
Peak memory 201608 kb
Host smart-7e4506ef-2da9-4c35-b73b-87258f696e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408511832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3408511832
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1059009514
Short name T486
Test name
Test status
Simulation time 5384311779 ps
CPU time 14.83 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 200428 kb
Host smart-faaa747d-50ab-4921-827b-1754d39950ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059009514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1059009514
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3152064973
Short name T82
Test name
Test status
Simulation time 4137383712 ps
CPU time 10.52 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 216088 kb
Host smart-515213d5-76e8-42cf-a357-a7fabfb58bd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152064973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3152064973
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4254744742
Short name T474
Test name
Test status
Simulation time 5794399346 ps
CPU time 3.45 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:24:33 PM PDT 24
Peak memory 201536 kb
Host smart-d0a367a1-2b09-43b3-9148-707c10976a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254744742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4254744742
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2308781870
Short name T290
Test name
Test status
Simulation time 442587276841 ps
CPU time 1440.93 seconds
Started Mar 17 12:27:55 PM PDT 24
Finished Mar 17 12:51:57 PM PDT 24
Peak memory 202092 kb
Host smart-809f3f25-c5f9-4ef2-90df-503c624bf973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308781870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2308781870
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4091050387
Short name T611
Test name
Test status
Simulation time 311801319 ps
CPU time 1.37 seconds
Started Mar 17 12:27:26 PM PDT 24
Finished Mar 17 12:27:28 PM PDT 24
Peak memory 201408 kb
Host smart-32bedd46-1c35-40b6-a171-594aeb4eb572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091050387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4091050387
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2601230105
Short name T166
Test name
Test status
Simulation time 332695657767 ps
CPU time 180.5 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:30:18 PM PDT 24
Peak memory 201696 kb
Host smart-9df2eff9-360a-42b4-a00f-cc7468d0f635
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601230105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2601230105
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1715364104
Short name T478
Test name
Test status
Simulation time 163193579100 ps
CPU time 192.49 seconds
Started Mar 17 12:27:17 PM PDT 24
Finished Mar 17 12:30:30 PM PDT 24
Peak memory 201692 kb
Host smart-bc473e4b-3b5f-478a-8e5d-b7d20fea8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715364104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1715364104
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1394066453
Short name T30
Test name
Test status
Simulation time 335263638182 ps
CPU time 215.11 seconds
Started Mar 17 12:27:11 PM PDT 24
Finished Mar 17 12:30:47 PM PDT 24
Peak memory 201676 kb
Host smart-f89a9fc9-e9ef-424a-a23b-1e7496ee569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394066453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1394066453
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2635586181
Short name T604
Test name
Test status
Simulation time 487708406818 ps
CPU time 279 seconds
Started Mar 17 12:27:11 PM PDT 24
Finished Mar 17 12:31:50 PM PDT 24
Peak memory 201684 kb
Host smart-27b08c77-acfc-47ad-b6f3-054a20f9405c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635586181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2635586181
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.4153080736
Short name T300
Test name
Test status
Simulation time 337028622038 ps
CPU time 736.55 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:40:17 PM PDT 24
Peak memory 201764 kb
Host smart-21fcbb1e-9ec4-4d4e-afaf-ac94a87e8d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153080736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.4153080736
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3418890035
Short name T494
Test name
Test status
Simulation time 166878488812 ps
CPU time 336.7 seconds
Started Mar 17 12:27:15 PM PDT 24
Finished Mar 17 12:32:52 PM PDT 24
Peak memory 201792 kb
Host smart-f0d8e0af-863f-4139-9116-6678cc4b637f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418890035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3418890035
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.938173107
Short name T323
Test name
Test status
Simulation time 96338701923 ps
CPU time 410.24 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:34:55 PM PDT 24
Peak memory 201960 kb
Host smart-a498d9f9-46b8-4733-89c6-11c0b74fdc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938173107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.938173107
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3696599095
Short name T327
Test name
Test status
Simulation time 35671852579 ps
CPU time 83.07 seconds
Started Mar 17 12:27:38 PM PDT 24
Finished Mar 17 12:29:01 PM PDT 24
Peak memory 201540 kb
Host smart-74c5cb46-d71a-4ecd-9dc0-7bd87b53bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696599095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3696599095
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.661618343
Short name T533
Test name
Test status
Simulation time 4023394537 ps
CPU time 8.16 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201528 kb
Host smart-37fefdf1-d9fd-412e-b035-c75fc4c1c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661618343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.661618343
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1442342703
Short name T755
Test name
Test status
Simulation time 5908609380 ps
CPU time 14.49 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:29 PM PDT 24
Peak memory 201404 kb
Host smart-cdff70e8-5ef4-4a54-9197-61baa08143b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442342703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1442342703
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.111065975
Short name T40
Test name
Test status
Simulation time 5248263383 ps
CPU time 11.26 seconds
Started Mar 17 12:27:15 PM PDT 24
Finished Mar 17 12:27:27 PM PDT 24
Peak memory 201964 kb
Host smart-87b4da2c-cff7-43cc-8ba5-05fa6d0ece47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111065975 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.111065975
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3785435780
Short name T197
Test name
Test status
Simulation time 360972475616 ps
CPU time 440 seconds
Started Mar 17 12:27:25 PM PDT 24
Finished Mar 17 12:34:46 PM PDT 24
Peak memory 201700 kb
Host smart-12ea3857-99eb-40a5-83d8-149226463ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785435780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3785435780
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1215787945
Short name T165
Test name
Test status
Simulation time 164794263802 ps
CPU time 105.51 seconds
Started Mar 17 12:27:20 PM PDT 24
Finished Mar 17 12:29:05 PM PDT 24
Peak memory 201704 kb
Host smart-0604ae4d-e56b-4828-9419-ff6aa39d0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215787945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1215787945
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2470844848
Short name T613
Test name
Test status
Simulation time 491481425298 ps
CPU time 224.96 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:32:10 PM PDT 24
Peak memory 201564 kb
Host smart-bd4c032e-5146-4239-a0f6-b7178782f39e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470844848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2470844848
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1890745641
Short name T185
Test name
Test status
Simulation time 493779389844 ps
CPU time 104.17 seconds
Started Mar 17 12:28:23 PM PDT 24
Finished Mar 17 12:30:08 PM PDT 24
Peak memory 201744 kb
Host smart-3e307bf6-9a4b-4aa0-930f-49e19fba1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890745641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1890745641
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2418641057
Short name T734
Test name
Test status
Simulation time 162058197322 ps
CPU time 185.22 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:31:31 PM PDT 24
Peak memory 201652 kb
Host smart-e3f36602-c4ab-4937-9b99-c90b8a30c937
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418641057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2418641057
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1168288886
Short name T554
Test name
Test status
Simulation time 602244033431 ps
CPU time 1428.5 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:52:11 PM PDT 24
Peak memory 201448 kb
Host smart-fcb4a7af-7c6c-48f8-ac97-293d619f1566
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168288886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1168288886
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2601871741
Short name T662
Test name
Test status
Simulation time 89178051938 ps
CPU time 444.49 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:34:56 PM PDT 24
Peak memory 202240 kb
Host smart-704ad62f-4064-4de5-aa80-419b0be1f5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601871741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2601871741
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.204061218
Short name T642
Test name
Test status
Simulation time 36824394686 ps
CPU time 76.49 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:28:48 PM PDT 24
Peak memory 201504 kb
Host smart-3f4b4e05-4db7-43d6-b717-70b74eb0bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204061218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.204061218
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3728795124
Short name T352
Test name
Test status
Simulation time 3467739868 ps
CPU time 2.65 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:28:04 PM PDT 24
Peak memory 201472 kb
Host smart-ff6160d8-5468-44b5-a16f-c2906ecac25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728795124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3728795124
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2833085274
Short name T471
Test name
Test status
Simulation time 5581101917 ps
CPU time 7.45 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:27:25 PM PDT 24
Peak memory 201444 kb
Host smart-4fd466e9-71a5-44b0-a3c9-ba3282c4c49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833085274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2833085274
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1781270113
Short name T152
Test name
Test status
Simulation time 338958925832 ps
CPU time 183.79 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:30:36 PM PDT 24
Peak memory 201672 kb
Host smart-6b3b59d4-c57a-4269-a632-a68a47a4cc1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781270113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1781270113
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4030916216
Short name T429
Test name
Test status
Simulation time 407071059 ps
CPU time 1.33 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:28:06 PM PDT 24
Peak memory 201320 kb
Host smart-210765c5-ba53-4416-992a-bcc8971bb907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030916216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4030916216
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1321745311
Short name T190
Test name
Test status
Simulation time 363201003891 ps
CPU time 885.42 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:42:28 PM PDT 24
Peak memory 201748 kb
Host smart-ef8fc7b5-5845-4801-bd43-020661779fe5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321745311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1321745311
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2090983048
Short name T227
Test name
Test status
Simulation time 157297112869 ps
CPU time 99.28 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:29:20 PM PDT 24
Peak memory 201808 kb
Host smart-a9a362c2-b2bf-4459-ab68-ea7db73d60cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090983048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2090983048
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1311478711
Short name T585
Test name
Test status
Simulation time 327845861596 ps
CPU time 202.56 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:30:53 PM PDT 24
Peak memory 201780 kb
Host smart-680af6e0-e663-4393-b4ee-d2d173411b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311478711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1311478711
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.386095378
Short name T400
Test name
Test status
Simulation time 169217896705 ps
CPU time 378.44 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:34:01 PM PDT 24
Peak memory 201696 kb
Host smart-a0ddff23-51d5-42c5-9de8-2f7cd06b3dee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=386095378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.386095378
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1713703303
Short name T509
Test name
Test status
Simulation time 333202885725 ps
CPU time 189.88 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:30:42 PM PDT 24
Peak memory 201808 kb
Host smart-ab2852a2-639e-47fd-89e8-d803664f8671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713703303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1713703303
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.884766519
Short name T399
Test name
Test status
Simulation time 324867854623 ps
CPU time 805.04 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:40:58 PM PDT 24
Peak memory 201728 kb
Host smart-e14a2ec0-5053-4967-b97c-d010d32e084b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884766519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.884766519
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3595267174
Short name T766
Test name
Test status
Simulation time 339485684935 ps
CPU time 780.43 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:40:31 PM PDT 24
Peak memory 201768 kb
Host smart-38859392-d136-4188-b75d-8f6bb398db04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595267174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3595267174
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.437099914
Short name T498
Test name
Test status
Simulation time 598832609952 ps
CPU time 241.62 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:32:08 PM PDT 24
Peak memory 201720 kb
Host smart-744b6704-2c6d-4fc3-8602-f2505a676b04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437099914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.437099914
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1426928968
Short name T688
Test name
Test status
Simulation time 134185414897 ps
CPU time 764.52 seconds
Started Mar 17 12:27:42 PM PDT 24
Finished Mar 17 12:40:27 PM PDT 24
Peak memory 202416 kb
Host smart-145e21fd-d179-402f-b559-32f4f537aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426928968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1426928968
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1220871266
Short name T28
Test name
Test status
Simulation time 31808090161 ps
CPU time 68.46 seconds
Started Mar 17 12:27:45 PM PDT 24
Finished Mar 17 12:28:53 PM PDT 24
Peak memory 201520 kb
Host smart-69ced167-a886-4048-b254-73c5225671c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220871266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1220871266
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.40668976
Short name T598
Test name
Test status
Simulation time 4413727813 ps
CPU time 7.38 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:22 PM PDT 24
Peak memory 201420 kb
Host smart-69f5e788-4515-461d-87e0-654be8564e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40668976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.40668976
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3878941948
Short name T705
Test name
Test status
Simulation time 5889823601 ps
CPU time 15.62 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:27:48 PM PDT 24
Peak memory 201632 kb
Host smart-4ff64c27-9736-4062-9760-c8b6de4547b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878941948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3878941948
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1313400040
Short name T779
Test name
Test status
Simulation time 509312486 ps
CPU time 0.87 seconds
Started Mar 17 12:27:43 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 201812 kb
Host smart-20cbfba0-172c-426e-9372-2847893412b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313400040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1313400040
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2713612192
Short name T229
Test name
Test status
Simulation time 167417680301 ps
CPU time 191.96 seconds
Started Mar 17 12:27:53 PM PDT 24
Finished Mar 17 12:31:05 PM PDT 24
Peak memory 201712 kb
Host smart-f654951e-2fdc-4658-b3cc-3acae7d5ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713612192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2713612192
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.327531236
Short name T504
Test name
Test status
Simulation time 169214624487 ps
CPU time 411.89 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:35:06 PM PDT 24
Peak memory 201520 kb
Host smart-92fb2337-ace2-4fd2-913f-6c5d578af3a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=327531236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.327531236
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3774314019
Short name T618
Test name
Test status
Simulation time 163241385438 ps
CPU time 78.88 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:29:33 PM PDT 24
Peak memory 201656 kb
Host smart-f2993e48-f42b-44a6-a097-6111adf5a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774314019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3774314019
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3850994302
Short name T580
Test name
Test status
Simulation time 166778796301 ps
CPU time 411.39 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:34:57 PM PDT 24
Peak memory 201628 kb
Host smart-d584d556-c4af-453f-94e7-b283764af960
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850994302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3850994302
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.625414959
Short name T267
Test name
Test status
Simulation time 358399733890 ps
CPU time 752.82 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:40:41 PM PDT 24
Peak memory 201728 kb
Host smart-e78fd15e-f44c-47a9-8b5b-2ac315dc14fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625414959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.625414959
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.9211335
Short name T347
Test name
Test status
Simulation time 200682891647 ps
CPU time 178.2 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:31:13 PM PDT 24
Peak memory 201784 kb
Host smart-012c48af-fb3a-4904-8667-8afa9480b6e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9211335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.ad
c_ctrl_filters_wakeup_fixed.9211335
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2106414026
Short name T398
Test name
Test status
Simulation time 123843996902 ps
CPU time 642.94 seconds
Started Mar 17 12:27:45 PM PDT 24
Finished Mar 17 12:38:28 PM PDT 24
Peak memory 202120 kb
Host smart-41581dac-87df-47b3-bcab-ca3508895037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106414026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2106414026
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1644329057
Short name T458
Test name
Test status
Simulation time 35989723074 ps
CPU time 75.85 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:29:30 PM PDT 24
Peak memory 201264 kb
Host smart-ff2a022a-c804-48ac-b1d9-ad1444657003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644329057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1644329057
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1151265960
Short name T606
Test name
Test status
Simulation time 4825726957 ps
CPU time 12.43 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:13 PM PDT 24
Peak memory 201704 kb
Host smart-140ba0f0-456b-4b2a-8645-3f0699da85c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151265960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1151265960
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1669308073
Short name T594
Test name
Test status
Simulation time 5494868435 ps
CPU time 3.54 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:28:09 PM PDT 24
Peak memory 201388 kb
Host smart-2663ed71-265e-44c0-bcc2-ddde7791eb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669308073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1669308073
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3520823828
Short name T528
Test name
Test status
Simulation time 11662431005 ps
CPU time 4.6 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201632 kb
Host smart-15145cc3-8de6-4514-a915-957923524f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520823828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3520823828
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.4288759242
Short name T73
Test name
Test status
Simulation time 335430103 ps
CPU time 0.93 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:27:50 PM PDT 24
Peak memory 201444 kb
Host smart-514b90d5-914c-4616-a856-aee73226cf44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288759242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.4288759242
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2745287287
Short name T228
Test name
Test status
Simulation time 347111340189 ps
CPU time 546.57 seconds
Started Mar 17 12:27:47 PM PDT 24
Finished Mar 17 12:36:53 PM PDT 24
Peak memory 201764 kb
Host smart-d55eb23f-4627-450e-831c-1c250317c734
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745287287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2745287287
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.647197131
Short name T597
Test name
Test status
Simulation time 497071727806 ps
CPU time 1153.03 seconds
Started Mar 17 12:28:26 PM PDT 24
Finished Mar 17 12:47:39 PM PDT 24
Peak memory 201556 kb
Host smart-3504bb93-4ff5-46a9-904f-dbefa97de356
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=647197131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.647197131
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1554036282
Short name T578
Test name
Test status
Simulation time 487658096112 ps
CPU time 1149.53 seconds
Started Mar 17 12:27:47 PM PDT 24
Finished Mar 17 12:46:57 PM PDT 24
Peak memory 201892 kb
Host smart-7c4bc796-c75f-4e32-a46f-0f32e0e00ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554036282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1554036282
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3582980884
Short name T22
Test name
Test status
Simulation time 329620774976 ps
CPU time 187.24 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:31:08 PM PDT 24
Peak memory 201788 kb
Host smart-b15a6f4a-a1bd-4f6e-9baa-4c0bb174b6ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582980884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3582980884
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2848418898
Short name T566
Test name
Test status
Simulation time 196899857662 ps
CPU time 97.2 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:30:02 PM PDT 24
Peak memory 201580 kb
Host smart-67178cdc-d574-4cba-9f94-e3fbdcd497c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848418898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2848418898
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4145914192
Short name T581
Test name
Test status
Simulation time 75117762765 ps
CPU time 376.76 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:35:12 PM PDT 24
Peak memory 202044 kb
Host smart-5d81786f-b320-4acf-96e6-d0dc27856b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145914192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4145914192
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1016273937
Short name T634
Test name
Test status
Simulation time 34030531557 ps
CPU time 19.64 seconds
Started Mar 17 12:27:52 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 201532 kb
Host smart-806e5c8b-3a9d-464c-acf4-7148f49c3d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016273937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1016273937
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1201287513
Short name T25
Test name
Test status
Simulation time 3626222731 ps
CPU time 2.85 seconds
Started Mar 17 12:28:56 PM PDT 24
Finished Mar 17 12:28:59 PM PDT 24
Peak memory 201408 kb
Host smart-653c2bd9-57e5-4e61-a672-d01e83c7bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201287513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1201287513
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.67117243
Short name T444
Test name
Test status
Simulation time 6038005723 ps
CPU time 2.02 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 201628 kb
Host smart-3e08788f-1f5a-4f08-95e2-fbc8f0af90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67117243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.67117243
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.126172740
Short name T626
Test name
Test status
Simulation time 38392077277 ps
CPU time 23.96 seconds
Started Mar 17 12:28:56 PM PDT 24
Finished Mar 17 12:29:20 PM PDT 24
Peak memory 201744 kb
Host smart-2cab8dda-ffa8-4eb3-ac04-5600ee2a6a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126172740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
126172740
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2590610396
Short name T557
Test name
Test status
Simulation time 92631804785 ps
CPU time 184.12 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:31:53 PM PDT 24
Peak memory 209976 kb
Host smart-6e2e125f-db6f-4d53-bb2c-aeecf674a36c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590610396 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2590610396
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.448220324
Short name T392
Test name
Test status
Simulation time 492972775 ps
CPU time 0.9 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201320 kb
Host smart-1995af48-509e-4471-b75a-b1429ded4251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448220324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.448220324
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.4113011451
Short name T272
Test name
Test status
Simulation time 164912639550 ps
CPU time 33.03 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:28:30 PM PDT 24
Peak memory 201512 kb
Host smart-c0290b66-c2e3-4918-92ce-452846e9bfd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113011451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.4113011451
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4278298504
Short name T621
Test name
Test status
Simulation time 328541736402 ps
CPU time 666.33 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:40:01 PM PDT 24
Peak memory 201740 kb
Host smart-17773b61-3172-4d27-94c2-606e328aeb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278298504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4278298504
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2518730594
Short name T4
Test name
Test status
Simulation time 327586215703 ps
CPU time 725.21 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:40:26 PM PDT 24
Peak memory 201692 kb
Host smart-a743c7e5-4cb6-4c2e-a3ec-6b2e2fe9e125
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518730594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2518730594
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1245111632
Short name T646
Test name
Test status
Simulation time 168701486036 ps
CPU time 390.81 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:35:35 PM PDT 24
Peak memory 201764 kb
Host smart-d905719d-4f11-4b79-a584-89b0095fdec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245111632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1245111632
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2426631556
Short name T9
Test name
Test status
Simulation time 161060394655 ps
CPU time 343.62 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:33:45 PM PDT 24
Peak memory 201548 kb
Host smart-045b8b6c-9d67-4668-88cc-a989c183b47e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426631556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2426631556
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3494124020
Short name T148
Test name
Test status
Simulation time 551712484927 ps
CPU time 351.84 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:34:12 PM PDT 24
Peak memory 201780 kb
Host smart-c1f51251-779b-4104-ae4a-6ca24048105b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494124020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3494124020
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1027023780
Short name T771
Test name
Test status
Simulation time 611602152043 ps
CPU time 160.04 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:30:37 PM PDT 24
Peak memory 201520 kb
Host smart-63b72102-6d29-4098-8517-66bf73443a75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027023780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1027023780
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1753934047
Short name T445
Test name
Test status
Simulation time 95531438566 ps
CPU time 526.74 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:36:56 PM PDT 24
Peak memory 202004 kb
Host smart-2957a36e-8069-4cda-b4b4-61469860539d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753934047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1753934047
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3712339385
Short name T394
Test name
Test status
Simulation time 30830425655 ps
CPU time 22.21 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:28:43 PM PDT 24
Peak memory 201472 kb
Host smart-30236b56-01e2-49ef-b73e-27ddfa931ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712339385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3712339385
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4086167372
Short name T511
Test name
Test status
Simulation time 4151122220 ps
CPU time 3.1 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:28:41 PM PDT 24
Peak memory 201416 kb
Host smart-ec9404ba-371d-44b7-8ca6-84e06e0d4ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086167372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4086167372
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1653046003
Short name T415
Test name
Test status
Simulation time 5614560914 ps
CPU time 7.17 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:28:32 PM PDT 24
Peak memory 201400 kb
Host smart-fb3120ec-e535-46ec-a13f-0500370a7a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653046003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1653046003
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.691518691
Short name T620
Test name
Test status
Simulation time 1044120729685 ps
CPU time 1433.01 seconds
Started Mar 17 12:27:54 PM PDT 24
Finished Mar 17 12:51:48 PM PDT 24
Peak memory 210396 kb
Host smart-93b83b4c-2d85-4fb9-af0d-ae4a532aff84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691518691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
691518691
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1436795195
Short name T198
Test name
Test status
Simulation time 29644071367 ps
CPU time 43.28 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:28:52 PM PDT 24
Peak memory 210028 kb
Host smart-b1638966-a54d-44c7-8eec-4307eeb2e822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436795195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1436795195
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.598706221
Short name T545
Test name
Test status
Simulation time 451427496 ps
CPU time 0.9 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:07 PM PDT 24
Peak memory 201496 kb
Host smart-5d963f90-33b9-409d-a6e0-beebf3693e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598706221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.598706221
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3633526628
Short name T250
Test name
Test status
Simulation time 500270849273 ps
CPU time 1107.58 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:46:39 PM PDT 24
Peak memory 201648 kb
Host smart-38fbf04f-5a14-4572-a2fe-3913f8029edf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633526628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3633526628
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1499804092
Short name T531
Test name
Test status
Simulation time 329815400099 ps
CPU time 683.29 seconds
Started Mar 17 12:28:07 PM PDT 24
Finished Mar 17 12:39:31 PM PDT 24
Peak memory 201696 kb
Host smart-1da77ace-bae3-44a6-a01f-a7873f2d6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499804092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1499804092
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1441694469
Short name T164
Test name
Test status
Simulation time 499703066474 ps
CPU time 189.12 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:31:30 PM PDT 24
Peak memory 201704 kb
Host smart-361d9729-af62-4fe8-8557-015df3a8d893
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441694469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1441694469
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1584782575
Short name T633
Test name
Test status
Simulation time 323642761342 ps
CPU time 365.64 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:34:14 PM PDT 24
Peak memory 201620 kb
Host smart-608fd81a-7b2c-4bc5-b558-ca1e38ef395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584782575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1584782575
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1542475717
Short name T480
Test name
Test status
Simulation time 331511207329 ps
CPU time 766.44 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:40:55 PM PDT 24
Peak memory 201660 kb
Host smart-793fea10-a844-4c54-9fed-f372f13c4e7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542475717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1542475717
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.257488024
Short name T410
Test name
Test status
Simulation time 411883313917 ps
CPU time 939.8 seconds
Started Mar 17 12:28:11 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 201572 kb
Host smart-0e69152d-17cc-40d7-89b0-17a14b078e24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257488024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.257488024
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3018969210
Short name T749
Test name
Test status
Simulation time 101404490739 ps
CPU time 424.04 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 202084 kb
Host smart-c970c7dd-bfc6-470f-89f8-a0dc9ecb66c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018969210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3018969210
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2527545511
Short name T85
Test name
Test status
Simulation time 28951867126 ps
CPU time 20.37 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:35 PM PDT 24
Peak memory 201412 kb
Host smart-9c4eb5ca-2737-4439-ad15-c89e646595e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527545511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2527545511
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3001174193
Short name T672
Test name
Test status
Simulation time 4554400971 ps
CPU time 8.94 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:28:36 PM PDT 24
Peak memory 201436 kb
Host smart-94b407e1-e0b1-4aa4-831d-ac5f99aa6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001174193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3001174193
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2637111786
Short name T638
Test name
Test status
Simulation time 5596873980 ps
CPU time 12.82 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:46 PM PDT 24
Peak memory 201508 kb
Host smart-18561114-9135-471f-8de2-e3e995737caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637111786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2637111786
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.456258401
Short name T72
Test name
Test status
Simulation time 358008329 ps
CPU time 0.81 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 201356 kb
Host smart-b30aa886-01d4-4e9b-940a-35a72088aefd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456258401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.456258401
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2396783623
Short name T60
Test name
Test status
Simulation time 170637198580 ps
CPU time 26.97 seconds
Started Mar 17 12:28:11 PM PDT 24
Finished Mar 17 12:28:39 PM PDT 24
Peak memory 201568 kb
Host smart-68683a45-c61a-41c9-8b05-54316624a641
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396783623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2396783623
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3784920959
Short name T236
Test name
Test status
Simulation time 512101666126 ps
CPU time 611.26 seconds
Started Mar 17 12:28:26 PM PDT 24
Finished Mar 17 12:38:38 PM PDT 24
Peak memory 201636 kb
Host smart-ef38d468-df9c-4025-ad79-ac1c3fd4dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784920959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3784920959
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3561708034
Short name T201
Test name
Test status
Simulation time 327820350312 ps
CPU time 359.41 seconds
Started Mar 17 12:28:02 PM PDT 24
Finished Mar 17 12:34:02 PM PDT 24
Peak memory 201612 kb
Host smart-309123e6-a0b1-46b3-815f-62f21120f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561708034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3561708034
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3626570996
Short name T664
Test name
Test status
Simulation time 487509468411 ps
CPU time 314.76 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:33:16 PM PDT 24
Peak memory 201748 kb
Host smart-bfd2e1d8-2ed3-4b04-998d-725f7d5f0fa8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626570996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3626570996
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.629389358
Short name T518
Test name
Test status
Simulation time 332634733382 ps
CPU time 368.08 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:34:25 PM PDT 24
Peak memory 201740 kb
Host smart-23792b3a-eea0-4472-b833-5b7f5dee08a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629389358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.629389358
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1238391446
Short name T472
Test name
Test status
Simulation time 322582577106 ps
CPU time 380.05 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 201612 kb
Host smart-f944469d-39eb-4431-8f8c-c6bd7cfca7bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238391446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1238391446
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1671204121
Short name T210
Test name
Test status
Simulation time 582249455015 ps
CPU time 1388.58 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:51:25 PM PDT 24
Peak memory 201684 kb
Host smart-75d6b0f9-91eb-4933-be62-1873b3d048ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671204121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1671204121
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.982858817
Short name T426
Test name
Test status
Simulation time 193181134507 ps
CPU time 241.09 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:32:28 PM PDT 24
Peak memory 201636 kb
Host smart-09d1fe0f-8796-4d92-b381-261b69946152
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982858817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.982858817
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3911276610
Short name T556
Test name
Test status
Simulation time 73783881067 ps
CPU time 353.28 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:34:10 PM PDT 24
Peak memory 201960 kb
Host smart-03c81be7-70d5-41d6-8f85-e20b6f48d7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911276610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3911276610
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.270614455
Short name T639
Test name
Test status
Simulation time 43556390231 ps
CPU time 108.77 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:29:55 PM PDT 24
Peak memory 201524 kb
Host smart-98862815-6ed5-4dd0-a82a-77ef5df8a687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270614455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.270614455
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3295740536
Short name T595
Test name
Test status
Simulation time 3675272602 ps
CPU time 6.06 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:28:23 PM PDT 24
Peak memory 201416 kb
Host smart-5258b790-ad76-4d6d-ad96-edd3be397b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295740536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3295740536
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2781134853
Short name T696
Test name
Test status
Simulation time 5781460091 ps
CPU time 14.4 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:28:24 PM PDT 24
Peak memory 201432 kb
Host smart-ad610f3b-0901-4b7e-8245-4325bf6d3a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781134853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2781134853
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.1426559540
Short name T286
Test name
Test status
Simulation time 455287549227 ps
CPU time 571.05 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:37:45 PM PDT 24
Peak memory 210320 kb
Host smart-3e156763-e15b-445c-ac64-31e7b3b055c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426559540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.1426559540
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1299364627
Short name T20
Test name
Test status
Simulation time 314436032586 ps
CPU time 278.32 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:32:56 PM PDT 24
Peak memory 212648 kb
Host smart-4e1aca67-5b83-46bb-9c7e-029dda89b650
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299364627 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1299364627
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2268532727
Short name T782
Test name
Test status
Simulation time 389078895 ps
CPU time 1.49 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:28:21 PM PDT 24
Peak memory 201384 kb
Host smart-b5fb97fa-751b-4049-8981-72ab1f6b7cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268532727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2268532727
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1215939509
Short name T735
Test name
Test status
Simulation time 166852126519 ps
CPU time 105.72 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:29:52 PM PDT 24
Peak memory 201684 kb
Host smart-707f18ce-4fea-40da-8ef1-e12b03d0cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215939509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1215939509
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.674075452
Short name T499
Test name
Test status
Simulation time 169342984501 ps
CPU time 82.69 seconds
Started Mar 17 12:28:10 PM PDT 24
Finished Mar 17 12:29:34 PM PDT 24
Peak memory 201556 kb
Host smart-05c44027-911c-47a0-9166-3d7ccc45d403
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=674075452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.674075452
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3843998183
Short name T730
Test name
Test status
Simulation time 324843440837 ps
CPU time 170.57 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:31:00 PM PDT 24
Peak memory 201664 kb
Host smart-f2e2fb13-66c3-4f59-a9d0-b74912510982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843998183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3843998183
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1983667253
Short name T469
Test name
Test status
Simulation time 162960682273 ps
CPU time 173.55 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:31:11 PM PDT 24
Peak memory 201732 kb
Host smart-021ee0c4-c770-47dc-9d79-9b573b557095
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983667253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1983667253
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1826830981
Short name T712
Test name
Test status
Simulation time 342166655842 ps
CPU time 191.91 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:31:13 PM PDT 24
Peak memory 201840 kb
Host smart-4d4d35fd-f539-406c-891c-fc32a863a946
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826830981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1826830981
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2383722334
Short name T737
Test name
Test status
Simulation time 398566855974 ps
CPU time 446.43 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:35:42 PM PDT 24
Peak memory 201668 kb
Host smart-7111d5ba-5dd5-4ae1-9a1a-3fc38e8c3046
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383722334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2383722334
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2658405125
Short name T370
Test name
Test status
Simulation time 106072101217 ps
CPU time 391.81 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:34:47 PM PDT 24
Peak memory 201972 kb
Host smart-47807ca9-c40f-47ed-a378-b75969fb9d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658405125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2658405125
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1759925959
Short name T366
Test name
Test status
Simulation time 22301794513 ps
CPU time 26.48 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:28:43 PM PDT 24
Peak memory 201444 kb
Host smart-e567fba2-64d7-4249-bea4-840eed058e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759925959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1759925959
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1853584444
Short name T563
Test name
Test status
Simulation time 3351063778 ps
CPU time 8.25 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:28:29 PM PDT 24
Peak memory 201432 kb
Host smart-d902c68d-ba37-4cdb-ade4-e15ce4a57f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853584444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1853584444
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1052065767
Short name T505
Test name
Test status
Simulation time 5655491802 ps
CPU time 3.81 seconds
Started Mar 17 12:28:18 PM PDT 24
Finished Mar 17 12:28:22 PM PDT 24
Peak memory 201488 kb
Host smart-25fea2a3-95be-4d73-8774-ce46aca0875e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052065767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1052065767
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.868023524
Short name T440
Test name
Test status
Simulation time 127244703840 ps
CPU time 502.37 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:36:43 PM PDT 24
Peak memory 210244 kb
Host smart-4432adcb-2265-4d77-b480-dce67785b61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868023524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
868023524
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.742874015
Short name T37
Test name
Test status
Simulation time 109444671911 ps
CPU time 63.98 seconds
Started Mar 17 12:28:26 PM PDT 24
Finished Mar 17 12:29:31 PM PDT 24
Peak memory 201752 kb
Host smart-5e6d8136-f176-41f3-8ff1-692f79ad2e8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742874015 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.742874015
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4141034924
Short name T354
Test name
Test status
Simulation time 335062601 ps
CPU time 1.01 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:28:21 PM PDT 24
Peak memory 201384 kb
Host smart-18a04447-4858-48b0-b125-54626c0f4ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141034924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4141034924
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2168683799
Short name T117
Test name
Test status
Simulation time 494083888223 ps
CPU time 295.58 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:33:18 PM PDT 24
Peak memory 201572 kb
Host smart-99060884-3348-4ce8-b188-419014e8b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168683799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2168683799
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3907911342
Short name T502
Test name
Test status
Simulation time 496564087131 ps
CPU time 295.23 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:33:17 PM PDT 24
Peak memory 201368 kb
Host smart-e9bff1a0-3cd2-43ec-9ca5-1de37d357546
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907911342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3907911342
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.172449687
Short name T280
Test name
Test status
Simulation time 488740724128 ps
CPU time 580.51 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:38:07 PM PDT 24
Peak memory 201688 kb
Host smart-2c0772e6-82d7-4a43-b6b7-45686498191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172449687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.172449687
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1232241102
Short name T777
Test name
Test status
Simulation time 161909421725 ps
CPU time 57.97 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:29:19 PM PDT 24
Peak memory 201640 kb
Host smart-12cf259a-d1e1-4bc2-8ccd-24fdfb9dac11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232241102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1232241102
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3319564539
Short name T616
Test name
Test status
Simulation time 532145276342 ps
CPU time 1237.77 seconds
Started Mar 17 12:28:08 PM PDT 24
Finished Mar 17 12:48:47 PM PDT 24
Peak memory 201772 kb
Host smart-b28631c6-6df5-4e1a-9b9f-6107723d4b6c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319564539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3319564539
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.130506147
Short name T24
Test name
Test status
Simulation time 197821752457 ps
CPU time 78.02 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:29:39 PM PDT 24
Peak memory 201696 kb
Host smart-979eaa89-71f5-4d40-9f7c-585238f40df9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130506147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.130506147
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4023091512
Short name T130
Test name
Test status
Simulation time 30002292175 ps
CPU time 75.67 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:29:43 PM PDT 24
Peak memory 201444 kb
Host smart-50d60b38-8164-4833-809b-2fb955d3235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023091512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4023091512
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1930313421
Short name T348
Test name
Test status
Simulation time 2587877327 ps
CPU time 6.35 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:28:26 PM PDT 24
Peak memory 201460 kb
Host smart-f119bf77-5669-4cde-9621-9bd7f48095ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930313421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1930313421
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2396209234
Short name T575
Test name
Test status
Simulation time 5811134261 ps
CPU time 4.56 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:20 PM PDT 24
Peak memory 201408 kb
Host smart-db0faf3d-f51a-41b2-9c84-8480c559c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396209234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2396209234
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.978906362
Short name T650
Test name
Test status
Simulation time 168887655019 ps
CPU time 402.04 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:35:01 PM PDT 24
Peak memory 201804 kb
Host smart-1e80289c-85cb-46df-aa6b-90bb318774c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978906362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
978906362
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.646576402
Short name T171
Test name
Test status
Simulation time 36513704316 ps
CPU time 99.91 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:30:00 PM PDT 24
Peak memory 210400 kb
Host smart-ccadba42-ed8b-4583-acf3-48002921d0e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646576402 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.646576402
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.122494266
Short name T23
Test name
Test status
Simulation time 313076135 ps
CPU time 1.34 seconds
Started Mar 17 12:25:32 PM PDT 24
Finished Mar 17 12:25:33 PM PDT 24
Peak memory 201420 kb
Host smart-e1895fa4-71d4-43a6-8b84-105cf5c39197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122494266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.122494266
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2785911336
Short name T58
Test name
Test status
Simulation time 352032093214 ps
CPU time 201.95 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:31:18 PM PDT 24
Peak memory 201740 kb
Host smart-2744335f-5cf4-4c6f-9a99-370514f7bf0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785911336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2785911336
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3590180253
Short name T284
Test name
Test status
Simulation time 197472668489 ps
CPU time 493.77 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:36:15 PM PDT 24
Peak memory 200864 kb
Host smart-36cb793c-edb1-45d2-8215-3b212bed13c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590180253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3590180253
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2885615130
Short name T550
Test name
Test status
Simulation time 324350772796 ps
CPU time 700.73 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:39:46 PM PDT 24
Peak memory 201652 kb
Host smart-102e2db4-078e-4255-9bff-ab88c86fc564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885615130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2885615130
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.496057648
Short name T86
Test name
Test status
Simulation time 167564619569 ps
CPU time 105.16 seconds
Started Mar 17 12:27:49 PM PDT 24
Finished Mar 17 12:29:35 PM PDT 24
Peak memory 200508 kb
Host smart-9d160fce-cbc7-4515-9488-1b20a3fd22ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=496057648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.496057648
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.4267054979
Short name T147
Test name
Test status
Simulation time 497423112932 ps
CPU time 1105.9 seconds
Started Mar 17 12:25:29 PM PDT 24
Finished Mar 17 12:43:55 PM PDT 24
Peak memory 201820 kb
Host smart-b218bcbf-5aa1-417a-a1f1-ee685aca6875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267054979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.4267054979
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1824868615
Short name T338
Test name
Test status
Simulation time 502885987815 ps
CPU time 580.99 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 201736 kb
Host smart-a7d129fa-bf3e-4369-ba20-afb29ea6c88a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824868615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1824868615
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.4206598460
Short name T728
Test name
Test status
Simulation time 185038882481 ps
CPU time 375.67 seconds
Started Mar 17 12:25:31 PM PDT 24
Finished Mar 17 12:31:47 PM PDT 24
Peak memory 201904 kb
Host smart-e4f81593-da36-426e-a255-95dcf71e01d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206598460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.4206598460
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.254463286
Short name T420
Test name
Test status
Simulation time 210390288925 ps
CPU time 146.04 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:30:25 PM PDT 24
Peak memory 200088 kb
Host smart-a367abfb-736f-464d-b1ce-ac08ec0eae8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254463286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.254463286
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1217619316
Short name T649
Test name
Test status
Simulation time 64434805164 ps
CPU time 277.12 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:32:42 PM PDT 24
Peak memory 202056 kb
Host smart-2a0dc8cc-49cd-4a2e-bbff-5dea0fbb6bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217619316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1217619316
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3026560557
Short name T744
Test name
Test status
Simulation time 37344678471 ps
CPU time 88.18 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:29:29 PM PDT 24
Peak memory 200212 kb
Host smart-006e642b-df27-4081-a374-6432bd20bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026560557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3026560557
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3323870575
Short name T669
Test name
Test status
Simulation time 3968355504 ps
CPU time 4.42 seconds
Started Mar 17 12:25:33 PM PDT 24
Finished Mar 17 12:25:38 PM PDT 24
Peak memory 201564 kb
Host smart-fb032ef7-1ff0-4868-a8a3-788245ce2f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323870575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3323870575
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3488799166
Short name T66
Test name
Test status
Simulation time 4661726064 ps
CPU time 3.36 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:27:36 PM PDT 24
Peak memory 217232 kb
Host smart-4181adc1-2798-402f-8787-7d66683d5466
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488799166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3488799166
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3684123346
Short name T462
Test name
Test status
Simulation time 5931125492 ps
CPU time 4.19 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:28:05 PM PDT 24
Peak memory 199816 kb
Host smart-7fad5f2e-3efd-4e72-8221-3b36b24db45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684123346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3684123346
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3673531510
Short name T709
Test name
Test status
Simulation time 155149493729 ps
CPU time 447.9 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:33:07 PM PDT 24
Peak memory 201984 kb
Host smart-1ad310d2-bf46-4fc9-89f3-fab6b4ce8065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673531510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3673531510
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2986172621
Short name T586
Test name
Test status
Simulation time 476038985 ps
CPU time 1.52 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:28:22 PM PDT 24
Peak memory 201384 kb
Host smart-84df5ebb-a29b-41bf-9198-f77a97659b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986172621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2986172621
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2264643470
Short name T239
Test name
Test status
Simulation time 327498965543 ps
CPU time 183.73 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:31:25 PM PDT 24
Peak memory 201672 kb
Host smart-8399e71c-9360-4ed8-90cf-9997b6de0723
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264643470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2264643470
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2766099690
Short name T232
Test name
Test status
Simulation time 327254103063 ps
CPU time 214.24 seconds
Started Mar 17 12:28:27 PM PDT 24
Finished Mar 17 12:32:01 PM PDT 24
Peak memory 201600 kb
Host smart-b58aeb9f-2572-4ba1-84a8-58820bf002f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766099690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2766099690
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1349138619
Short name T674
Test name
Test status
Simulation time 487709878176 ps
CPU time 224.56 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:32:06 PM PDT 24
Peak memory 201612 kb
Host smart-9a4425f8-0adf-4f0c-a24d-62a28770232d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349138619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1349138619
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3507816655
Short name T113
Test name
Test status
Simulation time 489570647206 ps
CPU time 607.39 seconds
Started Mar 17 12:28:35 PM PDT 24
Finished Mar 17 12:38:43 PM PDT 24
Peak memory 201656 kb
Host smart-08489cd1-f007-4205-abec-b1fceae177a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507816655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3507816655
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.4005499522
Short name T424
Test name
Test status
Simulation time 486600839038 ps
CPU time 1145.5 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:47:25 PM PDT 24
Peak memory 201676 kb
Host smart-7d6c2703-0029-41f7-867c-7b9f7715b051
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005499522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.4005499522
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1603743165
Short name T274
Test name
Test status
Simulation time 204944021169 ps
CPU time 110.88 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:30:08 PM PDT 24
Peak memory 201688 kb
Host smart-2eacae60-ac66-4d01-b4f5-8912f90632e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603743165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1603743165
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3579816375
Short name T729
Test name
Test status
Simulation time 205854933184 ps
CPU time 39.48 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 201764 kb
Host smart-32112805-701e-459b-aac0-197b2480bc95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579816375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3579816375
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3438092108
Short name T651
Test name
Test status
Simulation time 92030264665 ps
CPU time 472.32 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:36:13 PM PDT 24
Peak memory 202048 kb
Host smart-dc9a708d-2520-406d-811e-e7f1cb19fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438092108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3438092108
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1943072428
Short name T414
Test name
Test status
Simulation time 22193466975 ps
CPU time 15.59 seconds
Started Mar 17 12:28:21 PM PDT 24
Finished Mar 17 12:28:36 PM PDT 24
Peak memory 201600 kb
Host smart-a935b158-cf52-469c-8ccf-337917a9cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943072428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1943072428
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3508235592
Short name T567
Test name
Test status
Simulation time 3616401891 ps
CPU time 9.12 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:28:29 PM PDT 24
Peak memory 201540 kb
Host smart-8a424986-5b40-4608-901b-32ec09d946f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508235592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3508235592
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2414532283
Short name T652
Test name
Test status
Simulation time 5703569639 ps
CPU time 6.78 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:24 PM PDT 24
Peak memory 201508 kb
Host smart-6a511a38-9ae1-4e6a-a74a-a9bc77630036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414532283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2414532283
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3324225357
Short name T126
Test name
Test status
Simulation time 45538608226 ps
CPU time 118.24 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:30:28 PM PDT 24
Peak memory 210276 kb
Host smart-bb3b9307-7359-44eb-9c8c-3961b2b19483
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324225357 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3324225357
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.658671094
Short name T473
Test name
Test status
Simulation time 400579780 ps
CPU time 0.89 seconds
Started Mar 17 12:28:31 PM PDT 24
Finished Mar 17 12:28:32 PM PDT 24
Peak memory 201344 kb
Host smart-33f3fb9d-5d40-435f-aea3-81fb9ae90b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658671094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.658671094
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1032812881
Short name T772
Test name
Test status
Simulation time 333873435040 ps
CPU time 213.41 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:31:58 PM PDT 24
Peak memory 201576 kb
Host smart-496b5724-413a-4dc3-ab10-ca85cdcfee9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032812881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1032812881
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.3644953477
Short name T677
Test name
Test status
Simulation time 325508895751 ps
CPU time 773.6 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:41:13 PM PDT 24
Peak memory 201792 kb
Host smart-2600b93c-a734-4c48-b92f-c2db6a4c193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644953477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.3644953477
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2426741610
Short name T356
Test name
Test status
Simulation time 491833644262 ps
CPU time 307.44 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:33:24 PM PDT 24
Peak memory 201752 kb
Host smart-331d1906-ec15-4b24-87b4-981a09ece5bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426741610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2426741610
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1017757806
Short name T268
Test name
Test status
Simulation time 351812453429 ps
CPU time 215.46 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:32:05 PM PDT 24
Peak memory 201692 kb
Host smart-3e5ee174-5aa2-4fd6-8081-6562b048209d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017757806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1017757806
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3882742641
Short name T711
Test name
Test status
Simulation time 210048483989 ps
CPU time 139.97 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:30:40 PM PDT 24
Peak memory 201676 kb
Host smart-601b2c92-4e93-4e75-9b13-4762315c4f2a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882742641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3882742641
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.948799883
Short name T762
Test name
Test status
Simulation time 131084193539 ps
CPU time 450.88 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:36:09 PM PDT 24
Peak memory 201980 kb
Host smart-d41fafbf-b4b2-4a71-9556-e7a9877aa283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948799883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.948799883
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1161001343
Short name T579
Test name
Test status
Simulation time 25064675898 ps
CPU time 3.6 seconds
Started Mar 17 12:28:17 PM PDT 24
Finished Mar 17 12:28:21 PM PDT 24
Peak memory 201496 kb
Host smart-4b74a6aa-a174-40fa-8ec6-813606c6fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161001343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1161001343
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1136900298
Short name T443
Test name
Test status
Simulation time 3766078602 ps
CPU time 3.07 seconds
Started Mar 17 12:28:31 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 201364 kb
Host smart-bdc755d3-6ef6-43c7-aefc-d500aa60abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136900298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1136900298
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2130900888
Short name T680
Test name
Test status
Simulation time 5778845148 ps
CPU time 8.36 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:42 PM PDT 24
Peak memory 201464 kb
Host smart-3946f155-3c59-47b5-b1bc-28b4d22a3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130900888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2130900888
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2061721261
Short name T500
Test name
Test status
Simulation time 30945347397 ps
CPU time 17.91 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:28:41 PM PDT 24
Peak memory 201620 kb
Host smart-a77f861c-4b14-425c-a925-ba76cce43017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061721261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2061721261
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1526783589
Short name T215
Test name
Test status
Simulation time 37581167655 ps
CPU time 22.63 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:29:07 PM PDT 24
Peak memory 201828 kb
Host smart-7ffe9418-778f-4edf-a1d6-1150ad77c8e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526783589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1526783589
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.696290898
Short name T455
Test name
Test status
Simulation time 467455920 ps
CPU time 0.89 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:28:24 PM PDT 24
Peak memory 201496 kb
Host smart-70ce25a2-e0f0-4411-b477-0d5d82a83a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696290898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.696290898
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.872297646
Short name T109
Test name
Test status
Simulation time 177011144324 ps
CPU time 414.68 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 201576 kb
Host smart-a3014b26-aca5-43ae-8a76-0375cda7d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872297646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.872297646
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2859173154
Short name T155
Test name
Test status
Simulation time 490605905031 ps
CPU time 72.23 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:29:42 PM PDT 24
Peak memory 201760 kb
Host smart-462ecd9a-bcc8-4873-854a-f3713a846553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859173154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2859173154
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3826909272
Short name T483
Test name
Test status
Simulation time 322948067289 ps
CPU time 798.03 seconds
Started Mar 17 12:28:18 PM PDT 24
Finished Mar 17 12:41:37 PM PDT 24
Peak memory 201756 kb
Host smart-cd7e8e98-4286-4da8-a176-87c04b65e9ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826909272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3826909272
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1082299071
Short name T465
Test name
Test status
Simulation time 328802147660 ps
CPU time 193.16 seconds
Started Mar 17 12:28:39 PM PDT 24
Finished Mar 17 12:31:54 PM PDT 24
Peak memory 201736 kb
Host smart-85950b90-b72e-4672-98a3-fa494fc2ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082299071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1082299071
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2359956525
Short name T367
Test name
Test status
Simulation time 331989843222 ps
CPU time 219.56 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:32:05 PM PDT 24
Peak memory 201656 kb
Host smart-d2401171-b1e2-46fe-b98f-991ba4e3c9c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359956525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2359956525
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3923779958
Short name T258
Test name
Test status
Simulation time 497507756391 ps
CPU time 543.73 seconds
Started Mar 17 12:28:26 PM PDT 24
Finished Mar 17 12:37:30 PM PDT 24
Peak memory 201788 kb
Host smart-68e205ce-8622-48f7-bc76-301a53f48581
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923779958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3923779958
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4173049944
Short name T487
Test name
Test status
Simulation time 590695538021 ps
CPU time 648.6 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:39:08 PM PDT 24
Peak memory 201688 kb
Host smart-a04bcdb3-982e-4121-8036-136e0c6228d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173049944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4173049944
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1170455644
Short name T391
Test name
Test status
Simulation time 129928788183 ps
CPU time 643.55 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:39:27 PM PDT 24
Peak memory 202012 kb
Host smart-19e4020b-c63a-41fd-af03-2a8128673ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170455644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1170455644
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3591067078
Short name T516
Test name
Test status
Simulation time 29701298527 ps
CPU time 68.04 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:29:25 PM PDT 24
Peak memory 201608 kb
Host smart-81e78f4f-46cb-4382-9f11-b4aa556eb273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591067078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3591067078
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1179936541
Short name T432
Test name
Test status
Simulation time 4356913877 ps
CPU time 2.96 seconds
Started Mar 17 12:28:36 PM PDT 24
Finished Mar 17 12:28:40 PM PDT 24
Peak memory 201428 kb
Host smart-3ddf2ecb-5ebf-42ee-8b84-ca08e0f1402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179936541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1179936541
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2846498358
Short name T362
Test name
Test status
Simulation time 6002611668 ps
CPU time 4.25 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:28:27 PM PDT 24
Peak memory 201612 kb
Host smart-b157b01a-2366-4b1f-954c-955365c05ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846498358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2846498358
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.4172784354
Short name T538
Test name
Test status
Simulation time 189404654555 ps
CPU time 423.66 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:35:29 PM PDT 24
Peak memory 201644 kb
Host smart-83cd58d7-3f43-4d1b-a045-a6898275f378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172784354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.4172784354
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1081685465
Short name T756
Test name
Test status
Simulation time 30339599405 ps
CPU time 72.47 seconds
Started Mar 17 12:28:31 PM PDT 24
Finished Mar 17 12:29:44 PM PDT 24
Peak memory 210008 kb
Host smart-fd4ab875-2874-43ff-b770-9e642e82ddaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081685465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1081685465
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1868911020
Short name T387
Test name
Test status
Simulation time 461206062 ps
CPU time 1.57 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:28:35 PM PDT 24
Peak memory 201348 kb
Host smart-6a25d5a3-e746-48b3-89e5-60a4def32d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868911020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1868911020
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1306388339
Short name T220
Test name
Test status
Simulation time 435419418558 ps
CPU time 163.53 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:31:13 PM PDT 24
Peak memory 201680 kb
Host smart-83529b39-d01d-492b-b7a5-d0314ffe04c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306388339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1306388339
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.4001096978
Short name T212
Test name
Test status
Simulation time 336908710718 ps
CPU time 261.99 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:32:52 PM PDT 24
Peak memory 201680 kb
Host smart-87eb6fbc-b65a-4ce3-a08d-26996fd52712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001096978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.4001096978
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4062780024
Short name T467
Test name
Test status
Simulation time 333264049867 ps
CPU time 219.03 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:32:09 PM PDT 24
Peak memory 201684 kb
Host smart-706d96f4-811d-4af9-bfc1-a9ca71b9a2ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062780024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4062780024
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1446893985
Short name T641
Test name
Test status
Simulation time 491012882268 ps
CPU time 1070.44 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:46:28 PM PDT 24
Peak memory 201688 kb
Host smart-333da6ab-94fe-449b-864e-9d64d3bff8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446893985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1446893985
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4254836405
Short name T374
Test name
Test status
Simulation time 326525999202 ps
CPU time 204.47 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:32:02 PM PDT 24
Peak memory 201600 kb
Host smart-3da7fdf5-e407-4b9e-8536-a6c4544556f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254836405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4254836405
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2779114938
Short name T630
Test name
Test status
Simulation time 368709024752 ps
CPU time 253.27 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:32:30 PM PDT 24
Peak memory 201836 kb
Host smart-ff626916-3bb7-40df-9401-8d644cb37918
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779114938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2779114938
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2216842350
Short name T627
Test name
Test status
Simulation time 609150787369 ps
CPU time 1414.52 seconds
Started Mar 17 12:28:20 PM PDT 24
Finished Mar 17 12:51:55 PM PDT 24
Peak memory 201764 kb
Host smart-f1800397-5a61-4279-8b81-dd326164179b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216842350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2216842350
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3009293602
Short name T325
Test name
Test status
Simulation time 88728919492 ps
CPU time 452.09 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 201964 kb
Host smart-1f53f178-d70b-4d7b-bf10-c5ce7909ebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009293602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3009293602
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.4144800389
Short name T661
Test name
Test status
Simulation time 46083345001 ps
CPU time 17 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:28:57 PM PDT 24
Peak memory 201404 kb
Host smart-8493b173-1f73-436d-b095-060e2f1f2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144800389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.4144800389
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2977089214
Short name T635
Test name
Test status
Simulation time 3101491818 ps
CPU time 2.12 seconds
Started Mar 17 12:28:15 PM PDT 24
Finished Mar 17 12:28:18 PM PDT 24
Peak memory 201388 kb
Host smart-88eeba69-8186-4adc-8bae-bd892f2e772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977089214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2977089214
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.409936930
Short name T29
Test name
Test status
Simulation time 5699366726 ps
CPU time 3.77 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:28:42 PM PDT 24
Peak memory 201416 kb
Host smart-f824913e-397a-43f7-954c-7f7fd62b6a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409936930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.409936930
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1839394328
Short name T303
Test name
Test status
Simulation time 344334828840 ps
CPU time 190.6 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:31:50 PM PDT 24
Peak memory 201680 kb
Host smart-081d555e-6974-4d67-942c-9c434efc3f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839394328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1839394328
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2053484530
Short name T38
Test name
Test status
Simulation time 43800868913 ps
CPU time 52.22 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:29:25 PM PDT 24
Peak memory 210284 kb
Host smart-62bafc8a-4e96-406a-a941-088dbbfdffa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053484530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2053484530
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3037518834
Short name T457
Test name
Test status
Simulation time 350120201 ps
CPU time 1.4 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:28:48 PM PDT 24
Peak memory 201312 kb
Host smart-dc6839a0-13fd-45ea-a82b-0ba7acc72b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037518834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3037518834
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2111736278
Short name T223
Test name
Test status
Simulation time 327212303607 ps
CPU time 507.57 seconds
Started Mar 17 12:28:19 PM PDT 24
Finished Mar 17 12:36:46 PM PDT 24
Peak memory 201784 kb
Host smart-4081cc72-47d1-4370-ade9-bacc5b636f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111736278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2111736278
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3648896440
Short name T450
Test name
Test status
Simulation time 166612990382 ps
CPU time 71.1 seconds
Started Mar 17 12:28:26 PM PDT 24
Finished Mar 17 12:29:38 PM PDT 24
Peak memory 201640 kb
Host smart-51fbf4bf-75a2-4586-85c9-549fae4533d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648896440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3648896440
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4190156909
Short name T255
Test name
Test status
Simulation time 324754554570 ps
CPU time 116.51 seconds
Started Mar 17 12:28:44 PM PDT 24
Finished Mar 17 12:30:40 PM PDT 24
Peak memory 201704 kb
Host smart-1a9195ab-4d4a-46ef-a740-64ef26c8f5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190156909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4190156909
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.645162605
Short name T359
Test name
Test status
Simulation time 162894528093 ps
CPU time 169.19 seconds
Started Mar 17 12:28:34 PM PDT 24
Finished Mar 17 12:31:24 PM PDT 24
Peak memory 201644 kb
Host smart-e2733a28-d7c2-4cf4-864c-52f2c27ba1f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=645162605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.645162605
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.783425109
Short name T154
Test name
Test status
Simulation time 561239663502 ps
CPU time 91.18 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:30:11 PM PDT 24
Peak memory 201752 kb
Host smart-a423bc73-40ca-462d-a924-b856825cb339
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783425109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.783425109
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1684043261
Short name T330
Test name
Test status
Simulation time 405507167029 ps
CPU time 443.2 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 201712 kb
Host smart-8fff610d-2893-4c3d-a74b-d407e3bb9513
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684043261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1684043261
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.801666118
Short name T51
Test name
Test status
Simulation time 108329757724 ps
CPU time 385.27 seconds
Started Mar 17 12:28:39 PM PDT 24
Finished Mar 17 12:35:06 PM PDT 24
Peak memory 202064 kb
Host smart-e59eca1a-e2a5-4045-b154-e3ed19ecbc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801666118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.801666118
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.123378451
Short name T743
Test name
Test status
Simulation time 26553236588 ps
CPU time 17.12 seconds
Started Mar 17 12:28:25 PM PDT 24
Finished Mar 17 12:28:42 PM PDT 24
Peak memory 201636 kb
Host smart-d14c137b-5344-4ad3-ba0b-92b4ece432f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123378451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.123378451
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3521481351
Short name T614
Test name
Test status
Simulation time 4111926033 ps
CPU time 9.22 seconds
Started Mar 17 12:28:24 PM PDT 24
Finished Mar 17 12:28:33 PM PDT 24
Peak memory 201500 kb
Host smart-33fb0328-a598-4e12-a635-933bbd0c8f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521481351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3521481351
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1770441402
Short name T368
Test name
Test status
Simulation time 6022556013 ps
CPU time 4.46 seconds
Started Mar 17 12:28:36 PM PDT 24
Finished Mar 17 12:28:42 PM PDT 24
Peak memory 201480 kb
Host smart-cf8cbb1e-af38-45a5-825f-ed13d5dfa27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770441402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1770441402
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4845863
Short name T277
Test name
Test status
Simulation time 137948331888 ps
CPU time 262.1 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:33:10 PM PDT 24
Peak memory 201908 kb
Host smart-8d55b468-1eec-4bcc-a6aa-bb1129af9419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4845863 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4845863
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1250728961
Short name T343
Test name
Test status
Simulation time 343327432 ps
CPU time 0.98 seconds
Started Mar 17 12:28:36 PM PDT 24
Finished Mar 17 12:28:37 PM PDT 24
Peak memory 201344 kb
Host smart-80bd612a-b5f0-4c2e-8949-945c301c8be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250728961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1250728961
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3898836004
Short name T485
Test name
Test status
Simulation time 328969205434 ps
CPU time 61.83 seconds
Started Mar 17 12:28:22 PM PDT 24
Finished Mar 17 12:29:24 PM PDT 24
Peak memory 202116 kb
Host smart-7677456b-ff22-4c1a-a055-c309da40dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898836004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3898836004
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1888914763
Short name T686
Test name
Test status
Simulation time 164354596338 ps
CPU time 209.33 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:32:15 PM PDT 24
Peak memory 201612 kb
Host smart-142a51e0-9d12-4b7a-bd35-c0b970a62ca3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888914763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1888914763
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1821379543
Short name T143
Test name
Test status
Simulation time 489503854644 ps
CPU time 1144.34 seconds
Started Mar 17 12:28:38 PM PDT 24
Finished Mar 17 12:47:44 PM PDT 24
Peak memory 201652 kb
Host smart-96d70d36-c964-420d-909e-63b1a9d4f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821379543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1821379543
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.495177923
Short name T716
Test name
Test status
Simulation time 331093958614 ps
CPU time 157.77 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:31:24 PM PDT 24
Peak memory 201656 kb
Host smart-cfadd58f-1d2a-4ce4-8f36-9c740f9725ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=495177923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.495177923
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3201344019
Short name T733
Test name
Test status
Simulation time 512188280368 ps
CPU time 568.48 seconds
Started Mar 17 12:28:29 PM PDT 24
Finished Mar 17 12:37:58 PM PDT 24
Peak memory 201728 kb
Host smart-7681f0bb-75ea-4c1c-a989-74f323a3fdbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201344019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3201344019
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1933001932
Short name T439
Test name
Test status
Simulation time 198842524600 ps
CPU time 129.43 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:30:57 PM PDT 24
Peak memory 201712 kb
Host smart-c3411964-4323-4ed8-88f9-b07b7333d055
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933001932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1933001932
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3037586449
Short name T1
Test name
Test status
Simulation time 124246780647 ps
CPU time 673.35 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:40:02 PM PDT 24
Peak memory 202064 kb
Host smart-d2dbf338-133b-4f6a-bf2a-5a7ef897c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037586449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3037586449
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1557424074
Short name T484
Test name
Test status
Simulation time 42075373629 ps
CPU time 106.56 seconds
Started Mar 17 12:28:31 PM PDT 24
Finished Mar 17 12:30:18 PM PDT 24
Peak memory 201448 kb
Host smart-2377e8ad-577f-46da-b133-d5d68d45f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557424074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1557424074
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2688273233
Short name T694
Test name
Test status
Simulation time 4101093422 ps
CPU time 10.14 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:28:48 PM PDT 24
Peak memory 201312 kb
Host smart-3ac47633-3adf-4213-8c43-108103e49bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688273233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2688273233
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1750596068
Short name T341
Test name
Test status
Simulation time 5714956783 ps
CPU time 2.51 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:28:50 PM PDT 24
Peak memory 201532 kb
Host smart-cd484100-1804-4a91-a2be-5e8a56836b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750596068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1750596068
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2473897874
Short name T33
Test name
Test status
Simulation time 41059683042 ps
CPU time 98.68 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:30:25 PM PDT 24
Peak memory 201472 kb
Host smart-016305bb-a7f9-470d-af28-d22202690eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473897874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2473897874
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2918765899
Short name T241
Test name
Test status
Simulation time 30629965831 ps
CPU time 76.88 seconds
Started Mar 17 12:28:39 PM PDT 24
Finished Mar 17 12:29:57 PM PDT 24
Peak memory 210420 kb
Host smart-e81a5a1a-afd7-45ce-8619-65307a6e8068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918765899 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2918765899
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3728395716
Short name T778
Test name
Test status
Simulation time 381458015 ps
CPU time 1.43 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:28:51 PM PDT 24
Peak memory 201388 kb
Host smart-c54f5bae-742e-4a8f-bfec-9940b9689dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728395716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3728395716
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.314717102
Short name T722
Test name
Test status
Simulation time 405130888867 ps
CPU time 212.01 seconds
Started Mar 17 12:28:35 PM PDT 24
Finished Mar 17 12:32:07 PM PDT 24
Peak memory 201760 kb
Host smart-7c72e26c-4bf7-476f-80a5-48dcca1a1eaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314717102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.314717102
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2106562319
Short name T305
Test name
Test status
Simulation time 162684763288 ps
CPU time 399.46 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:35:29 PM PDT 24
Peak memory 201636 kb
Host smart-c5972c09-9c1d-4ac9-bd7d-d5cd1d091f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106562319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2106562319
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1835036413
Short name T619
Test name
Test status
Simulation time 493743445190 ps
CPU time 1068.07 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:46:36 PM PDT 24
Peak memory 201776 kb
Host smart-aa3b0aae-a070-4cd4-90a2-b46b7b89a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835036413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1835036413
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1509274674
Short name T3
Test name
Test status
Simulation time 496617653450 ps
CPU time 1187.19 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:48:47 PM PDT 24
Peak memory 201748 kb
Host smart-f7938365-40c5-4ed7-8fa9-4d4f9c19f3a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509274674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1509274674
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1659593426
Short name T7
Test name
Test status
Simulation time 162677645107 ps
CPU time 174.07 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:32:06 PM PDT 24
Peak memory 201628 kb
Host smart-bc2bccab-dbbc-4258-9ccb-ac3641b095ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659593426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1659593426
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.136758085
Short name T589
Test name
Test status
Simulation time 502092175378 ps
CPU time 447.94 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:36:15 PM PDT 24
Peak memory 201748 kb
Host smart-ec9bf08d-fc21-4eaf-9724-b6b9e379da8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=136758085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.136758085
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1570469381
Short name T433
Test name
Test status
Simulation time 593883528156 ps
CPU time 1442.92 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:52:48 PM PDT 24
Peak memory 201692 kb
Host smart-d7fb87a0-cecc-4166-bccf-4d76545df733
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570469381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1570469381
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.395339495
Short name T182
Test name
Test status
Simulation time 143892427998 ps
CPU time 569.17 seconds
Started Mar 17 12:29:11 PM PDT 24
Finished Mar 17 12:38:40 PM PDT 24
Peak memory 202028 kb
Host smart-33f31135-96dd-4a62-bb30-005a2159d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395339495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.395339495
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.635279069
Short name T416
Test name
Test status
Simulation time 34745729315 ps
CPU time 14.87 seconds
Started Mar 17 12:28:42 PM PDT 24
Finished Mar 17 12:28:57 PM PDT 24
Peak memory 201492 kb
Host smart-5b87a162-258f-45e5-bd37-e1268612cfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635279069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.635279069
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.4060926382
Short name T670
Test name
Test status
Simulation time 3842608613 ps
CPU time 2.94 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:01 PM PDT 24
Peak memory 201440 kb
Host smart-c6be8f91-b224-41d5-9428-a03940c0c6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060926382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.4060926382
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3587358167
Short name T753
Test name
Test status
Simulation time 5787901595 ps
CPU time 13.61 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:29:03 PM PDT 24
Peak memory 201488 kb
Host smart-d50190c3-175b-4355-b7dc-9d83241242a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587358167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3587358167
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.554648263
Short name T706
Test name
Test status
Simulation time 452791700065 ps
CPU time 414.25 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:35:38 PM PDT 24
Peak memory 201932 kb
Host smart-2ec9a7c6-06f2-4a12-a365-205de14dac22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554648263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
554648263
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2312167297
Short name T294
Test name
Test status
Simulation time 207579845837 ps
CPU time 175.98 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:31:51 PM PDT 24
Peak memory 217560 kb
Host smart-0c077dac-db88-42da-9bec-9e1fb06f346b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312167297 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2312167297
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.52263865
Short name T339
Test name
Test status
Simulation time 371526808 ps
CPU time 0.82 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:28:49 PM PDT 24
Peak memory 201268 kb
Host smart-81ac9171-ba86-4987-af7b-1546d2d77846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52263865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.52263865
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3417360846
Short name T599
Test name
Test status
Simulation time 511832976260 ps
CPU time 1074.69 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:46:40 PM PDT 24
Peak memory 201660 kb
Host smart-b85c97d1-9e0b-4558-af57-07584e51e68d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417360846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3417360846
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.539328012
Short name T724
Test name
Test status
Simulation time 176823719644 ps
CPU time 424.27 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:36:03 PM PDT 24
Peak memory 201692 kb
Host smart-d890afd4-9f31-423b-bb6c-758cb739b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539328012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.539328012
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1045359660
Short name T312
Test name
Test status
Simulation time 162962056230 ps
CPU time 76.85 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:30:06 PM PDT 24
Peak memory 201780 kb
Host smart-20d9cef6-f8e2-495b-80b5-ff4c6edccf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045359660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1045359660
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2638936165
Short name T751
Test name
Test status
Simulation time 334611854379 ps
CPU time 771.14 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:41:40 PM PDT 24
Peak memory 201716 kb
Host smart-8dc08115-9172-44a4-8b64-fe28e7082c21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638936165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2638936165
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1689626759
Short name T315
Test name
Test status
Simulation time 487081142623 ps
CPU time 1177.56 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:48:29 PM PDT 24
Peak memory 201712 kb
Host smart-81cb1c17-f5a1-4df7-b8e8-071d6e163c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689626759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1689626759
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2571475509
Short name T600
Test name
Test status
Simulation time 326642241656 ps
CPU time 419.89 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:36:12 PM PDT 24
Peak memory 201708 kb
Host smart-7ff97eb5-8e5b-46ef-bc86-003b5d3856cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571475509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2571475509
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3870079978
Short name T285
Test name
Test status
Simulation time 180691851673 ps
CPU time 101.57 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:30:27 PM PDT 24
Peak memory 201748 kb
Host smart-66451d7a-b08f-40aa-a62b-07b548f3528b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870079978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3870079978
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3784064760
Short name T708
Test name
Test status
Simulation time 591901828838 ps
CPU time 359.88 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 201680 kb
Host smart-88566d3a-5c9d-4e84-b9f0-31100ec98810
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784064760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3784064760
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2750487721
Short name T448
Test name
Test status
Simulation time 81240487072 ps
CPU time 323.59 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 201976 kb
Host smart-c219bd0f-ec2f-4077-98ca-6fa78c6b3e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750487721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2750487721
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2649199296
Short name T84
Test name
Test status
Simulation time 38201288585 ps
CPU time 21.67 seconds
Started Mar 17 12:28:39 PM PDT 24
Finished Mar 17 12:29:03 PM PDT 24
Peak memory 201524 kb
Host smart-11233e54-f66c-4e00-803e-0f264e3f3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649199296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2649199296
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3581429540
Short name T704
Test name
Test status
Simulation time 5497305282 ps
CPU time 14.33 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:29:03 PM PDT 24
Peak memory 201452 kb
Host smart-e92091c0-0eb9-4475-8acd-e504937fc324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581429540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3581429540
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2074568640
Short name T376
Test name
Test status
Simulation time 5557623036 ps
CPU time 13.4 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:29:02 PM PDT 24
Peak memory 201464 kb
Host smart-8d35eed5-6c63-43cb-8c87-6d359fced4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074568640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2074568640
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3208945505
Short name T757
Test name
Test status
Simulation time 306588128274 ps
CPU time 1022.02 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:45:49 PM PDT 24
Peak memory 210192 kb
Host smart-d05cbca9-e031-4993-9e2c-8b4fcbf67cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208945505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3208945505
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1423972747
Short name T601
Test name
Test status
Simulation time 186923540570 ps
CPU time 286.68 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:33:36 PM PDT 24
Peak memory 210664 kb
Host smart-39e94180-dade-4ecc-a3f7-57d595715890
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423972747 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1423972747
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.491829042
Short name T361
Test name
Test status
Simulation time 320328946 ps
CPU time 1.38 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:28:49 PM PDT 24
Peak memory 201348 kb
Host smart-42247eac-20e7-4490-aed7-c892bf11f607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491829042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.491829042
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2315291460
Short name T254
Test name
Test status
Simulation time 348484656406 ps
CPU time 389.36 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:35:19 PM PDT 24
Peak memory 201692 kb
Host smart-1f034f5c-bab5-4771-8740-1ab7fb317584
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315291460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2315291460
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2292844468
Short name T10
Test name
Test status
Simulation time 166799723403 ps
CPU time 374.96 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:35:00 PM PDT 24
Peak memory 201668 kb
Host smart-56d1bcb8-5543-430d-94a7-884813f748c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292844468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2292844468
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3407978949
Short name T452
Test name
Test status
Simulation time 332096965331 ps
CPU time 688.33 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:40:14 PM PDT 24
Peak memory 201696 kb
Host smart-6520b56d-b7a8-4bab-bbb5-e307c6fb9659
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407978949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3407978949
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2880381641
Short name T587
Test name
Test status
Simulation time 161370689633 ps
CPU time 100.1 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:30:33 PM PDT 24
Peak memory 201688 kb
Host smart-d72dc39e-229d-4933-84a4-996f4f38a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880381641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2880381641
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2526478362
Short name T510
Test name
Test status
Simulation time 491298040943 ps
CPU time 1132.26 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:47:42 PM PDT 24
Peak memory 201760 kb
Host smart-0f2b1789-e09e-4902-9d2a-53685db24890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526478362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2526478362
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.17874775
Short name T145
Test name
Test status
Simulation time 537581609377 ps
CPU time 614.64 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:39:01 PM PDT 24
Peak memory 201788 kb
Host smart-1bfb492f-6334-4b69-8cc7-b765a27f9d93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17874775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_w
akeup.17874775
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3100579678
Short name T417
Test name
Test status
Simulation time 399719687987 ps
CPU time 486.06 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:36:55 PM PDT 24
Peak memory 201728 kb
Host smart-fd59a876-163f-46b0-824e-72348bf668bf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100579678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3100579678
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1070723856
Short name T562
Test name
Test status
Simulation time 81952948034 ps
CPU time 375.2 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:35:01 PM PDT 24
Peak memory 202040 kb
Host smart-567fbffd-eeff-4e48-9694-e491eadd8fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070723856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1070723856
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1732550472
Short name T725
Test name
Test status
Simulation time 43857869127 ps
CPU time 86.44 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:30:13 PM PDT 24
Peak memory 201524 kb
Host smart-a74dd3b2-b78e-45a0-a4ca-9d8f05ae54c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732550472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1732550472
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3559906774
Short name T687
Test name
Test status
Simulation time 3738892887 ps
CPU time 2.84 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:28:46 PM PDT 24
Peak memory 201508 kb
Host smart-b4ca8d01-579a-4a27-8faa-1adc05dec83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559906774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3559906774
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3005349115
Short name T573
Test name
Test status
Simulation time 5679678436 ps
CPU time 14.71 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:28:58 PM PDT 24
Peak memory 201524 kb
Host smart-4acc742e-9936-4229-8768-b9ef8cd467ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005349115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3005349115
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.840596737
Short name T222
Test name
Test status
Simulation time 340532730694 ps
CPU time 175.2 seconds
Started Mar 17 12:28:37 PM PDT 24
Finished Mar 17 12:31:33 PM PDT 24
Peak memory 210088 kb
Host smart-9773af1f-6913-4de1-90e5-429ab9350204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840596737 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.840596737
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.278556367
Short name T647
Test name
Test status
Simulation time 533915279 ps
CPU time 1.21 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:28:59 PM PDT 24
Peak memory 201372 kb
Host smart-24daf1a3-776a-4a27-93da-e4a35839c93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278556367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.278556367
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2219347199
Short name T276
Test name
Test status
Simulation time 172350271655 ps
CPU time 339.9 seconds
Started Mar 17 12:28:44 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 201772 kb
Host smart-cf60398b-2d2d-4cce-a328-143c9647e90b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219347199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2219347199
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.517743015
Short name T607
Test name
Test status
Simulation time 360797611899 ps
CPU time 232.17 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:32:41 PM PDT 24
Peak memory 201660 kb
Host smart-21cec214-ddee-45fc-b037-bd71b509fc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517743015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.517743015
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1333622014
Short name T497
Test name
Test status
Simulation time 159986285048 ps
CPU time 364.57 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:34:48 PM PDT 24
Peak memory 201628 kb
Host smart-1e386868-a196-462b-a187-b0c6b6fd17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333622014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1333622014
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2989901137
Short name T375
Test name
Test status
Simulation time 164911279196 ps
CPU time 366.81 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:34:50 PM PDT 24
Peak memory 201708 kb
Host smart-8c692bea-fdec-4a31-98c8-b3a44b2e4e78
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989901137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2989901137
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.718361333
Short name T159
Test name
Test status
Simulation time 325347111687 ps
CPU time 206.87 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:32:15 PM PDT 24
Peak memory 201772 kb
Host smart-5db1985a-20cb-4d02-8058-abcad3a9298f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718361333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.718361333
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1255243694
Short name T434
Test name
Test status
Simulation time 168012835970 ps
CPU time 240.95 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:32:48 PM PDT 24
Peak memory 201544 kb
Host smart-c513be84-8be9-4ab0-8d30-7aeb15cf1268
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255243694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1255243694
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.660342174
Short name T590
Test name
Test status
Simulation time 545394898145 ps
CPU time 598.51 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:38:45 PM PDT 24
Peak memory 201716 kb
Host smart-010d8fa8-4486-4a8a-aaf5-18008a9ca1bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660342174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.660342174
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.417778900
Short name T335
Test name
Test status
Simulation time 614802503837 ps
CPU time 128.9 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:30:53 PM PDT 24
Peak memory 201652 kb
Host smart-35529f41-201a-4eaf-ab73-3d11d407f466
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417778900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.417778900
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3916296484
Short name T48
Test name
Test status
Simulation time 109022352328 ps
CPU time 420.57 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:35:51 PM PDT 24
Peak memory 201936 kb
Host smart-0789c8e7-e6c3-4d01-951a-209f072f373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916296484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3916296484
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3952078749
Short name T456
Test name
Test status
Simulation time 35434235023 ps
CPU time 4.99 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:28:51 PM PDT 24
Peak memory 201464 kb
Host smart-b4f66748-37ac-4d02-8732-897ef7275c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952078749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3952078749
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1145775706
Short name T783
Test name
Test status
Simulation time 4372740089 ps
CPU time 2.33 seconds
Started Mar 17 12:28:42 PM PDT 24
Finished Mar 17 12:28:45 PM PDT 24
Peak memory 201440 kb
Host smart-b29d5d93-685d-4f63-8005-5b0318e4f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145775706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1145775706
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4006087879
Short name T610
Test name
Test status
Simulation time 6276568141 ps
CPU time 4.49 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:28:48 PM PDT 24
Peak memory 201448 kb
Host smart-45d1346d-e147-4f9b-bbce-b0600215cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006087879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4006087879
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2715999194
Short name T273
Test name
Test status
Simulation time 41277844921 ps
CPU time 53.22 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:29:42 PM PDT 24
Peak memory 210104 kb
Host smart-9b05ff6c-c1e3-4915-bab2-4478fc52a7d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715999194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2715999194
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1598197453
Short name T685
Test name
Test status
Simulation time 391402388 ps
CPU time 1.48 seconds
Started Mar 17 12:25:38 PM PDT 24
Finished Mar 17 12:25:40 PM PDT 24
Peak memory 201600 kb
Host smart-70509fea-5b62-4755-bd32-6035c5cd437a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598197453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1598197453
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1221231918
Short name T124
Test name
Test status
Simulation time 163514143105 ps
CPU time 233.15 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:31:54 PM PDT 24
Peak memory 201480 kb
Host smart-19e3751e-fc01-4e74-bfff-aa278ced7532
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221231918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1221231918
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2967027631
Short name T275
Test name
Test status
Simulation time 342151500508 ps
CPU time 208.53 seconds
Started Mar 17 12:25:39 PM PDT 24
Finished Mar 17 12:29:09 PM PDT 24
Peak memory 201748 kb
Host smart-3c9cc370-8fb4-430f-94b7-4fb6e586178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967027631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2967027631
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.227461113
Short name T169
Test name
Test status
Simulation time 326509511971 ps
CPU time 734.85 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:40:14 PM PDT 24
Peak memory 200268 kb
Host smart-5f4b50f2-3147-4bb1-ad80-36d56a7dd081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227461113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.227461113
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2505797808
Short name T495
Test name
Test status
Simulation time 162390927150 ps
CPU time 116.39 seconds
Started Mar 17 12:28:12 PM PDT 24
Finished Mar 17 12:30:08 PM PDT 24
Peak memory 201820 kb
Host smart-8b2a465e-ed10-4b90-8e1b-6dfa05600ada
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505797808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2505797808
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1102725866
Short name T539
Test name
Test status
Simulation time 165142110173 ps
CPU time 186 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:31:07 PM PDT 24
Peak memory 200144 kb
Host smart-bafb47a5-d4e7-4f4b-8d2f-c1210d70bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102725866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1102725866
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.619552487
Short name T769
Test name
Test status
Simulation time 322804000629 ps
CPU time 682.63 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:39:24 PM PDT 24
Peak memory 200024 kb
Host smart-b143d5a4-bd41-4042-be3d-b2673ae91de5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=619552487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.619552487
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2547500393
Short name T168
Test name
Test status
Simulation time 421260600273 ps
CPU time 266.01 seconds
Started Mar 17 12:27:50 PM PDT 24
Finished Mar 17 12:32:16 PM PDT 24
Peak memory 201488 kb
Host smart-c6588351-a049-46bb-a2d1-6c77193d79b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547500393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2547500393
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3196999713
Short name T543
Test name
Test status
Simulation time 398193763652 ps
CPU time 349.94 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:33:55 PM PDT 24
Peak memory 201724 kb
Host smart-303a7d32-9b36-47c7-8a2c-82ffb6e4f347
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196999713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3196999713
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3837246050
Short name T671
Test name
Test status
Simulation time 37076692491 ps
CPU time 89.37 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:29:30 PM PDT 24
Peak memory 201484 kb
Host smart-bb48862c-72a4-498e-b09a-3385e6b3f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837246050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3837246050
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4212926702
Short name T363
Test name
Test status
Simulation time 2922103863 ps
CPU time 2.24 seconds
Started Mar 17 12:27:41 PM PDT 24
Finished Mar 17 12:27:43 PM PDT 24
Peak memory 200588 kb
Host smart-9981ffea-e161-4a13-8c3e-b4eb4068b780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212926702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4212926702
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4014402842
Short name T65
Test name
Test status
Simulation time 4034124539 ps
CPU time 2.61 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 217268 kb
Host smart-79a3eedf-1d15-4816-81e3-27d0dda8fcd8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014402842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4014402842
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3150373479
Short name T334
Test name
Test status
Simulation time 5961507223 ps
CPU time 4.26 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201176 kb
Host smart-93c95638-6b99-4083-b672-23aacc32b412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150373479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3150373479
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.646842743
Short name T513
Test name
Test status
Simulation time 38929726260 ps
CPU time 90.52 seconds
Started Mar 17 12:25:49 PM PDT 24
Finished Mar 17 12:27:21 PM PDT 24
Peak memory 201580 kb
Host smart-60b01afc-3822-431f-928c-1b8c18d3cc4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646842743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.646842743
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2882153316
Short name T657
Test name
Test status
Simulation time 98083156776 ps
CPU time 203.65 seconds
Started Mar 17 12:28:14 PM PDT 24
Finished Mar 17 12:31:37 PM PDT 24
Peak memory 209948 kb
Host smart-141dcf2a-30ba-4be8-85fc-5177357c8822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882153316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2882153316
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3959441299
Short name T470
Test name
Test status
Simulation time 411218650 ps
CPU time 1.61 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:28:55 PM PDT 24
Peak memory 201336 kb
Host smart-acccf717-dd33-42ad-9c80-0b438be23272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959441299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3959441299
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3158868869
Short name T683
Test name
Test status
Simulation time 175112349433 ps
CPU time 410.95 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:35:38 PM PDT 24
Peak memory 201556 kb
Host smart-4657d63f-0faf-48e9-80ec-6c04e8de45b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158868869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3158868869
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3974000210
Short name T188
Test name
Test status
Simulation time 162663610902 ps
CPU time 198.81 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:32:02 PM PDT 24
Peak memory 201488 kb
Host smart-d2425a3a-37d1-4595-b604-eabe2bb1b2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974000210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3974000210
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1233659004
Short name T150
Test name
Test status
Simulation time 501012457837 ps
CPU time 304.29 seconds
Started Mar 17 12:28:44 PM PDT 24
Finished Mar 17 12:33:49 PM PDT 24
Peak memory 201680 kb
Host smart-d0a7c91f-e2ef-4303-bb4a-984df03f29ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233659004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1233659004
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2685875055
Short name T127
Test name
Test status
Simulation time 161241097852 ps
CPU time 374.62 seconds
Started Mar 17 12:28:43 PM PDT 24
Finished Mar 17 12:34:58 PM PDT 24
Peak memory 201768 kb
Host smart-f74ac06a-b3dd-4d48-a905-ac508b3b1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685875055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2685875055
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2105155479
Short name T584
Test name
Test status
Simulation time 496536859143 ps
CPU time 543.39 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:37:52 PM PDT 24
Peak memory 201656 kb
Host smart-d73825a4-9763-40cd-9389-a3ef78fb5d34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105155479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2105155479
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3834188606
Short name T206
Test name
Test status
Simulation time 576215549662 ps
CPU time 1348 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:51:16 PM PDT 24
Peak memory 201684 kb
Host smart-896f7f5e-522b-4ba9-a483-f510b2b19a28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834188606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3834188606
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2581200065
Short name T418
Test name
Test status
Simulation time 391946056379 ps
CPU time 492.47 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:37:02 PM PDT 24
Peak memory 201696 kb
Host smart-b1be5f36-8629-437d-bcfa-cfe660419be9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581200065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2581200065
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3635990735
Short name T731
Test name
Test status
Simulation time 30328274015 ps
CPU time 71.72 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:30:06 PM PDT 24
Peak memory 201512 kb
Host smart-07fc1d71-cba7-49d2-ba09-180eb8001e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635990735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3635990735
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3000832348
Short name T476
Test name
Test status
Simulation time 2768445155 ps
CPU time 2.17 seconds
Started Mar 17 12:28:51 PM PDT 24
Finished Mar 17 12:28:53 PM PDT 24
Peak memory 201416 kb
Host smart-7130c177-0dbc-4c7f-8be0-cc691c0a0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000832348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3000832348
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2494565112
Short name T637
Test name
Test status
Simulation time 6050906492 ps
CPU time 8.13 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:28:58 PM PDT 24
Peak memory 201476 kb
Host smart-12f25fcc-dda0-4e6d-851d-007123a014b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494565112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2494565112
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1472799569
Short name T602
Test name
Test status
Simulation time 339438542568 ps
CPU time 1168.81 seconds
Started Mar 17 12:28:56 PM PDT 24
Finished Mar 17 12:48:24 PM PDT 24
Peak memory 212160 kb
Host smart-14f3a99f-887d-4a96-a03b-d08f77cbea80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472799569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1472799569
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2810800542
Short name T293
Test name
Test status
Simulation time 83565529371 ps
CPU time 109.98 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:30:50 PM PDT 24
Peak memory 210528 kb
Host smart-4a90c3d9-4661-4faf-82a9-06e0c8fd1e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810800542 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2810800542
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4117310068
Short name T512
Test name
Test status
Simulation time 303803084 ps
CPU time 0.77 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:28:56 PM PDT 24
Peak memory 201444 kb
Host smart-cdf98531-4ac2-48d4-886f-6097b9a1dd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117310068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4117310068
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2406730707
Short name T681
Test name
Test status
Simulation time 167032566154 ps
CPU time 219.22 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:32:38 PM PDT 24
Peak memory 201636 kb
Host smart-b2605e6a-6db9-4c3e-85de-02d2d72fec28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406730707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2406730707
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1904310917
Short name T565
Test name
Test status
Simulation time 160981244261 ps
CPU time 332.92 seconds
Started Mar 17 12:28:51 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 201612 kb
Host smart-3bdd9dd9-de64-4d9c-bbfa-69fca1b16442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904310917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1904310917
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2620823325
Short name T139
Test name
Test status
Simulation time 163904630540 ps
CPU time 104.27 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:30:38 PM PDT 24
Peak memory 201808 kb
Host smart-8f9cf016-943c-4b1a-9c83-580e914452c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620823325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2620823325
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1157604683
Short name T707
Test name
Test status
Simulation time 338693354163 ps
CPU time 207.3 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:32:20 PM PDT 24
Peak memory 201680 kb
Host smart-417df06a-8c1a-46c8-9225-d21e688b569c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157604683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1157604683
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.152057677
Short name T270
Test name
Test status
Simulation time 324663102257 ps
CPU time 382.44 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:35:12 PM PDT 24
Peak memory 201660 kb
Host smart-49859cf6-b446-4e03-b046-761c064231d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152057677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.152057677
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1351525857
Short name T42
Test name
Test status
Simulation time 324563815336 ps
CPU time 207.32 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:32:21 PM PDT 24
Peak memory 201628 kb
Host smart-9e867513-4837-48b9-8bb2-6e7187aa0097
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351525857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1351525857
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2763433190
Short name T537
Test name
Test status
Simulation time 168423788148 ps
CPU time 402.48 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:35:37 PM PDT 24
Peak memory 201692 kb
Host smart-5a8ec307-9c03-41eb-8ccc-077beb3a48f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763433190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2763433190
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.908649663
Short name T491
Test name
Test status
Simulation time 205017731987 ps
CPU time 250.9 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:32:59 PM PDT 24
Peak memory 201780 kb
Host smart-4877a52e-512b-409f-aa88-40baaa420fbb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908649663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.908649663
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.253314546
Short name T322
Test name
Test status
Simulation time 77609986642 ps
CPU time 456.56 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:36:31 PM PDT 24
Peak memory 202008 kb
Host smart-5508d28f-be4b-4eea-adfe-98cc8a3a3970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253314546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.253314546
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.99350129
Short name T421
Test name
Test status
Simulation time 29950953325 ps
CPU time 67.18 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:30:10 PM PDT 24
Peak memory 201496 kb
Host smart-ed4730d6-6253-4d12-b945-129d8dabde8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99350129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.99350129
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.560529401
Short name T111
Test name
Test status
Simulation time 3248235322 ps
CPU time 3.07 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:28:56 PM PDT 24
Peak memory 201380 kb
Host smart-81207706-abd2-4f8f-bdb4-cec76e33e77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560529401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.560529401
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4139813043
Short name T490
Test name
Test status
Simulation time 5818965963 ps
CPU time 2.96 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:28:58 PM PDT 24
Peak memory 201460 kb
Host smart-c914ffc7-17b6-41ab-97c5-ba1e4828c425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139813043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4139813043
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.201008384
Short name T316
Test name
Test status
Simulation time 72428491004 ps
CPU time 139.79 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:31:13 PM PDT 24
Peak memory 217920 kb
Host smart-111cf47b-fced-466c-a7da-527a552661e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201008384 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.201008384
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2444088729
Short name T409
Test name
Test status
Simulation time 376893081 ps
CPU time 1.05 seconds
Started Mar 17 12:28:45 PM PDT 24
Finished Mar 17 12:28:46 PM PDT 24
Peak memory 201432 kb
Host smart-a88caad2-9425-4927-88ff-bae8b4d04c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444088729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2444088729
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.4074580868
Short name T137
Test name
Test status
Simulation time 500333944827 ps
CPU time 372.48 seconds
Started Mar 17 12:28:50 PM PDT 24
Finished Mar 17 12:35:03 PM PDT 24
Peak memory 201640 kb
Host smart-bcfc128c-216a-4f75-b0dc-f9cdacecffa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074580868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.4074580868
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2039620646
Short name T717
Test name
Test status
Simulation time 502220065110 ps
CPU time 186.49 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:32:00 PM PDT 24
Peak memory 201724 kb
Host smart-cfc2d4d2-6947-4998-9f7c-e336d8a2f185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039620646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2039620646
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3529633292
Short name T6
Test name
Test status
Simulation time 163115167128 ps
CPU time 375.35 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:35:14 PM PDT 24
Peak memory 201680 kb
Host smart-3a613a39-1c44-45db-b200-75fb1f1f4228
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529633292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3529633292
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1625396902
Short name T715
Test name
Test status
Simulation time 164078343821 ps
CPU time 395.31 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:35:24 PM PDT 24
Peak memory 201560 kb
Host smart-c3b4ff07-90e2-4e02-adc6-cc22c2c7a72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625396902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1625396902
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.333089569
Short name T11
Test name
Test status
Simulation time 171145914319 ps
CPU time 397.38 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 201668 kb
Host smart-73ee47c4-de91-4a16-bed9-cc18800e75ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=333089569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.333089569
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.246536652
Short name T548
Test name
Test status
Simulation time 348328580256 ps
CPU time 371.77 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 201632 kb
Host smart-8b97b17f-421e-4293-ab96-d6e74155be39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246536652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.246536652
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.205684212
Short name T625
Test name
Test status
Simulation time 611935700577 ps
CPU time 720.75 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:40:56 PM PDT 24
Peak memory 201716 kb
Host smart-f95419e2-023b-4884-bda2-53879986f337
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205684212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.205684212
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.590468778
Short name T570
Test name
Test status
Simulation time 117478433979 ps
CPU time 499.29 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:37:21 PM PDT 24
Peak memory 202064 kb
Host smart-738a7286-5464-4120-bcc4-0c49ab24638d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590468778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.590468778
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3880893883
Short name T582
Test name
Test status
Simulation time 29118678873 ps
CPU time 17.49 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:29:10 PM PDT 24
Peak memory 201444 kb
Host smart-ab1516d5-57c8-44d2-a27b-7c87ffc324f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880893883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3880893883
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3980436140
Short name T720
Test name
Test status
Simulation time 5383668012 ps
CPU time 5.32 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:28:59 PM PDT 24
Peak memory 201480 kb
Host smart-4a8d71a4-b0cc-4efa-813e-7d9181a67000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980436140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3980436140
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3976541938
Short name T405
Test name
Test status
Simulation time 6019539187 ps
CPU time 2.43 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 201408 kb
Host smart-55824d90-8185-4e9f-ab01-0f997bb3f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976541938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3976541938
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1857311286
Short name T736
Test name
Test status
Simulation time 236147699754 ps
CPU time 1190.51 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:48:53 PM PDT 24
Peak memory 202008 kb
Host smart-1a7069bb-83c7-4878-9b2d-de0b393defdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857311286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1857311286
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3447668525
Short name T313
Test name
Test status
Simulation time 39927207312 ps
CPU time 96.98 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:30:35 PM PDT 24
Peak memory 218456 kb
Host smart-d58005fb-458f-402c-8b5e-88d524fa3e02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447668525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3447668525
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.648924313
Short name T342
Test name
Test status
Simulation time 303016334 ps
CPU time 1.24 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:29:04 PM PDT 24
Peak memory 201384 kb
Host smart-8c71f401-37d0-463d-9969-c5bd28a29298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648924313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.648924313
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2652042985
Short name T121
Test name
Test status
Simulation time 182549707521 ps
CPU time 59.56 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:29:53 PM PDT 24
Peak memory 201704 kb
Host smart-3d027eb7-9b39-4a6a-87d6-943c5d60293b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652042985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2652042985
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3170948227
Short name T199
Test name
Test status
Simulation time 528516988099 ps
CPU time 1143.32 seconds
Started Mar 17 12:28:44 PM PDT 24
Finished Mar 17 12:47:48 PM PDT 24
Peak memory 201660 kb
Host smart-a04771e4-1eeb-4dff-be1e-42fe2770bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170948227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3170948227
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1564173140
Short name T628
Test name
Test status
Simulation time 164761922812 ps
CPU time 190.91 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:32:06 PM PDT 24
Peak memory 201688 kb
Host smart-6d19c186-7d07-4814-8e7c-ae81e365f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564173140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1564173140
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.93349761
Short name T629
Test name
Test status
Simulation time 163615693088 ps
CPU time 391.23 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:35:34 PM PDT 24
Peak memory 201652 kb
Host smart-5fae2bd0-56b8-45ee-b9af-807ee9e139f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=93349761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt
_fixed.93349761
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.994556909
Short name T431
Test name
Test status
Simulation time 168137288449 ps
CPU time 377.25 seconds
Started Mar 17 12:28:47 PM PDT 24
Finished Mar 17 12:35:04 PM PDT 24
Peak memory 201792 kb
Host smart-f5185b94-0c2e-4975-bfe8-0a8acd5bf768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994556909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.994556909
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2401959049
Short name T461
Test name
Test status
Simulation time 488815167834 ps
CPU time 1229.62 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:49:30 PM PDT 24
Peak memory 201760 kb
Host smart-a1b4fb69-f906-4cce-b4ed-bbca85f1df49
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401959049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2401959049
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2336842203
Short name T138
Test name
Test status
Simulation time 175551656203 ps
CPU time 66.71 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:30:05 PM PDT 24
Peak memory 201692 kb
Host smart-c59c956b-fd4d-4b56-86e4-7295f270e0be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336842203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2336842203
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.412041049
Short name T381
Test name
Test status
Simulation time 200076543668 ps
CPU time 215.36 seconds
Started Mar 17 12:28:49 PM PDT 24
Finished Mar 17 12:32:25 PM PDT 24
Peak memory 201628 kb
Host smart-4a9a5bda-b9a7-43ec-8f34-3bdd3ef591b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412041049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.412041049
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1902321143
Short name T572
Test name
Test status
Simulation time 135796439052 ps
CPU time 729.35 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:41:01 PM PDT 24
Peak memory 202016 kb
Host smart-8be6b617-a28a-483e-8537-747159b6c76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902321143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1902321143
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3549644408
Short name T355
Test name
Test status
Simulation time 29788310574 ps
CPU time 17.08 seconds
Started Mar 17 12:28:51 PM PDT 24
Finished Mar 17 12:29:08 PM PDT 24
Peak memory 201448 kb
Host smart-2decf8ca-19d6-4ecd-ba5a-eb20cc9d0f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549644408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3549644408
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2567456638
Short name T492
Test name
Test status
Simulation time 2722372459 ps
CPU time 3.92 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:02 PM PDT 24
Peak memory 201392 kb
Host smart-6d5e1b3e-ee67-4e72-b34e-a453701d114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567456638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2567456638
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.232130518
Short name T679
Test name
Test status
Simulation time 5771521901 ps
CPU time 3.75 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:28:57 PM PDT 24
Peak memory 201492 kb
Host smart-032c2b46-ddf3-4c39-8792-2b055f3da82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232130518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.232130518
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2053957072
Short name T230
Test name
Test status
Simulation time 381818371521 ps
CPU time 94.36 seconds
Started Mar 17 12:28:57 PM PDT 24
Finished Mar 17 12:30:31 PM PDT 24
Peak memory 201612 kb
Host smart-d27b31a0-89a6-480e-8e64-27981ba399e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053957072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2053957072
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1862460707
Short name T14
Test name
Test status
Simulation time 81876497563 ps
CPU time 88.72 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:30:21 PM PDT 24
Peak memory 201748 kb
Host smart-2d6489d5-b739-42f9-9c75-f5d8df6fe734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862460707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1862460707
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.303365532
Short name T477
Test name
Test status
Simulation time 292201887 ps
CPU time 1.22 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 201376 kb
Host smart-0324623d-0320-44b2-b3ca-bc6ba944c168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303365532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.303365532
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3979340820
Short name T514
Test name
Test status
Simulation time 206282674742 ps
CPU time 443.98 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:36:26 PM PDT 24
Peak memory 201692 kb
Host smart-9ab484b1-081e-4ef0-b6a2-dc7623944c98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979340820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3979340820
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.820659827
Short name T116
Test name
Test status
Simulation time 335952378348 ps
CPU time 525 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:37:43 PM PDT 24
Peak memory 201612 kb
Host smart-bbed2283-7426-4bae-af1d-dfeb529a6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820659827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.820659827
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3740898829
Short name T576
Test name
Test status
Simulation time 164439176636 ps
CPU time 336.93 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:34:31 PM PDT 24
Peak memory 201628 kb
Host smart-fbad3361-ca42-42da-88a6-d2453b91c971
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740898829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3740898829
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.29313912
Short name T184
Test name
Test status
Simulation time 326024802866 ps
CPU time 360.83 seconds
Started Mar 17 12:28:53 PM PDT 24
Finished Mar 17 12:34:54 PM PDT 24
Peak memory 201660 kb
Host smart-a66bbb6a-4bfb-4f88-9bc0-c931a4182401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29313912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.29313912
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4154511811
Short name T653
Test name
Test status
Simulation time 498351623522 ps
CPU time 291.2 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:33:46 PM PDT 24
Peak memory 201636 kb
Host smart-2f0a9774-7fdd-4bdb-b508-cb8ddd309529
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154511811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4154511811
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3247446593
Short name T240
Test name
Test status
Simulation time 552134330719 ps
CPU time 288 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:33:48 PM PDT 24
Peak memory 201684 kb
Host smart-85831f45-9cf9-4e4e-bf7f-b41a63c37e1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247446593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3247446593
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1005095126
Short name T541
Test name
Test status
Simulation time 211891932708 ps
CPU time 148.43 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:31:30 PM PDT 24
Peak memory 201760 kb
Host smart-15c66c6c-9895-471d-8625-edde3199b024
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005095126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1005095126
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4083564961
Short name T179
Test name
Test status
Simulation time 93903954636 ps
CPU time 330.05 seconds
Started Mar 17 12:30:23 PM PDT 24
Finished Mar 17 12:35:53 PM PDT 24
Peak memory 201744 kb
Host smart-ad15e674-7611-4a2b-ba44-d26bb524376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083564961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4083564961
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2143889167
Short name T643
Test name
Test status
Simulation time 38724653607 ps
CPU time 10.23 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:29:11 PM PDT 24
Peak memory 201484 kb
Host smart-86788381-cfd0-4a13-b47b-ccac4e823630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143889167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2143889167
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1217317777
Short name T622
Test name
Test status
Simulation time 5479072311 ps
CPU time 12.48 seconds
Started Mar 17 12:28:54 PM PDT 24
Finished Mar 17 12:29:06 PM PDT 24
Peak memory 201508 kb
Host smart-7a78af59-eecf-4b76-b091-61f93f613cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217317777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1217317777
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1819048718
Short name T773
Test name
Test status
Simulation time 5978323694 ps
CPU time 8.31 seconds
Started Mar 17 12:30:23 PM PDT 24
Finished Mar 17 12:30:32 PM PDT 24
Peak memory 201256 kb
Host smart-a580e7d9-157b-4760-9fc3-ce76c6a5f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819048718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1819048718
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4040134418
Short name T252
Test name
Test status
Simulation time 356324861217 ps
CPU time 220.99 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:32:42 PM PDT 24
Peak memory 201668 kb
Host smart-7d61577d-b057-4aa6-b4ae-9851a1bbf05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040134418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4040134418
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2741236487
Short name T34
Test name
Test status
Simulation time 169411907738 ps
CPU time 140.93 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:31:20 PM PDT 24
Peak memory 216040 kb
Host smart-82b17664-87f7-476d-9fb9-0a36eaa10774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741236487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2741236487
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3762791347
Short name T328
Test name
Test status
Simulation time 355421395 ps
CPU time 0.79 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 201392 kb
Host smart-3bd7408b-ce8a-43d3-bb27-0836bdb78072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762791347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3762791347
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.541943858
Short name T146
Test name
Test status
Simulation time 528463893652 ps
CPU time 633.75 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:39:34 PM PDT 24
Peak memory 201752 kb
Host smart-f0e8088e-2ce9-46ee-8426-29412b90a351
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541943858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.541943858
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2216900741
Short name T118
Test name
Test status
Simulation time 177939536079 ps
CPU time 157.85 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:31:33 PM PDT 24
Peak memory 201576 kb
Host smart-9e0a5c69-b693-46a9-890d-283116a59b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216900741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2216900741
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.693808353
Short name T245
Test name
Test status
Simulation time 166661797830 ps
CPU time 115.25 seconds
Started Mar 17 12:29:01 PM PDT 24
Finished Mar 17 12:30:56 PM PDT 24
Peak memory 201792 kb
Host smart-a12336f5-71a6-4b05-ad22-045fe341108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693808353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.693808353
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3937754140
Short name T551
Test name
Test status
Simulation time 323038372023 ps
CPU time 712.73 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:40:53 PM PDT 24
Peak memory 201680 kb
Host smart-2ac5cabe-051a-4f81-b69e-c83b3a20ea7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937754140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3937754140
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.36257467
Short name T289
Test name
Test status
Simulation time 325116620741 ps
CPU time 720.35 seconds
Started Mar 17 12:29:01 PM PDT 24
Finished Mar 17 12:41:02 PM PDT 24
Peak memory 201676 kb
Host smart-1250a250-303e-47b9-97e3-b2b9ec74c797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36257467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.36257467
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3919859447
Short name T346
Test name
Test status
Simulation time 165094776662 ps
CPU time 363.53 seconds
Started Mar 17 12:28:46 PM PDT 24
Finished Mar 17 12:34:50 PM PDT 24
Peak memory 201960 kb
Host smart-8b815bb9-d522-4062-bf66-4a4d38aeec9c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919859447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3919859447
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3293225032
Short name T449
Test name
Test status
Simulation time 595145901282 ps
CPU time 76.65 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:30:16 PM PDT 24
Peak memory 201668 kb
Host smart-2d00a694-2aa5-4a4d-b352-e55ab812d716
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293225032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3293225032
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1153808039
Short name T609
Test name
Test status
Simulation time 125223047778 ps
CPU time 427.25 seconds
Started Mar 17 12:29:03 PM PDT 24
Finished Mar 17 12:36:11 PM PDT 24
Peak memory 202108 kb
Host smart-6031ff94-5d6e-4aab-925b-8fdd098364d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153808039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1153808039
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2077418159
Short name T463
Test name
Test status
Simulation time 26066340433 ps
CPU time 29.05 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:29:33 PM PDT 24
Peak memory 201440 kb
Host smart-2015de61-88cb-4433-a5f3-b5af59e622ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077418159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2077418159
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.454267932
Short name T344
Test name
Test status
Simulation time 3777349431 ps
CPU time 9.5 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:29:11 PM PDT 24
Peak memory 201456 kb
Host smart-78db5986-5f72-490f-a59c-ba0689200771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454267932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.454267932
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3864038726
Short name T784
Test name
Test status
Simulation time 6064022239 ps
CPU time 2.74 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:29:02 PM PDT 24
Peak memory 201492 kb
Host smart-c78989fd-40eb-4abb-844f-65cbce7ca205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864038726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3864038726
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2146925584
Short name T17
Test name
Test status
Simulation time 311612859676 ps
CPU time 242.7 seconds
Started Mar 17 12:28:57 PM PDT 24
Finished Mar 17 12:32:59 PM PDT 24
Peak memory 210312 kb
Host smart-b1ec63a9-3a41-41c3-b5b5-22df8cfeac52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146925584 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2146925584
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1783206247
Short name T780
Test name
Test status
Simulation time 435540079 ps
CPU time 0.69 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:29:03 PM PDT 24
Peak memory 201400 kb
Host smart-f0f67cdc-66ad-4294-b4e7-9b18e720c7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783206247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1783206247
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.790877544
Short name T750
Test name
Test status
Simulation time 562332153168 ps
CPU time 1279.01 seconds
Started Mar 17 12:29:36 PM PDT 24
Finished Mar 17 12:50:55 PM PDT 24
Peak memory 201608 kb
Host smart-12cdc4b4-97fc-4c4c-b8b3-7693f3ae5b46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790877544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.790877544
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1226825050
Short name T271
Test name
Test status
Simulation time 166678787252 ps
CPU time 285.68 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:33:46 PM PDT 24
Peak memory 201780 kb
Host smart-7fdedf75-be03-41f3-9d63-1ced47b9b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226825050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1226825050
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.960808511
Short name T423
Test name
Test status
Simulation time 502035312945 ps
CPU time 1188.19 seconds
Started Mar 17 12:29:03 PM PDT 24
Finished Mar 17 12:48:52 PM PDT 24
Peak memory 201796 kb
Host smart-cc52ed37-c8ac-4337-95dc-8d1129b8fada
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=960808511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.960808511
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2085607223
Short name T435
Test name
Test status
Simulation time 162747535654 ps
CPU time 43.67 seconds
Started Mar 17 12:28:56 PM PDT 24
Finished Mar 17 12:29:40 PM PDT 24
Peak memory 201672 kb
Host smart-6031c092-97bd-48a7-9aa5-807c47ba1f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085607223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2085607223
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1643827385
Short name T768
Test name
Test status
Simulation time 490471244062 ps
CPU time 262.16 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:33:22 PM PDT 24
Peak memory 201572 kb
Host smart-e30e7f63-bdf5-421f-8b26-ee1708686ea4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643827385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1643827385
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.672010943
Short name T754
Test name
Test status
Simulation time 195611013986 ps
CPU time 429.31 seconds
Started Mar 17 12:28:52 PM PDT 24
Finished Mar 17 12:36:01 PM PDT 24
Peak memory 201580 kb
Host smart-8cb6c7aa-e795-43be-af17-e295bc13198c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672010943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.672010943
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1378690216
Short name T329
Test name
Test status
Simulation time 200129230716 ps
CPU time 503.29 seconds
Started Mar 17 12:29:22 PM PDT 24
Finished Mar 17 12:37:46 PM PDT 24
Peak memory 201628 kb
Host smart-0512be4b-7a68-4162-b801-142c97d5474a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378690216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1378690216
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2288795515
Short name T386
Test name
Test status
Simulation time 130518438601 ps
CPU time 592.44 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:38:51 PM PDT 24
Peak memory 202096 kb
Host smart-52227f15-79cf-44a1-bcd3-7b2bb2c51993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288795515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2288795515
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2000863187
Short name T682
Test name
Test status
Simulation time 26249700837 ps
CPU time 7.73 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:06 PM PDT 24
Peak memory 201500 kb
Host smart-b49ac80f-7a5a-4212-8ae0-73a6456f15fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000863187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2000863187
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2080263902
Short name T583
Test name
Test status
Simulation time 3533716405 ps
CPU time 2.4 seconds
Started Mar 17 12:29:01 PM PDT 24
Finished Mar 17 12:29:03 PM PDT 24
Peak memory 201444 kb
Host smart-c8b99cf3-90a8-406e-8ea6-1fe63938e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080263902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2080263902
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2422334500
Short name T404
Test name
Test status
Simulation time 5823315564 ps
CPU time 4.12 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:29:04 PM PDT 24
Peak memory 201436 kb
Host smart-38c8d222-0900-46be-a38d-299a4ebfc19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422334500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2422334500
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4129005192
Short name T658
Test name
Test status
Simulation time 28245085244 ps
CPU time 63.05 seconds
Started Mar 17 12:28:55 PM PDT 24
Finished Mar 17 12:29:59 PM PDT 24
Peak memory 201896 kb
Host smart-1059443c-ab3f-4a0e-b1c6-aa1e6b7814f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129005192 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4129005192
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2162577744
Short name T617
Test name
Test status
Simulation time 451188532 ps
CPU time 1.69 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:29:00 PM PDT 24
Peak memory 201388 kb
Host smart-1b5d5155-a022-46d9-a21d-2b2a026bd8f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162577744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2162577744
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2449358317
Short name T660
Test name
Test status
Simulation time 166438123359 ps
CPU time 199.38 seconds
Started Mar 17 12:29:03 PM PDT 24
Finished Mar 17 12:32:22 PM PDT 24
Peak memory 201700 kb
Host smart-a8cc5728-9b61-44ae-ab88-2e1822074d3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449358317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2449358317
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.376619180
Short name T574
Test name
Test status
Simulation time 350379749270 ps
CPU time 200.97 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:32:21 PM PDT 24
Peak memory 201720 kb
Host smart-6bd014a7-725b-46f3-9fea-2ac8670f6878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376619180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.376619180
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4152130796
Short name T251
Test name
Test status
Simulation time 155935903252 ps
CPU time 347.58 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:34:47 PM PDT 24
Peak memory 201740 kb
Host smart-9d661232-9c5c-4a1e-a0a7-0425de3d607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152130796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4152130796
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.598813435
Short name T552
Test name
Test status
Simulation time 161400212355 ps
CPU time 364.38 seconds
Started Mar 17 12:30:23 PM PDT 24
Finished Mar 17 12:36:27 PM PDT 24
Peak memory 201440 kb
Host smart-d89c4fbd-693d-4c3a-bc1d-e56f024f9a94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=598813435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.598813435
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1810287640
Short name T508
Test name
Test status
Simulation time 162753672246 ps
CPU time 270.04 seconds
Started Mar 17 12:29:03 PM PDT 24
Finished Mar 17 12:33:33 PM PDT 24
Peak memory 201816 kb
Host smart-fa4a856c-9ef0-4a20-88e7-741b5edbe3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810287640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1810287640
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4232953106
Short name T544
Test name
Test status
Simulation time 497899798461 ps
CPU time 740.89 seconds
Started Mar 17 12:31:18 PM PDT 24
Finished Mar 17 12:43:39 PM PDT 24
Peak memory 201640 kb
Host smart-9d42dd5e-2afd-491a-8ec6-2cc874c9e551
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232953106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4232953106
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3362185050
Short name T310
Test name
Test status
Simulation time 202358043463 ps
CPU time 135.83 seconds
Started Mar 17 12:30:22 PM PDT 24
Finished Mar 17 12:32:38 PM PDT 24
Peak memory 201540 kb
Host smart-012ba132-fdc7-46cf-b34b-9535e52ba7de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362185050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3362185050
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1364761646
Short name T460
Test name
Test status
Simulation time 576714289601 ps
CPU time 324.06 seconds
Started Mar 17 12:29:22 PM PDT 24
Finished Mar 17 12:34:47 PM PDT 24
Peak memory 201716 kb
Host smart-c57d118a-4b05-4bd8-9ede-e07b1e3cf275
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364761646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1364761646
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2846960004
Short name T175
Test name
Test status
Simulation time 125833964237 ps
CPU time 491.73 seconds
Started Mar 17 12:30:15 PM PDT 24
Finished Mar 17 12:38:28 PM PDT 24
Peak memory 200476 kb
Host smart-ca046fa0-2d92-4e9f-a4dd-198c40f64ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846960004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2846960004
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2605118750
Short name T592
Test name
Test status
Simulation time 37403143140 ps
CPU time 83.72 seconds
Started Mar 17 12:28:56 PM PDT 24
Finished Mar 17 12:30:20 PM PDT 24
Peak memory 201468 kb
Host smart-27de460c-7ed8-4920-a590-18fd5efc6481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605118750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2605118750
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.173099810
Short name T365
Test name
Test status
Simulation time 3135704901 ps
CPU time 8.46 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:07 PM PDT 24
Peak memory 201400 kb
Host smart-fd6f0b9c-67df-45e9-b168-5fc47fc9c1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173099810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.173099810
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2849209096
Short name T571
Test name
Test status
Simulation time 5922707354 ps
CPU time 1.78 seconds
Started Mar 17 12:29:20 PM PDT 24
Finished Mar 17 12:29:22 PM PDT 24
Peak memory 201596 kb
Host smart-0201d13c-f6bb-465f-a2f4-861194f6df8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849209096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2849209096
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3611667109
Short name T380
Test name
Test status
Simulation time 657138957 ps
CPU time 0.67 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:29:01 PM PDT 24
Peak memory 201332 kb
Host smart-16cba4a4-4f99-47b1-be9b-77de4494a298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611667109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3611667109
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.538978170
Short name T217
Test name
Test status
Simulation time 185039566723 ps
CPU time 436.93 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:36:21 PM PDT 24
Peak memory 201748 kb
Host smart-cc3769eb-7071-48c6-bfbc-9890566e6f08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538978170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.538978170
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3832841212
Short name T158
Test name
Test status
Simulation time 330106037043 ps
CPU time 221.96 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:32:41 PM PDT 24
Peak memory 201732 kb
Host smart-77860f3a-d589-4c7c-a7c2-a7a4e95981bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832841212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3832841212
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.412442692
Short name T437
Test name
Test status
Simulation time 334026077035 ps
CPU time 780.28 seconds
Started Mar 17 12:30:22 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 201504 kb
Host smart-1358c2f8-401e-43ea-8001-c3a53f94d47f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412442692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.412442692
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.274254665
Short name T309
Test name
Test status
Simulation time 485469907449 ps
CPU time 1168 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:48:28 PM PDT 24
Peak memory 201792 kb
Host smart-0cd7f4f4-11fd-4b42-8a31-d3f9ef4ae5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274254665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.274254665
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2978017222
Short name T369
Test name
Test status
Simulation time 331265967473 ps
CPU time 775.72 seconds
Started Mar 17 12:30:15 PM PDT 24
Finished Mar 17 12:43:12 PM PDT 24
Peak memory 199884 kb
Host smart-3bbb25d7-1889-4ee4-a1e1-96a491721bf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978017222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2978017222
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3822001673
Short name T764
Test name
Test status
Simulation time 192115841401 ps
CPU time 118.75 seconds
Started Mar 17 12:30:22 PM PDT 24
Finished Mar 17 12:32:21 PM PDT 24
Peak memory 201524 kb
Host smart-38a7ffaf-3a19-4591-8f49-ac47f507cc48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822001673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3822001673
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3433665616
Short name T522
Test name
Test status
Simulation time 598538063915 ps
CPU time 339.38 seconds
Started Mar 17 12:30:15 PM PDT 24
Finished Mar 17 12:35:55 PM PDT 24
Peak memory 199808 kb
Host smart-f85aba1b-aba6-427d-9d16-295b89a5ddf3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433665616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3433665616
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1131543833
Short name T459
Test name
Test status
Simulation time 92113171649 ps
CPU time 555.99 seconds
Started Mar 17 12:29:05 PM PDT 24
Finished Mar 17 12:38:21 PM PDT 24
Peak memory 202116 kb
Host smart-bce3f2b5-0525-451d-a1e2-e27acca5531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131543833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1131543833
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.345961545
Short name T561
Test name
Test status
Simulation time 37891419540 ps
CPU time 41.83 seconds
Started Mar 17 12:29:52 PM PDT 24
Finished Mar 17 12:30:34 PM PDT 24
Peak memory 201456 kb
Host smart-f036a8c2-75a3-44bd-8511-2858d1742798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345961545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.345961545
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2803467520
Short name T131
Test name
Test status
Simulation time 5006415610 ps
CPU time 3.71 seconds
Started Mar 17 12:30:23 PM PDT 24
Finished Mar 17 12:30:27 PM PDT 24
Peak memory 201252 kb
Host smart-bb25129f-aea1-42c5-969c-4f1cc1423eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803467520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2803467520
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.4287846125
Short name T397
Test name
Test status
Simulation time 5635486919 ps
CPU time 13.3 seconds
Started Mar 17 12:28:58 PM PDT 24
Finished Mar 17 12:29:11 PM PDT 24
Peak memory 201524 kb
Host smart-fc1fc8e1-856c-46e1-95f2-d3f73bef43ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287846125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.4287846125
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3627618096
Short name T226
Test name
Test status
Simulation time 399692954063 ps
CPU time 925.34 seconds
Started Mar 17 12:29:03 PM PDT 24
Finished Mar 17 12:44:28 PM PDT 24
Peak memory 201760 kb
Host smart-77b99dc3-2e50-4b7e-87af-a97f58666c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627618096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3627618096
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2737147500
Short name T291
Test name
Test status
Simulation time 89795271464 ps
CPU time 53.64 seconds
Started Mar 17 12:30:22 PM PDT 24
Finished Mar 17 12:31:16 PM PDT 24
Peak memory 209744 kb
Host smart-d4e34650-0e96-4530-8d31-3cdfebbf8c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737147500 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2737147500
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3956270893
Short name T699
Test name
Test status
Simulation time 483008119 ps
CPU time 1.21 seconds
Started Mar 17 12:29:22 PM PDT 24
Finished Mar 17 12:29:23 PM PDT 24
Peak memory 201352 kb
Host smart-17f2c79b-569c-473c-9ddd-41ddccd5ab65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956270893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3956270893
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3336054227
Short name T560
Test name
Test status
Simulation time 465527929014 ps
CPU time 506.68 seconds
Started Mar 17 12:29:05 PM PDT 24
Finished Mar 17 12:37:32 PM PDT 24
Peak memory 201676 kb
Host smart-a4c8ca6e-b4b7-49f4-87ab-28581b72b433
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336054227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3336054227
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2297167557
Short name T211
Test name
Test status
Simulation time 494111584903 ps
CPU time 483.79 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:37:16 PM PDT 24
Peak memory 201692 kb
Host smart-39b24fa0-15d4-4084-be58-59b4de980ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297167557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2297167557
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2187641310
Short name T692
Test name
Test status
Simulation time 164103993435 ps
CPU time 92.09 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:30:32 PM PDT 24
Peak memory 201584 kb
Host smart-9edfe492-1057-4327-9dfd-66110fed12d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187641310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2187641310
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2531875900
Short name T536
Test name
Test status
Simulation time 163464058162 ps
CPU time 187.74 seconds
Started Mar 17 12:29:00 PM PDT 24
Finished Mar 17 12:32:08 PM PDT 24
Peak memory 201724 kb
Host smart-d0ab7db7-e06a-4fb5-821b-ca30925c66a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531875900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2531875900
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.748296068
Short name T311
Test name
Test status
Simulation time 501774892885 ps
CPU time 282.7 seconds
Started Mar 17 12:29:05 PM PDT 24
Finished Mar 17 12:33:47 PM PDT 24
Peak memory 201648 kb
Host smart-15d045c6-db7f-42f8-89a6-9316833bfca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748296068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.748296068
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.944139651
Short name T767
Test name
Test status
Simulation time 493969785076 ps
CPU time 303.66 seconds
Started Mar 17 12:29:18 PM PDT 24
Finished Mar 17 12:34:21 PM PDT 24
Peak memory 201712 kb
Host smart-4d71a6d7-ae6f-4c1a-b2de-62bf18ea5631
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=944139651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.944139651
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.750996193
Short name T189
Test name
Test status
Simulation time 557497265771 ps
CPU time 1274.27 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:50:19 PM PDT 24
Peak memory 201680 kb
Host smart-634d5fb6-aad3-4617-b23b-79b53a0bf331
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750996193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.750996193
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2000397820
Short name T763
Test name
Test status
Simulation time 206570346956 ps
CPU time 253.9 seconds
Started Mar 17 12:29:02 PM PDT 24
Finished Mar 17 12:33:16 PM PDT 24
Peak memory 201728 kb
Host smart-afa9aaa2-3a12-43cb-8198-e74f6a4bc3a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000397820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2000397820
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2748204713
Short name T745
Test name
Test status
Simulation time 29388020540 ps
CPU time 66.39 seconds
Started Mar 17 12:28:59 PM PDT 24
Finished Mar 17 12:30:05 PM PDT 24
Peak memory 201412 kb
Host smart-3afb1511-0b1d-44d1-819d-8a97930b043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748204713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2748204713
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.707485656
Short name T412
Test name
Test status
Simulation time 3023734173 ps
CPU time 2.06 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:29:07 PM PDT 24
Peak memory 201436 kb
Host smart-29af3d57-50e4-4376-9c07-c4f718f8c56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707485656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.707485656
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.771355726
Short name T523
Test name
Test status
Simulation time 5893427019 ps
CPU time 7.71 seconds
Started Mar 17 12:29:20 PM PDT 24
Finished Mar 17 12:29:28 PM PDT 24
Peak memory 201564 kb
Host smart-07ed7c02-802d-4a46-8cfa-9098e913430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771355726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.771355726
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.97870746
Short name T340
Test name
Test status
Simulation time 562293734 ps
CPU time 0.78 seconds
Started Mar 17 12:25:43 PM PDT 24
Finished Mar 17 12:25:44 PM PDT 24
Peak memory 201504 kb
Host smart-5a8220ab-c562-4f21-9900-0ebfe1d19405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97870746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.97870746
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3524135820
Short name T758
Test name
Test status
Simulation time 171021654086 ps
CPU time 99.35 seconds
Started Mar 17 12:27:24 PM PDT 24
Finished Mar 17 12:29:04 PM PDT 24
Peak memory 200408 kb
Host smart-c6897a53-5bb8-4673-98a0-e490065a2bc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524135820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3524135820
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4178049209
Short name T447
Test name
Test status
Simulation time 302201309064 ps
CPU time 725.38 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:39:45 PM PDT 24
Peak memory 201640 kb
Host smart-ca45c3e5-13a9-4714-9c93-5cb189387f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178049209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4178049209
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3689524497
Short name T41
Test name
Test status
Simulation time 157985456923 ps
CPU time 198.18 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:31:17 PM PDT 24
Peak memory 199928 kb
Host smart-0415de75-0a52-4c18-a9c7-115eb2440ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689524497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3689524497
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3549125199
Short name T529
Test name
Test status
Simulation time 327792820251 ps
CPU time 134.06 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:29:55 PM PDT 24
Peak memory 201644 kb
Host smart-4279de31-95fb-497f-bd4d-211455882f69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549125199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3549125199
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3437636049
Short name T765
Test name
Test status
Simulation time 499192623905 ps
CPU time 295.16 seconds
Started Mar 17 12:25:41 PM PDT 24
Finished Mar 17 12:30:37 PM PDT 24
Peak memory 201880 kb
Host smart-662f8e4f-6796-4cfd-bdeb-76692bb22975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437636049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3437636049
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1274960652
Short name T371
Test name
Test status
Simulation time 328912385962 ps
CPU time 690.28 seconds
Started Mar 17 12:27:59 PM PDT 24
Finished Mar 17 12:39:31 PM PDT 24
Peak memory 201656 kb
Host smart-1da4a2bc-f1b4-4243-be83-b8b7d800bf71
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274960652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1274960652
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.590853877
Short name T207
Test name
Test status
Simulation time 406675481536 ps
CPU time 246.48 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:32:05 PM PDT 24
Peak memory 199532 kb
Host smart-6ee12b59-dacc-4211-ac40-3efd52504172
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590853877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.590853877
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3580459176
Short name T519
Test name
Test status
Simulation time 400448517773 ps
CPU time 124.84 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:29:45 PM PDT 24
Peak memory 201632 kb
Host smart-fd6ba1b8-6bd5-4750-b446-71327ffee009
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580459176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3580459176
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1871794832
Short name T411
Test name
Test status
Simulation time 115653686185 ps
CPU time 575.95 seconds
Started Mar 17 12:27:24 PM PDT 24
Finished Mar 17 12:37:01 PM PDT 24
Peak memory 200848 kb
Host smart-ea4256e8-c29a-4dab-8666-3f16713cb297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871794832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1871794832
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2272236397
Short name T382
Test name
Test status
Simulation time 23062594194 ps
CPU time 55.3 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:28:27 PM PDT 24
Peak memory 201456 kb
Host smart-874ca299-7822-4bdb-a79d-1fa3ba8b1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272236397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2272236397
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1675085201
Short name T357
Test name
Test status
Simulation time 3352853887 ps
CPU time 2.71 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:28:08 PM PDT 24
Peak memory 201172 kb
Host smart-c25e0269-99bb-4de8-95a6-4587668e3adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675085201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1675085201
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2745904569
Short name T384
Test name
Test status
Simulation time 5965026625 ps
CPU time 3.62 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:28:02 PM PDT 24
Peak memory 200448 kb
Host smart-f628a295-43a1-4f7f-b844-a4bf4719defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745904569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2745904569
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.92742749
Short name T172
Test name
Test status
Simulation time 180019993774 ps
CPU time 227.81 seconds
Started Mar 17 12:27:58 PM PDT 24
Finished Mar 17 12:31:47 PM PDT 24
Peak memory 199968 kb
Host smart-dc4f11fb-c8ef-438d-9c6e-68dbcc85504e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92742749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.92742749
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2441222308
Short name T524
Test name
Test status
Simulation time 435980507 ps
CPU time 1.18 seconds
Started Mar 17 12:27:14 PM PDT 24
Finished Mar 17 12:27:16 PM PDT 24
Peak memory 200540 kb
Host smart-aa8db395-ba5b-42a5-8c9b-fc71e6e03db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441222308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2441222308
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3786615544
Short name T112
Test name
Test status
Simulation time 322300496395 ps
CPU time 75 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:29:21 PM PDT 24
Peak memory 201368 kb
Host smart-48db52c6-4cf3-41d0-a22b-2bef9b4e8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786615544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3786615544
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1073590764
Short name T605
Test name
Test status
Simulation time 329691491989 ps
CPU time 173.3 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:30:26 PM PDT 24
Peak memory 201660 kb
Host smart-56161a45-0ba0-47ac-9325-995f9b58cf82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073590764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1073590764
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.881109913
Short name T453
Test name
Test status
Simulation time 159151419898 ps
CPU time 95.23 seconds
Started Mar 17 12:25:56 PM PDT 24
Finished Mar 17 12:27:31 PM PDT 24
Peak memory 201908 kb
Host smart-6da4fe49-7600-4a66-998e-c40135bc6a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881109913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.881109913
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.493835160
Short name T337
Test name
Test status
Simulation time 491104206299 ps
CPU time 1096.14 seconds
Started Mar 17 12:25:54 PM PDT 24
Finished Mar 17 12:44:11 PM PDT 24
Peak memory 201656 kb
Host smart-261c277d-6c45-4f77-902a-f26c2595b976
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=493835160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.493835160
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1294451398
Short name T496
Test name
Test status
Simulation time 355724390131 ps
CPU time 228.68 seconds
Started Mar 17 12:25:49 PM PDT 24
Finished Mar 17 12:29:38 PM PDT 24
Peak memory 201920 kb
Host smart-109b198e-bba9-4bf3-8808-8b3d57ed4d19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294451398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1294451398
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3378436925
Short name T336
Test name
Test status
Simulation time 201397703899 ps
CPU time 466.54 seconds
Started Mar 17 12:25:56 PM PDT 24
Finished Mar 17 12:33:42 PM PDT 24
Peak memory 201960 kb
Host smart-7694d52e-2a79-4a4e-bfb8-5664924f7375
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378436925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3378436925
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3451592667
Short name T741
Test name
Test status
Simulation time 78372354521 ps
CPU time 286.09 seconds
Started Mar 17 12:27:32 PM PDT 24
Finished Mar 17 12:32:19 PM PDT 24
Peak memory 202024 kb
Host smart-93832769-bbb2-452f-b451-f260ae76039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451592667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3451592667
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4140048886
Short name T430
Test name
Test status
Simulation time 35211333610 ps
CPU time 87.8 seconds
Started Mar 17 12:25:55 PM PDT 24
Finished Mar 17 12:27:23 PM PDT 24
Peak memory 201732 kb
Host smart-50c0c0a5-b90a-44c8-8e70-35fcc5536cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140048886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4140048886
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4238020335
Short name T678
Test name
Test status
Simulation time 3094766194 ps
CPU time 2.52 seconds
Started Mar 17 12:27:39 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 201372 kb
Host smart-dd43b54c-a3e3-40fd-b5ea-004c4d8a4698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238020335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4238020335
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.731687778
Short name T727
Test name
Test status
Simulation time 5845460556 ps
CPU time 4.51 seconds
Started Mar 17 12:28:06 PM PDT 24
Finished Mar 17 12:28:10 PM PDT 24
Peak memory 201208 kb
Host smart-6c1f6af5-b739-43ad-b923-065ca7c3e04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731687778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.731687778
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1514243367
Short name T110
Test name
Test status
Simulation time 172577214562 ps
CPU time 102.35 seconds
Started Mar 17 12:27:33 PM PDT 24
Finished Mar 17 12:29:15 PM PDT 24
Peak memory 201688 kb
Host smart-a521074e-1da5-447a-b2c3-198fdd575786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514243367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1514243367
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3471441376
Short name T401
Test name
Test status
Simulation time 369337506 ps
CPU time 1.5 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:28:00 PM PDT 24
Peak memory 199596 kb
Host smart-7f388d9a-17d9-4746-b217-fe0f2a6d67d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471441376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3471441376
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.57139417
Short name T224
Test name
Test status
Simulation time 328222381116 ps
CPU time 381.12 seconds
Started Mar 17 12:26:05 PM PDT 24
Finished Mar 17 12:32:27 PM PDT 24
Peak memory 201768 kb
Host smart-825c7754-7452-4270-8677-00f6a789fe6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57139417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gating
.57139417
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3404411088
Short name T221
Test name
Test status
Simulation time 499763332898 ps
CPU time 292.86 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:32:52 PM PDT 24
Peak memory 199948 kb
Host smart-a947ac73-1649-49ca-a7a0-0d09eb499a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404411088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3404411088
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3879799423
Short name T701
Test name
Test status
Simulation time 330181121503 ps
CPU time 205.51 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:31:06 PM PDT 24
Peak memory 201724 kb
Host smart-e89c65ac-74fb-4187-b38c-839246c015b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879799423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3879799423
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3155018667
Short name T632
Test name
Test status
Simulation time 167452043998 ps
CPU time 114.03 seconds
Started Mar 17 12:27:28 PM PDT 24
Finished Mar 17 12:29:22 PM PDT 24
Peak memory 201360 kb
Host smart-04ed7551-a3c3-460e-aefe-e2f64458bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155018667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3155018667
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.104056144
Short name T436
Test name
Test status
Simulation time 493830044735 ps
CPU time 1177.8 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:47:51 PM PDT 24
Peak memory 201604 kb
Host smart-684bfce2-fa7c-479f-b497-19924bb15609
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=104056144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.104056144
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1128755960
Short name T278
Test name
Test status
Simulation time 359323908610 ps
CPU time 795.5 seconds
Started Mar 17 12:25:58 PM PDT 24
Finished Mar 17 12:39:14 PM PDT 24
Peak memory 201820 kb
Host smart-ea8dccbb-673d-4f4e-930b-8b7aa3a7c0a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128755960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1128755960
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3840908800
Short name T698
Test name
Test status
Simulation time 386673726700 ps
CPU time 106.9 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:29:21 PM PDT 24
Peak memory 201688 kb
Host smart-33f04ef4-823c-46c2-807b-8a8af4a19cdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840908800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3840908800
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2063656275
Short name T332
Test name
Test status
Simulation time 24359666349 ps
CPU time 59.11 seconds
Started Mar 17 12:25:56 PM PDT 24
Finished Mar 17 12:26:55 PM PDT 24
Peak memory 201544 kb
Host smart-ac275422-3b5b-4629-a54a-1e62a8c2922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063656275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2063656275
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3893689325
Short name T385
Test name
Test status
Simulation time 3436393216 ps
CPU time 4.36 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:28:17 PM PDT 24
Peak memory 201412 kb
Host smart-c2f0bd2e-50ce-4685-bbf7-512e78d79a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893689325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3893689325
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1142095670
Short name T546
Test name
Test status
Simulation time 5707950102 ps
CPU time 13.41 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:28:12 PM PDT 24
Peak memory 199736 kb
Host smart-c016cc44-fb5a-4e85-8ee3-dbbd9051a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142095670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1142095670
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3961093744
Short name T161
Test name
Test status
Simulation time 334029909755 ps
CPU time 189.22 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:31:08 PM PDT 24
Peak memory 200376 kb
Host smart-30021c9f-5216-4ff5-827f-ef84b84016b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961093744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3961093744
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4175655332
Short name T264
Test name
Test status
Simulation time 854906010392 ps
CPU time 319.65 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:33:00 PM PDT 24
Peak memory 211228 kb
Host smart-e506f35e-ad6a-4b77-9cde-15c960fd5c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175655332 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4175655332
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2306313361
Short name T390
Test name
Test status
Simulation time 428670171 ps
CPU time 0.96 seconds
Started Mar 17 12:28:02 PM PDT 24
Finished Mar 17 12:28:04 PM PDT 24
Peak memory 201232 kb
Host smart-eea473fa-14eb-4c1b-a05a-e7fd638a9b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306313361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2306313361
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1089254655
Short name T214
Test name
Test status
Simulation time 327216381710 ps
CPU time 187.74 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:30:43 PM PDT 24
Peak memory 201392 kb
Host smart-5ad8c230-c764-4e66-86e5-78c70706f53d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089254655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1089254655
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2452403612
Short name T568
Test name
Test status
Simulation time 487884678190 ps
CPU time 1084.06 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:46:02 PM PDT 24
Peak memory 200240 kb
Host smart-afbc37de-b7c6-4859-845a-7b02aee12acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452403612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2452403612
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1266322565
Short name T700
Test name
Test status
Simulation time 326568008335 ps
CPU time 88.95 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:27:39 PM PDT 24
Peak memory 201688 kb
Host smart-e3ddbebc-8a86-4789-b299-728a6aad735c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266322565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1266322565
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.4193334707
Short name T588
Test name
Test status
Simulation time 164137841355 ps
CPU time 182.13 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:29:12 PM PDT 24
Peak memory 201736 kb
Host smart-37b567d8-8d16-4c00-9ff1-26b79410013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193334707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.4193334707
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3580990147
Short name T345
Test name
Test status
Simulation time 163620723605 ps
CPU time 87.23 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:29:08 PM PDT 24
Peak memory 201624 kb
Host smart-36cb1c97-3720-4015-a6f0-c75fabb21f00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580990147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3580990147
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2286407485
Short name T534
Test name
Test status
Simulation time 337760186987 ps
CPU time 189.57 seconds
Started Mar 17 12:27:34 PM PDT 24
Finished Mar 17 12:30:43 PM PDT 24
Peak memory 201636 kb
Host smart-b03c2e15-9766-44d4-becd-4d00d3ed6344
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286407485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2286407485
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3777938055
Short name T149
Test name
Test status
Simulation time 205057052428 ps
CPU time 115.48 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:29:14 PM PDT 24
Peak memory 200384 kb
Host smart-cf67aaa5-c9da-46f1-9bcf-4676b3ed81ea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777938055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3777938055
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2127157563
Short name T655
Test name
Test status
Simulation time 86549861585 ps
CPU time 297.89 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:33:01 PM PDT 24
Peak memory 201980 kb
Host smart-89b2a83b-c9fb-4a21-8f1f-d69ec2eda1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127157563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2127157563
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.307390661
Short name T697
Test name
Test status
Simulation time 24852127529 ps
CPU time 54.78 seconds
Started Mar 17 12:27:18 PM PDT 24
Finished Mar 17 12:28:14 PM PDT 24
Peak memory 200244 kb
Host smart-bd5fba25-9b3a-4208-85d3-bca5c3462a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307390661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.307390661
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2320105281
Short name T612
Test name
Test status
Simulation time 4768195335 ps
CPU time 11.65 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:28:15 PM PDT 24
Peak memory 201424 kb
Host smart-47583193-4c23-4069-b06c-7c71e531942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320105281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2320105281
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1934062306
Short name T383
Test name
Test status
Simulation time 5557357306 ps
CPU time 3.99 seconds
Started Mar 17 12:27:40 PM PDT 24
Finished Mar 17 12:27:44 PM PDT 24
Peak memory 201452 kb
Host smart-9933e609-602f-4aae-98a8-d12264ba3f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934062306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1934062306
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3208223532
Short name T306
Test name
Test status
Simulation time 329057055127 ps
CPU time 191.56 seconds
Started Mar 17 12:27:28 PM PDT 24
Finished Mar 17 12:30:39 PM PDT 24
Peak memory 201288 kb
Host smart-c27689b8-1bf5-472b-89e7-138285198997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208223532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3208223532
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.526927575
Short name T16
Test name
Test status
Simulation time 60032678659 ps
CPU time 126.26 seconds
Started Mar 17 12:26:09 PM PDT 24
Finished Mar 17 12:28:16 PM PDT 24
Peak memory 210032 kb
Host smart-76e8becc-fe47-491e-b403-5c292ba0300d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526927575 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.526927575
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1919446764
Short name T689
Test name
Test status
Simulation time 520338492 ps
CPU time 1.66 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:27:37 PM PDT 24
Peak memory 201140 kb
Host smart-a7b35014-0436-4fac-9302-79708bba6ba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919446764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1919446764
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2766950718
Short name T133
Test name
Test status
Simulation time 379100971622 ps
CPU time 411.11 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:34:27 PM PDT 24
Peak memory 201420 kb
Host smart-2b274914-771b-4475-9e3d-a1a4e521fa08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766950718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2766950718
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3749188154
Short name T740
Test name
Test status
Simulation time 514033258318 ps
CPU time 240.66 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:31:36 PM PDT 24
Peak memory 201512 kb
Host smart-a3d41437-d702-4a2f-91b3-e42d608548b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749188154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3749188154
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2781106290
Short name T202
Test name
Test status
Simulation time 488006120542 ps
CPU time 403.3 seconds
Started Mar 17 12:28:02 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 201600 kb
Host smart-0bc4d64e-825f-4a7b-a4d3-4769b70b9073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781106290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2781106290
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.533264763
Short name T739
Test name
Test status
Simulation time 169516213271 ps
CPU time 365.01 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:33:40 PM PDT 24
Peak memory 201428 kb
Host smart-b1e742e4-d13d-4565-8dc6-3cd9067d3360
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=533264763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.533264763
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.679089343
Short name T413
Test name
Test status
Simulation time 160673491726 ps
CPU time 100.41 seconds
Started Mar 17 12:28:03 PM PDT 24
Finished Mar 17 12:29:44 PM PDT 24
Peak memory 201648 kb
Host smart-265c7f4c-7b8c-4d44-a9ce-9a59fab9d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679089343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.679089343
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3937025353
Short name T475
Test name
Test status
Simulation time 486956014476 ps
CPU time 572.96 seconds
Started Mar 17 12:26:10 PM PDT 24
Finished Mar 17 12:35:43 PM PDT 24
Peak memory 201728 kb
Host smart-9107f9d3-fc62-469a-9db8-b3dc67d84029
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937025353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3937025353
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3775302958
Short name T774
Test name
Test status
Simulation time 609437200846 ps
CPU time 1454.89 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:50:23 PM PDT 24
Peak memory 201696 kb
Host smart-32ddbc31-caf0-4ebb-80d9-2976186d54be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775302958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3775302958
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1600746990
Short name T50
Test name
Test status
Simulation time 70259093417 ps
CPU time 239.61 seconds
Started Mar 17 12:27:35 PM PDT 24
Finished Mar 17 12:31:35 PM PDT 24
Peak memory 201744 kb
Host smart-beef7599-0c9e-40f9-bb14-7e1db1ec8b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600746990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1600746990
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.1352321912
Short name T742
Test name
Test status
Simulation time 29542825911 ps
CPU time 15.98 seconds
Started Mar 17 12:27:25 PM PDT 24
Finished Mar 17 12:27:41 PM PDT 24
Peak memory 200648 kb
Host smart-41bf57fa-6f40-43d4-91dd-a95aa696c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352321912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.1352321912
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.984466366
Short name T360
Test name
Test status
Simulation time 4564163951 ps
CPU time 1.88 seconds
Started Mar 17 12:26:09 PM PDT 24
Finished Mar 17 12:26:11 PM PDT 24
Peak memory 201484 kb
Host smart-bfab1beb-cb28-492a-bd42-b1b8fbb6597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984466366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.984466366
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1855530405
Short name T378
Test name
Test status
Simulation time 5794064460 ps
CPU time 2.46 seconds
Started Mar 17 12:27:29 PM PDT 24
Finished Mar 17 12:27:32 PM PDT 24
Peak memory 201104 kb
Host smart-b9a2c083-1440-4c46-b6b4-544287ac3d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855530405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1855530405
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3884690786
Short name T266
Test name
Test status
Simulation time 337332348214 ps
CPU time 60.67 seconds
Started Mar 17 12:27:37 PM PDT 24
Finished Mar 17 12:28:38 PM PDT 24
Peak memory 201660 kb
Host smart-7163c1b9-0460-4619-a743-5ab880116058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884690786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3884690786
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2808656606
Short name T559
Test name
Test status
Simulation time 47715790315 ps
CPU time 119.4 seconds
Started Mar 17 12:27:38 PM PDT 24
Finished Mar 17 12:29:37 PM PDT 24
Peak memory 210376 kb
Host smart-b6d99003-de2f-42ce-b4df-ffd82bea932e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808656606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2808656606
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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